KR20110119375A - Shift register - Google Patents

Abstract

PURPOSE: A shift register is provided to make loads of lines the same wherein a plurality of start pulses is supplied to the lines, thereby synchronizing rising time with fall time. CONSTITUTION: A plurality of stages(S1~Sn) includes a plurality of switching devices and successively outputs scan pulses(Vout1~Voutn). A pull-up switching device is turned on/off according to a signal state of a set node. The pull-down switching device connects a low potential power supply line. A first switching device is turned on/off by a scan pulse. Each stage receives one of start pulses(Vst1,Vst2).

Description

Shift register {SHIFT REGISTER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register, and more particularly, to a shift register capable of reducing an image quality defect due to a load difference between respective lines supplied with start pulses by changing a structure in which a plurality of start pulses are supplied.

Recently, a GIP (Gate In Panel) type display device, in which a gate driving circuit is embedded in a panel, reduces a volume and weight of a display device and lowers manufacturing cost.

In the conventional GIP type display device, the gate driving circuit includes a shift register having a plurality of stages for sequentially supplying scan pulses to the plurality of gate lines. Such a shift register receives a plurality of start pulses, for example, first and second start pulses having different phase differences through two transmission lines. At this time, the odd-numbered stages sequentially output scan pulses in response to the first start pulse, and the even-numbered stages sequentially output the scan pulses in response to the second start pulse. To this end, the first stage is supplied with a first start pulse and the second stage is supplied with a second start pulse.

On the other hand, each stage has a pull-up switching element which outputs a clock pulse provided as a scan pulse from the timing controller according to the signal state of the set node. At this time, the whole stage uses a start pulse to initialize the set node to a low voltage state at the start of every frame.

This shift register is supplied with a first start pulse to the entire stage for initialization of the set node. That is, the first start pulse is supplied to the entire stage, and the second start pulse is supplied only to the second stage. This resulted in a load difference between the transmission lines supplied with the first and second start pulses. The load difference between the lines to which the first and second start pulses are supplied has a problem of affecting the scan pulses output from each stage, thereby causing an image quality defect.

An object of the present invention is to provide a shift register that can reduce image quality defects due to a load difference of each line to which start pulses are supplied by changing a structure in which a plurality of start pulses are supplied. have.

In order to achieve the above object, a shift register according to an exemplary embodiment of the present invention includes a plurality of stages that sequentially output scan pulses with a plurality of switching elements, and each of the plurality of stages has a different phase difference. Any one of a plurality of start pulses may be supplied, and adjacent stages may be supplied with start pulses having different phase differences.

The plurality of start pulses may be sequentially delayed in phase and exhibit only one high state at the beginning of each frame.

The start pulses supplied to the neighboring stages have a phase difference of one horizontal period from each other.

The plurality of start pulses include first and second start pulses having different phase differences, wherein the first start pulses are commonly supplied to odd-numbered stages, and the second start pulses are common to even-numbered stages. It is characterized in that the supply.

The number of odd-numbered stages and the total number of even-numbered stages are the same.

The k-th stage is turned on or off according to the signal state of the set node, and a pull-up switching element which connects one of the clock transmission lines and the output terminal of the k-th stage to each other during turn-on; It is turned on or off according to the signal state of the clock pulse supplied to the pull-up switching element and the clock pulse inverted by 180 degrees, and connects the low potential power supply line and the output terminal of the k-th stage at turn-on. A first switching device which is turned on or off in response to a scan pulse provided from the k-th stage, and which connects an output terminal of the k-th stage to the set node during turn-on; An element and one of the first and second start pulses, which are turned on or off depending on the signal state of the provided start pulse, and at turn-on between the low potential power supply line and the set node A second switching element to be connected, and a third switching element which is turned on or off according to a scan pulse provided from the k + 2 stage, and which connects between the low potential power supply line and the set node when turned on; And turned on or off according to a signal state of a clock pulse delayed by one horizontal period than a clock pulse supplied to the pull-up switching element, and is connected between an output terminal of the k-1th stage and the set node. It is characterized by including the 4th switching element to connect.

In the shift register according to the present invention, the rise and fall times of the scan pulse output from the shift register are equalized by equalizing the loads of the respective lines to which the start pulses are supplied. As a result, image quality defects due to differences in rise and fall times of each scan pulse can be reduced.

1 is a block diagram of a shift register according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of any k-th stage shown in FIG. 1. FIG.
3 is an output waveform diagram of the first, third and fifth stages shown in FIG.
4A and 4B are simulation waveforms for comparing the shift register of the prior art and the present invention.

Hereinafter, the shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram of a shift register according to a first embodiment of the present invention.

Referring to FIG. 1, a shift register according to an embodiment of the present invention may receive a plurality of scan pulses in response to a plurality of clock pulses and a plurality of start pulses provided from a timing controller. Output sequentially. For this purpose, the shift register includes first to nth stages S1 to Sn. The shift register sequentially outputs scan pulses Vout1 to Voutn from the first stage S1 to the nth stage Sn. Here, the plurality of clock pulses may include first to fourth clock pulses CLK1 to CLK4 outputted with different phase differences, and the start pulses may be output with first and second start pulses Vst1 and Vst2 having different phase differences. ).

Each stage S1 to Sn receives one of the clock pulses CLK1 to CLK4, one of the start pulses Vst1 and Vst2, and a high potential power source and a low potential power source VDD and VSS. At this time, adjacent stages receive different clock pulses and different start pulses.

The first to fourth clock pulses CLK1 to CLK4 circulate with different phase differences. Each clock pulse CLK1 to CLK4 goes high for two horizontal periods. In addition, the first to fourth clock pulses CLK1 to CLK4 are output after being delayed by one horizontal period from each other. Meanwhile, in the embodiment of the present invention, the clock pulse includes four clock pulses having different phase differences, but any number of clock pulses may be used.

The first and second start pulses Vst1 and Vst2 are output with different phase differences and exhibit only one high state at the beginning of every frame. These first and second start pulses Vst1 and Vst2 exhibit a high state for two horizontal periods, and have a phase difference delayed by one horizontal period from each other. On the other hand, in the embodiment of the present invention, although the start pulse includes two kinds of start pulses having different phase differences, any number of start pulses may be used.

The high potential power supply VDD and the low potential power supply VSS are DC voltages, and the high potential power supply VDD has a higher potential than the low potential power supply VSS. For example, the high potential power source VDD may exhibit positive polarity, and the low potential power source VSS may exhibit negative polarity. On the other hand, the low potential power supply (VSS) may be a ground voltage. The low potential power supply VSS is equal to the potential of the low state of the clock pulse CLK.

The k-th stage Sk is initialized to stabilize the scan pulse output from the k-th stage Sk at the start of every frame. To this end, the k-th stage Sk receives one of the first and second start pulses Vst1 and Vst2 at the start of each frame. At this time, the k-th stage Sk receives a start pulse different from the start pulses provided to the neighboring k-1 and k + 1 stages Sk-1 and Sk + 1. However, the first stage S1 receives the first start pulse Vst1 and the second stage S2 receives the second start pulse Vst2, but the first and second stages S1 and S2 Do not use it for initialization.

After completing the initialization, the k-th stage Sk pre-sets the set node Q in response to the k-th scan pulse Voutk-2 provided from the stage before the second stage, that is, the k-th stage Sk-2. -Charge it. However, the first stage S1 receives the first start pulse Vst1, and the second stage S2 receives the second start pulse Vst2. In other words, the first and second stages S1 and S2 are used to pre-charge the set node Q without using the first and second start pulses Vst1 and Vst2 for initialization of the stage. Here, the operation of pre-charging the set node Q will be described later.

After pre-charging the set node Q, the k-th stage Sk receives the clock pulse in the high state to output the k-th scan pulse Voutk in the high state. The k-th stage Sk is a k-th scan pulse Voutk in a low state in response to the k + 2th scan pulse Voutk + 2 of the stage after the second stage, that is, the k + 2th stage Sk + 2. Outputs However, the n-th and nth stages Sn-1 and Sn receive scan pulses from the first and second dummy stages not shown.

In this way, the k-th stage Sk receives the first start pulse Vst1 or the second start pulse Vst2 and initializes at the start of each frame. The first and second stages are exceptions. Also, the k-th stage Sk pre-charges the set node Q in response to the scan pulse Voutk-2 provided from the stage Sk-2 before the second stage, and the stage Sk + after the second stage. The k th scan pulse Voutk in the low state is output in response to the scan pulse Voutk + 2 provided from 2).

This k-th stage has the following configuration.

FIG. 2 is a schematic diagram of any k-th stage shown in FIG. 1.

Referring to FIG. 2, the k-th stage includes a pull-up switching device Tu, a pull-down switching device Td, and first to fourth switching devices T1 to T4.

The pull-up switching device Tu is turned on or turned off according to the signal state of the set node Q, and outputs a scan pulse through an output terminal at turn-on. At this time, the pull-up switching device Tu receives one of the first to fourth clock pulses CLK1 to CLK4 and outputs it as a scan pulse.

The pull-down switching device Td is controlled according to a clock pulse delayed by two horizontal periods than the clock pulse provided to the pull-up switching device Tu. Since each of the clock pulses CLK1 to CLK4 is high for two horizontal periods, the clock pulses provided to the pull-up switching element Tu and the clock pulses delayed by two horizontal periods are inverted by 180 degrees. Therefore, the pull-down switching device Td is turned on or off depending on the signal state of the clock pulse supplied to the pull-up switching device Tu and the clock pulse inverted by 180 degrees. The pull-down switching device Td connects the low potential power supply line and the output terminal to each other at turn-on.

The first switching element T1 is turned on or off according to the scan pulse Voutk-2 provided from the k-2th stage Sk-2, and when turned on, the k-2th stage Sk-2 Is connected between the set output terminal of the output terminal However, the first switching device T1 provided in the first and second stages S1 and S2 receives one of the first and second start pulses Vst1 and Vst2 and is turned-on according to the provided start pulses. It is turned on or off.

The second switching element T2 receives one of the first and second start pulses Vst1 and Vst2 and is turned on or off according to the signal state of the provided start pulse. The second switching element T2 connects the low potential power supply line and the set node Q at turn-on. However, the first and second stages S1 and S2 do not include the second switching element T2.

The third switching element T3 is turned on or off according to the scan pulse Voutk + 2 provided from the k + 2th stage Sk + 2, and at turn-on, the low potential power supply line and the set node ( Q) is connected.

The fourth switching element T5 is turned on or off according to the clock pulse delayed by one horizontal period than the clock pulse supplied to the pull-up switching element Tu. The fourth switching device T5 connects between the output terminal of the k-th stage Sk-1 and the set node Q at turn-on.

The operation of the k-th stage Sk configured as described above will be described in detail as follows.

FIG. 3 is an output waveform diagram of the first, third, and fifth stages shown in FIG. 1.

Here, since the operation of each stage is the same, an operation of the third stage S3 will be described with reference to FIGS. 2 and 3.

First, in the third stage S3, the first start pulse Vst1 having a high state is supplied to the gate electrode of the second switching element T2 in the initialization period A. Then, the second switching element T2 is turned on and the low potential power VSS is supplied to the set node Q3 through the second switching element T2. Accordingly, the set node Q3 is initialized to the low state. On the other hand, in the initialization period A, the first start pulse Vst1 in the high state is simultaneously supplied to the odd-numbered stages S1, S3, S5, S7, S9... The remaining odd stages S3, S5, S7, and S9... Except for the first stage S1 initialize each set node Q to a low state. Here, the first stage S1 receives the first start pulse Vst1 in the high state to the gate electrode of the first switching element T1 to pre-charge the set node Q1.

In the third stage S3, the first scan pulse Vout1 in the high state provided from the first stage S1 is applied to the gate electrode of the first switching element T1 in the set period B after the initialization period A. Supplied. Then, the first switching element T1 is turned on and the first scan pulse Vout1 having a high state is supplied to the set node Q3 through the first switching element T1. The set node Q3 is thus pre-charged to the high state.

In the third stage S3, the third clock pulse CLK3 having a high state is supplied to the drain electrode of the pull-up switching device Tu in the output period C after the set period B. Accordingly, the voltage of the set node Q3 pre-charged by the parasitic capacitor Cgd between the gate electrode and the drain electrode of the pull-up switching element Tu is bootstrapping. Accordingly, the pull-up switching device Tu is completely turned on, and the third clock pulse CLK3 in the high state is turned on by the third scan pulse Vout3 through the turned-on pull-up switching device Tu. Is supplied to the output terminal. On the other hand, the third scan pulse Vout3 in the high state output in the output period C of the third stage S3 is supplied to the first switching element T1 of the fifth stage S5, and thus the fifth stage ( The set node Q5 of S5 is pre-charged. In addition, the third scan pulse Vout3 having the high state is supplied to the gate electrode of the third switching element T3 of the first stage S1, thereby bringing the set node Q1 of the first stage S1 into the low state. Reset it.

In the third stage S3, the fifth scan pulse Vout in the high state is supplied to the gate electrode of the third switching element T3 in the reset period D after the output period C. Then, the third switching device T3 is turned on and the low potential power VSS is supplied to the set node Q3 through the third switching device T3. Accordingly, the set node Q3 is reset to the low state.

Meanwhile, in the exemplary embodiment of the present invention, the odd-numbered stages S1, S3, S5, S7, S9... Which are supplied with the first start pulse Vst1 are described, but the even-numbered stage that is supplied with the second start pulse Vst2 is described. The operations of the stages S2, S4, S6, S8, S10 ... are also the same as the odd stages S1, S3, S5, S7, S9. In addition, similar to the first stage S1, the second stage S2 receives the second start pulse Vst2 in a high state from the gate electrode of the first switching element T1 to pre-set the set node Q2. Take it up.

As such, the shift register according to the present invention is supplied with the first and second start pulses Vst having different phase differences to initialize the set node Q. At this time, the first start pulse Vst1 is supplied to the odd-numbered stages S1, S3, S5, S7, S9... And the second start pulse Vst2 is the even-numbered stages S2, S4, S6, S8, S10. ...). At this time, the total number of odd-numbered stages S1, S3, S5, S7, S9... And the even-numbered stages S2, S4, S6, S8, S10. That is, the loads of the transmission lines to which the first and second start pulses Vst1 and Vst2 are supplied are equal. Accordingly, it is possible to reduce image quality defects caused by the load difference of the line through which the start pulse is transmitted.

4A and 4B are simulation waveforms for comparing the shift register of the prior art and the present invention.

Referring to FIG. 4A, it can be seen that the conventional first start pulse Vst1 and the second start pulse Vst2 have different rise times due to the difference in the loads connected to the respective stages. In addition, it can be seen that the rise times of the first scan pulse Vout1 and the second scan pulse Vout2 output in response to the first start pulse Vst1 and the second start pulse Vst2 are different.

4B, the first start pulse Vst1 and the second start pulse Vst2 according to the present invention have the same rise time because the loads connected to the respective stages are the same, and the first scan pulse Vout1 It can be seen that the rise time of the second scan pulse Vout2 is the same.

Conventional Structure Invention Vst1 rise time 25.2us 1.5us Vst2 rise time 1.2us 1.5us Vout1 Rise Time 6.2us 5.7us Vout2 Rise Time 5.5us 5.7us

Specifically, referring to Table 1, conventionally, the rise times of the first start pulse Vst1 and the second start pulse Vst2 are 25.2us // 1.2us, respectively, and the first scan pulse Vout1 and the second scan are respectively. It can be seen that the rise times of the pulses Vout2 are 6.2us // 5.5us respectively. On the other hand, in the present invention, the rise times of the first start pulse Vst1 and the second start pulse Vst2 are 1.5us // 1.5us, respectively, and the rise of the first scan pulse Vout1 and the second scan pulse Vout2 is increased. There is no difference in time with 5.7us // 5.7us respectively.

As described above, the shift register according to the present invention may equalize the load and the fall time of the scan pulse output from the shift register by equalizing the load of the line through which a plurality of start pulses are transmitted. In addition, since the rise and fall times of the scan pulses are the same, image quality defects due to the difference between the rise and fall times of each scan pulse can be reduced.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

Tu: pull-up switching element Td: pull-down switching element
Q: set nodes

Claims (6)

A plurality of stages having a plurality of switching elements to sequentially output scan pulses,
Each of the plurality of stages receives one of a plurality of start pulses having different phase differences,
A shift register, characterized in that adjacent stages are supplied with start pulses having different phase differences. The method of claim 1,
The plurality of start pulses
A shift register characterized in that the phases are sequentially delayed and exhibit only one high state at the beginning of every frame. The method of claim 2,
And the start pulses supplied to the neighboring stages have one horizontal period phase difference from each other. The method of claim 3, wherein
The plurality of start pulses
A first and second start pulse having different phase differences,
The first start pulse is commonly supplied to the odd-numbered stages,
And the second start pulse is commonly supplied to even-numbered stages. The method of claim 4, wherein
And the total number of odd-numbered stages and the total number of even-numbered stages are the same. The method of claim 5, wherein
K stage
A pull-up switching element which is turned on or turned off according to the signal state of the set node and which connects one of the clock transmission lines and the output terminal of the k-th stage to each other during turn-on;
It is turned on or off according to the signal state of the clock pulse supplied to the pull-up switching element and the clock pulse inverted by 180 degrees, and at the time of turn-on, the low potential power supply line and the output terminal of the k-th stage A pull-down switching element to connect
A first switching element which is turned on or off according to a scan pulse provided from the k-th stage, and which connects an output terminal of the k-th stage between the set node and the set node at turn-on;
Receiving one of the first and second start pulses, and turning on or off according to a signal state of the provided start pulses, and connecting the low potential power supply line and the set node at turn-on time; 2 switching elements,
A third switching element that is turned on or off in accordance with a scan pulse provided from a k + 2 stage, and which connects between the low potential power supply line and the set node when turned on;
It is turned on or off according to the signal state of the clock pulse delayed by one horizontal period than the clock pulse supplied to the pull-up switching element, and is connected between the output terminal of the k-1th stage and the set node at turn-on. And a fourth switching element.

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