KR20110117582A - System and device for succesive matrix transposes - Google Patents

Abstract

The present invention relates to a system and apparatus for continuously transposing a matrix. The present invention includes a plurality of data storage units arranged in a two-dimensional structure with X rows and Y columns. The invention also includes a recording control connected to the input of the plurality of data storages for recording data in the at least one virtual row. The invention also includes a read control coupled to the output of the plurality of data storages for reading data from at least one virtual column, the data being written into the at least one virtual row and read from the at least one virtual column. Data is performed substantially simultaneously during each operating cycle such that the two-dimensional structure is continuously transposed in zero cycle delays between successive transposes.

Description

Continuous Matrix Transpose Systems and Devices {SYSTEM AND DEVICE FOR SUCCESIVE MATRIX TRANSPOSES}

TECHNICAL FIELD The present invention relates to the field of Matrix Transpose, and more particularly, to a system and apparatus for continuously transposing a matrix.

Research on numerical array systems has led to advances in various matrix operations. One such matrix operation is the transpose, represented by M ^T. Where M is the matrix and T is the transpose operation. Matrix transposes are frequently used alterations in linear algebra and are particularly useful for solving complex differential equations.

Currently, various structures are known for methods for transposing the matrix. One of them is memory infrastructure. In this structure, the entire N x N matrix is written to memory by providing sequential addresses from row to row. In addition, the entire N x N matrix is read in columns in the column direction from the memory. This allows reading by appropriate addressing, allowing the desired column element to be read at once.

On the other hand, the N × N matrix can be read by reading the entire column at a point in time within the tolerance of the data width. However, the software burden for writing and reading the N × N matrix is high. This is due to the fact that the memory infrastructure needs to generate an appropriate address in order to access the data in each row and column. Further, in the above structure, when the memory used for writing and reading the N × N matrix is shared memory, it affects the efficiency of the entire memory infrastructure.

Another structure is a transpose buffer infrastructure using an N × N matrix of register pairs, such as a white transpose buffer register and a dark transpose buffer register. The data in this structure is N ² Until the white transpose buffer register is loaded, it is entered into the white transpose buffer register in the row direction. When loading is complete, the data in the white transpose buffer register is copied to the corresponding dark transpose buffer register in column direction. Data is read out from the dark transpose buffer register and the next set of data, written to the white transpose buffer register, is transposed to the dark transpose buffer register. However, the transpose buffer structure includes a latency of (N ² + 1) clock cycles with respect to the first matrix, and is one clock cycle between successive matrix transposes. For example, one clock cycle when writing and reading data. In addition, the transpose buffer structure requires a large area because two sets of N ² registers are used to transpose a block of N ² data.

Dual independent transpose buffer based architecture is another structure currently used for matrix transpose. The dual independent transpose buffer infrastructure has two independent buffers, both buffers being used alternately to successively transpose the matrix. In this structure, the first data set is written to the first buffer in row direction order. The first data set is read in column direction from the first buffer. Also, the second data set is written to the second buffer at the same time as reading the first data set from the first buffer.

Similarly, during the next operating cycle, a third data set is written to the first buffer and the second data set is read from the second buffer. The latency of the dual transpose buffer structure is N ² clock cycles for the first matrix and " 0 " for continuous matrix transposes. For example, one clock cycle when writing and reading data. Although in dual independent transpose buffers, the latency between successive matrix transposes is " 0 " compared to other conventional structures, but the required area is twice that of using two independent buffers.

Therefore, the technical problem to be achieved by the present invention is to provide a transpose device capable of continuous transpose of the matrix.

A system and apparatus for continuous matrix transpose of the present invention is described.

In one aspect of the present invention, the apparatus includes a data storage arranged as a two-dimensional structure, the two-dimensional structure comprising X rows and Y columns, each of which is configured to store data. Contains wealth. The apparatus includes a recording control unit connected to an input of a data storage unit for recording data in at least one virtual row.

The apparatus also includes a read control connected to the output of the data store for reading data from the at least one virtual column. The at least one virtual column corresponds to one of the X rows and Y columns associated with the data store in which data is recorded. At least one virtual row corresponds to one of the X rows and the Y columns associated with the data store from which data was read. In the apparatus, data writing to at least one virtual column and reading data from at least one virtual row are performed substantially simultaneously during each operation cycle. The two-dimensional structure is thereby continuously transposed at zero cycle delay between successive transposes.

In another aspect of the present invention, a two-dimensional Discrete Cosine Transform (DCT) processor includes a first one-dimensional DCT performing a one-dimensional transform of an N x M matrix generating an N x M intermediate transform matrix. It includes. The two-dimensional DCT processor further includes an N × M matrix transpose circuit coupled to the first one-dimensional DCT processor for continuously transposing the intermediate transform matrix in zero cycle delay between successive matrix transposes. The two-dimensional DCT processor includes a second one-dimensional DCT processor for performing one-dimensional transform on the transform of the N × M intermediate transform matrix to produce the desired two-dimensional DCT.

The transpose apparatus according to the embodiment of the present invention has the effect of enabling the continuous transpose of the matrix at zero cycle delay between the continuous matrix transposes.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.
1 is a block diagram of an apparatus for continuously transposing a two-dimensional structure according to an embodiment of the present invention.
FIG. 2 is an exemplary diagram for illustrating a continuous matrix transpose of a 4 × 4 matrix performed by the apparatus shown in FIG. 1.
3 is a timing diagram for four consecutive transposes of a 4 × 4 matrix, according to one embodiment of the invention.
4 is a block diagram of a two-dimensional DCT with an NXM matrix transpose circuit in accordance with an embodiment of the present invention.

Specific structural and functional descriptions of embodiments according to the concepts of the present invention disclosed in this specification or application are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention, The examples may be embodied in various forms and should not be construed as limited to the embodiments set forth herein or in the application.

Embodiments in accordance with the concepts of the present invention can make various changes and have various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to specific forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another, for example, without departing from the scope of rights in accordance with the inventive concept, and the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may exist in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for continuously transposing a two-dimensional structure according to an embodiment of the present invention. The apparatus 100 includes a data storage unit 102, a recording control unit 104, and a read control unit 106. The data store 102 may be a memory device or a register. The data store 102 may be composed of a combination of a memory and a register. Each data storage unit 102 stores, for example, a single bit of data or a plurality of bits of data such as image or video data. The write control unit 104 and read control unit 106 may include combinational logic gates and / or sequential logic elements.

As shown, the recording control unit 104 is connected to an input of the data storage unit 102. The read control unit 106 is connected to the output of the data storage unit 102. In addition, in the present device 100, the data storage 102 is arranged in a two-dimensional structure such as a matrix. For example, a two-dimensional structure includes X rows and Y columns. According to other embodiments of the present invention, the apparatus 100 receives data 108, for example moving image or image pixels, from external means for continuously transposing the data 108. For example, when the apparatus 100 is implemented in a two-dimensional Discrete Cosine Transform (DCT) processor, the apparatus 100 may receive data 108 from a one-dimensional DCT processor of the two-dimensional DCT processor.

Preferably, the recording control unit 104 of the apparatus 100 generates a virtual row selection signal 110 to select virtual rows in a two-dimensional structure. In this embodiment, the virtual rows may be rows or columns in a two-dimensional structure with a set of data stores 102. The recording control unit 104 also records the data 108 in the data stores 102 associated with the selected virtual rows in row wise order. As another embodiment, the write control unit 104 writes the data 108 in the row direction in the X ₁ -X _N rows of the two-dimensional structure during the first X clock cycle based on the column selection signal.

In turn, the read control section 106 generates a virtual column select signal 114 for selecting virtual columns corresponding to the set of storage 102 having data to be read. In the present embodiment, the virtual columns may be columns or rows in a two-dimensional structure having a data storage 102 set. For example, after completion of the first X clock cycle, ie, during the first transpose, the virtual column selection signal 114 may enable selection of Y ₁ -Y _N columns as virtual columns. Thus, read control 106 reads data 108 in column wise order from data store 102 associated with the Y ₁ -Y _N columns. As a result, data 108 of Y ₁ -Y _N columns is transposed to generate transpose data 112.

During the second transpose, the write control 104 generates a virtual column select signal 110 to select virtual columns for recording a new set of data 108. In this case, the virtual columns may be columns of Y ₁ -Y _N. For example, from the columns of Y ₁ -Y _N , data 108 is read substantially simultaneously during the same operating cycle. Thus, the write control unit 104 writes a new set of data 108 to the data storage unit 102 associated with the virtual rows substantially simultaneously with the read operation during the first transpose in row direction order.

Also, during the second transpose, the read control section 106 generates a virtual column select signal 114 for reading data from the virtual columns. Therefore, the read control section 106 selects X _N- X ₁ rows as virtual columns by the virtual column selection signal 114. The read control 106 also reads the new set of data 108 in column direction order from the data store 102 associated with the virtual columns. As a result, data 108 of X _N -X ₁ rows is transposed to produce transpose data 112.

Similarly, during the third transpose, the recording control unit 104 selects X _N -X ₁ rows as virtual rows based on the virtual row selection signal 110. The write control unit 104 then writes a new set of data 108 to the data storage unit 102 associated with the virtual rows in row direction substantially simultaneously with the read operation during the second transpose. In addition, during the third transpose, the recording controller 104 selects the Y _N -Y ₁ columns as the virtual columns and reads the data 108 in the column direction from the data storage 102 associated with the virtual columns. As a result, data 108 in columns Y _N -Y ₁ is transposed to generate transpose data 112.

During the fourth transpose, the read control unit 106 selects the Y _N -Y ₁ column as the virtual columns and connects to the data storage unit 102 associated with the virtual columns in the column order simultaneously with the read operation of the third transpose. Write a new set of data 108. As such, the next continuous transpose cycle in the apparatus 100 continues. The apparatus 100 may perform reading and writing of data in any cycle order by shifting rows and columns in any cycle form. The apparatus 100 successively transposes the data storage 102 arranged in a two-dimensional structure in a zero cycle delay between successive transposes, thereby improving the efficiency of the apparatus 100. . The cycle direction of changing rows and columns for read and write operations can contribute to completing a zero cycle delay between successive transposes of a two-dimensional structure.

FIG. 2 is an exemplary diagram for showing a continuous matrix transpose of a 4 × 4 matrix, performed by the apparatus 100 shown in FIG. In particular, Figure 2 shows the order of reading and writing data that occurs during successive matrix transposes. For example, the transposed matrix includes four rows and four columns, each of the rows and columns including four data stores.

As shown in Figure 2, during the first four clock cycles, data is written in four rows in row order. In a preferred embodiment, the matrix is continuously transposed from the fifth clock cycle. In other words, this is the case where the recording is completed in four rows. Data is read from the column 'C1' during the first transpose. During the second transpose, new data is written to the virtual column. That is, column 'C1' and data are read from a virtual column such as row 'R4'.

During the third transpose, new data is written to the virtual row. That is, the 'R4' row and data are read from a virtual column such as 'C4'. During the fourth transpose, new data is written to a virtual row, such as column 'C4', and data is read from the virtual column, such as row 'R1'. The cycle continuously performs additional matrix transposes. Continuous matrix transpose can be performed by cycle direction changing rows and columns.

This helps to complete the zero cycle delay between successive matrix transposes. Although the above is for data written or read from all data stores contained in rows and columns once per clock cycle, this can show data that can be written or read from each data store every cycle.

3 is a timing diagram for four consecutive transposes of a 4 × 4 matrix, in accordance with an embodiment of the invention. FIG. 3 shows that during the first transpose, data is written to four rows R1-R4 of the matrix in row direction order. When the write operation is completed, data is read from the virtual columns (Columns C1-C4) in column direction order for the next four clock cycles. During the second transpose, new data is written to the virtual rows (columns C1-C4) in row order simultaneously with the read operation associated with the first transpose.

When the write operation is completed during the second transpose, data is read from the virtual columns (rows R4-R1) in column direction order for the next four clock cycles. During the third transpose, new data is written to the virtual rows (rows R4-R1) in row direction order simultaneously with the read operation associated with the second transpose.

When the write operation is completed during the third transpose, the data is read out from the virtual columns (columns C4-C1) in column direction order for the next 4 clock cycles. During the fourth transpose, new data is written to the virtual rows (columns C4-C1) in row direction concurrent with the read operation associated with the third transpose, and the cycle continues for matrix transpose.

4 is a block diagram of a two-dimensional DCT processor with an N X M matrix transpose circuit 404, in accordance with an embodiment of the present invention. 4, the two-dimensional DCT processor 400 includes a first one-dimensional DCT processor 402 (also referred to as a row DCT processor). And, the two-dimensional DCT processor 400 includes an N × M matrix transpose circuit 404 and a second one-dimensional DCT processor 406 (also referred to as a column DCT processor). The N × M matrix transpose circuit 404 is a preferred embodiment according to the device 100 shown in FIG. This shows that the apparatus 100 can be implemented in two-dimensional DCT and other data processing systems that require continuous transpose of the matrix.

As a preferred operation, the first one-dimensional DCT processor 402 performs a one-dimensional transform of the N x M matrix 408 (e.g., an input data matrix having video and picture pixels encoded with 8-bit binary words), where N Create an x M intermediate transform matrix 410. The first one-dimensional DCT processor 402 supplies the one-dimensional N × M intermediate transform matrix 410 in row direction order. An N × M matrix transform circuit 404 coupled with the first one-dimensional DCT processor continuously transposes the intermediate transform matrix 410 at zero cycle delay between successive matrix transposes.

The second one-dimensional DCT processor 406 also performs one-dimensional transform on the transform of the N × M intermediate transform matrix 412 to produce the desired two-dimensional DCT 414. The operation of the N × M matrix transpose circuit 404 is similar to the operation of the device 100 shown in Figs. 1 to 3, and therefore description thereof will be omitted. The two-dimensional DCT 400 may be implemented as an image and image processing system. For example, this may be implemented with a Joint Photographic Experts Group (JPEG) system, a Moving Picture Experts Group (MPEG) system, an H.264 system, or the like. In addition, the two-dimensional DCT processor 400 may be implemented on a single chip.

The apparatus 100 shown in FIGS. 1-4 enables continuous transpose of the matrix at zero cycle delay between successive matrix transposes.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: two-dimensional transpose device 102: data storage unit
104: recording control unit 106: reading control unit

Claims (18)

A plurality of data storage units arranged in a two-dimensional structure, the two-dimensional structure having X rows and Y columns, each of the X rows and Y rows including a data storage set for storing data;
A recording control unit connected to an input of the plurality of data storage units for recording data in at least one virtual row; And
Coupled to an output of the plurality of data stores for reading data from at least one virtual column, wherein the at least one virtual row is associated with the X rows and Y columns associated with the set of data stores in which data is written. Wherein the at least one virtual column corresponds to one of the X rows and Y columns associated with the set of data stores from which the written data has been read, the data written to the at least one virtual row and Data read from the at least one virtual column is performed substantially simultaneously during each operating cycle so that the two-dimensional structure is continuously transposed at zero cycle delay between successive transposes. Transpose apparatus of a two-dimensional structure including a control unit. The recording apparatus of claim 1, wherein the recording controller comprises:
Selecting the X rows in the two-dimensional structure for recording data, and writing the data to the X rows in row direction during the first X operating cycle before successively transposing the two-dimensional structure. Transpose device. The method of claim 1,
And write data into the at least one virtual column and read data from the at least one virtual column are performed in a cyclic order. The method of claim 1, wherein the read control unit,
In the continuous transposing of the two-dimensional structure, when the first X clock cycles are completed, the transposing device of the two-dimensional structure to read the data from the virtual columns Y ₁ -Y _{N in} column direction order. The method of claim 1, wherein the read control unit,
In the continuous transposing of the two-dimensional structure, when the first X clock cycles are completed, the transposing device of the two-dimensional structure to read the data from the virtual columns Y ₁ -Y _{N in} column direction order. The method of claim 5, wherein the read control unit,
In continuously transposing the two-dimensional structure, the data is read from the virtual columns X _N -X _{1 in} column direction order, and the write control section is in a row direction order to the virtual rows X _N -X ₁ substantially simultaneously. Two-dimensional transpose device for recording data. The method of claim 6, wherein the read control unit,
In continuously transposing the two-dimensional structure, data is read from the virtual columns Y _N -Y _{1 in} column direction order, and the recording control unit substantially simultaneously rows the data in the virtual rows Y _N -Y ₁ . Transpose device of two-dimensional structure to record sequentially. The recording apparatus of claim 1, wherein the recording controller comprises:
A two-dimensional transpose device including at least one combinational logic circuit and a sequential logic circuit. The method of claim 1, wherein the read control unit,
A two-dimensional transpose device including at least one combinational logic circuit and a sequential logic circuit. The method of claim 1, wherein each of the plurality of data storage units,
A two-dimensional transpose device including at least one bit data. A first one-dimensional Discrete Cosine Transform (DCT) processor performing a one-dimensional transform of the N x M matrix to generate an N x M intermediate transform matrix;
The N × M matrix transpose circuit, in sequential transposition of the intermediate transform matrix, in a zero cycle delay between successive matrix transposes, coupled to the first one-dimensional DCT processor; And
And a second one-dimensional DCT processor performing a one-dimensional transform on the transform of the N × M intermediate transform matrix to produce a desired two-dimensional DCT. The circuit of claim 11, wherein the N × M matrix transpose circuit comprises:
A plurality of data stores arranged in a two-dimensional structure, the two-dimensional structure having X rows and Y columns, each of the X rows and Y rows storing data associated with the intermediate transform matrix;
A recording control unit connected to an input of the plurality of data storage units for selecting at least one virtual row for recording data associated with the intermediate transform matrix; And
Is connected to an output of the plurality of data storages for selecting at least one virtual column for reading the written data, the at least one virtual row being one of the two-dimensional structures in which the data is written; Corresponds to a row or one column, wherein the at least one virtual column corresponds to one row or column of the two-dimensional structure from which the written data is read, and the data written to the at least one virtual row and the at least one Data read from the virtual column is performed substantially simultaneously during each operating cycle such that the intermediate transform matrix has a read control that is continuously transposed at zero cycle delay between successive matrix transposes. Including two-dimensional DCT processor. The method of claim 12, wherein the recording control unit,
A two-dimensional DCT processor comprising at least one combinational logic and sequential logic. The method of claim 12, wherein the read control unit,
A two-dimensional DCT processor comprising at least one combinational logic and sequential logic. The method of claim 12, wherein the recording control unit,
Selecting the X rows in a two-dimensional structure for recording data, and writing the data to the X rows in row direction order during the first X operation cycle before successively transposing the two-dimensional structure. The method of claim 12, wherein the recording control unit,
Selecting an arbitrary row in a two-dimensional structure for recording data, writing the data to the data storage of the selected row in a Z operation cycle, and the value of Z matches the number of data storage of the selected row 2D DCT processor. The method of claim 12,
And the data written to the at least one virtual row and the data read from the at least one virtual column are performed in a periodic order. The method of claim 11,
Wherein the N × M matrix comprises video or image pixels encoded with an 8-bit binary word, wherein the two-dimensional DCT processor is implemented on a single chip.

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