KR20110108545A - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device that uses a negative word line and decodes an external command signal to generate an internal command signal. The present invention relates to a semiconductor memory device that detects a voltage level of an internal voltage and decodes an external command signal. There is provided a semiconductor memory device including command decoding means for generating an internal command signal, and activation control means for controlling whether or not the last internal command signal output in response to the internal command signal is activated according to the detection signal.

Description

Semiconductor memory device and its operation method {SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device that uses a negative word line and generates an internal command signal by decoding an external command signal.

In general, semiconductor memory devices including DDR SDRAM (Double Data Rate Synchronous DRAM) perform various operations in response to various signals input from an external chip set. Among the operations performed by the semiconductor memory device, there are typically read and write operations. First, during a write operation, the semiconductor memory device receives an external command signal, data, and an address corresponding to the write operation, and stores data in a position corresponding to the input address. During the read operation, the semiconductor memory device receives an external command signal and an address corresponding to the read operation, and outputs data at a location corresponding to the input address to the outside.

On the other hand, the external command signal includes a chip select signal (Chip Select, CS), a row address strobe signal (Row Address Strobe, RAS), a column address strobe signal (Colunm Address Strobe, CAS), and a write enable signal (Write Enable). , WE), and the semiconductor memory device decodes the external command signal to generate various internal command signals.

1 is a block diagram for describing a part of a general semiconductor memory device.

Referring to FIG. 1, a semiconductor memory device includes a command decoding unit 110 and a memory bank 120.

The command decoding unit 110 decodes the chip select signal CS, the row address strobe signal RAS, the column address strobe signal CAS, and the write enable signal WE, which are external command signals, to decode the active signal. ACT). Here, the active signal ACT is a signal for activating an active operation of the memory bank 120. Subsequently, the memory bank 120 includes a plurality of memory cells, and data input from the outside is stored in the plurality of memory cells.

2 is a circuit diagram illustrating a memory cell included in the memory bank 120 of FIG. 1.

Referring to FIG. 2, a memory cell includes a cell capacitor C for storing data and a cell transistor for transferring data stored in the cell capacitor C to the bit line BL when the word line WL is activated. TR). Here, the cell transistor TR performs a turn on / off operation according to the voltage driven in the word line WL, and in recent years, the word transistor WL is turned on to turn on the cell transistor TR. ) Is driven to a positive high voltage, and the word line WL is driven to a negative low voltage to turn off the cell transistor TR.

The memory bank 120 includes a plurality of memory cells having such a configuration, and word lines WL corresponding to addresses of the plurality of word lines WL disposed in the memory bank 120 are activated during an active operation. The word line remains inactive. That is, a positive high voltage is applied to the word line WL to be activated, and a negative low voltage is applied to the word line WL to be inactivated. Ideally, even when the word line WL is driven to the ground voltage VSS, since the cell transistor TR is configured as an NMOS transistor, the cell transistor TR is turned off so that no current flows through the cell transistor TR. Inevitably, current flows through (TR). Accordingly, by driving the word line WL at a negative low voltage these days, unnecessary current consumption flowing through the cell transistor TR is reduced.

Meanwhile, as the process technology of the semiconductor memory device develops day by day, the circuit sizes of the semiconductor memory device become smaller. In order to control such miniaturized circuits, it is necessary to use an external power supply voltage having a low voltage level. However, when using such a low external power supply voltage, an internal power supply voltage generated using this external power supply voltage does not maintain a desired voltage level before active operation. The same applies to the negative low voltage applied when the word line WL is deactivated. Negative undervoltages do not maintain the desired voltage levels, meaning that unnecessary current consumption occurs in the active memory bank.

The present invention has been proposed to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of controlling active operation by detecting a voltage level of a negative low voltage applied to a word line.

According to an aspect of the present invention, there is provided a semiconductor memory device, comprising: voltage detecting means for generating a detection signal by detecting a voltage level of an internal voltage; Command decoding means for decoding an external command signal to generate an internal command signal; And activation control means for controlling whether the final internal command signal output in response to the internal command signal is activated according to the detection signal.

According to another aspect of the present invention, there is provided a method of operating a semiconductor memory device, the method comprising: generating an active signal by decoding an external command signal; Detecting a point when the negative low voltage reaches a predetermined voltage level; Limiting an activation time of the active signal in response to the signal output from the detecting step; And activating a memory bank in response to the active signal.

In the semiconductor memory device according to the embodiment of the present invention, by controlling the activation time of the internal command signal activated during the active operation with the detection signal detecting the voltage level of the negative low voltage applied to the word line, it is possible to prevent unnecessary current consumption. It is possible.

The present invention can obtain the effect of minimizing the current consumed during the active operation of the semiconductor memory device.

1 is a block diagram for explaining a part of a configuration of a general semiconductor memory device.
FIG. 2 is a circuit diagram illustrating a memory cell included in the memory bank 120 of FIG. 1.
3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.
4 is a circuit diagram for describing the voltage detector 310 of FIG. 3.
FIG. 5 is a circuit diagram illustrating the activation control unit 330 of FIG. 3.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a block diagram illustrating a part of a configuration of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 3, the semiconductor memory device includes a voltage detector 310, a command decoder 320, an activation controller 330, and a memory bank 340.

The voltage detector 310 detects a voltage level of the negative low voltage VBBW and generates a detection signal DET. Here, the negative low voltage VBBW is a voltage applied when the word line WL is inactivated in FIG. 2, and has a lower voltage level than the ground power supply voltage VSS and is generated by an internal circuit provided in the semiconductor memory device. Voltage.

The command decoding unit 320 decodes an internal command signal by decoding the chip select signal CS, the row address strobe signal RAS, the column address strobe signal CAS, and the write enable signal WE, which are external command signals. Generates an active signal ACT. Here, the active signal ACT becomes a source signal for activating the active operation of the memory bank 340.

The activation controller 330 controls whether the final active signal FIN_ACT output in response to the active signal ACT is activated according to the detection signal DET. The active operation of the memory bank 340 is substantially activated in response to the final active signal FIN_ACT output from the activation controller 330.

The memory bank 340 includes a plurality of memory cells for storing data. In this case, a positive high voltage is applied to a word line WL connected to a memory cell corresponding to an address among a plurality of memory cells disposed in the active memory bank 340, and a negative low voltage VBBW is applied to the word line WL that is not. Is applied.

The semiconductor memory device according to an exemplary embodiment of the present invention detects a time point when the negative low voltage VBBW reaches a desired voltage level, and controls the activation time point of the active signal ACT by using the same. Therefore, even if the active signal ACT is activated before the negative low voltage VBBW reaches the desired voltage level, the final active signal FIN_ACT is not activated. That is, the final active signal FIN_ACT is activated after the negative low voltage VBBW reaches a desired voltage level.

4 is a circuit diagram illustrating the voltage detector 310 of FIG. 3.

Referring to FIG. 4, the voltage detector 310 includes a voltage divider 410 and a voltage comparator 420.

The voltage divider 410 receives an external power supply voltage VDD and a negative low voltage VBBW, and distributes the resistor at a predetermined rate. The voltage divider 410 receives a plurality of resistors connected in series between the external power supply voltage VDD and the negative low voltage VBBW. Equipped.

The voltage comparator 420 compares the output voltage output from the voltage divider 410 with the reference voltage VREF to output the detection signal DET. The voltage comparator 420 is activated by the activation signal EN and is logic 'high'. outputs a detection signal DET having a 'high' or a logic 'low'.

Hereinafter, a brief operation of the voltage detector 310 will be described.

First, when the negative low voltage VBBW does not reach the desired voltage level, the output voltage of the voltage divider 410 has a voltage level higher than the reference voltage VREF and the PMOS transistor of the voltage comparator 420 is turned on. Is on. Therefore, the detection signal DET becomes logic 'low'. Subsequently, when the negative low voltage VBBW reaches a desired voltage level, the output voltage of the voltage divider 410 has a voltage level lower than the reference voltage VREF and the NMOS transistor to which the reference voltage VREF is applied is turned on. Is on. Therefore, the detection signal DET becomes logic 'high'.

FIG. 5 is a circuit diagram for describing the activation controller 330 of FIG. 3.

Referring to FIG. 5, the activation controller 330 includes a negative AND gate NAND for receiving a detection signal DET and an active signal ACT. As illustrated in FIG. 4, the detection signal DET becomes logic 'low' when the negative low voltage VBBW does not reach the desired voltage level, and becomes logic 'high' when the desired voltage level is reached.

Therefore, even if the active signal ACT is activated in the section in which the detection signal DET is logic 'low', the activation control unit 330 does not reflect this to the final active signal FIN_ACT and the detection signal DET is logic 'high'. In the interval 'in', the active signal ACT is reflected in the final active signal FIN_ACT. That is, the detection signal DET limits the activation time of the active signal ACT.

As described above, the semiconductor memory device according to the embodiment of the present invention detects the negative low voltage VBBW and controls the activation time of the active signal ACT in response to the detected detection signal DET. Accordingly, the memory bank 340 performs an active operation only when the negative low voltage VBBW reaches a desired voltage level, and a desired voltage level is applied to word lines that are not activated among the word lines disposed in the active memory bank 340. The negative low voltage of VBBW is applied. This means that the current consumed in the memory bank can be minimized during active operation.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

In addition, the position and type of the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently according to the polarity of the input signal.

310: voltage detection unit 320: command decoding unit
330: activation control unit 340: memory bank

Claims (10)

Voltage detecting means for detecting a voltage level of an internal voltage and generating a detection signal;
Command decoding means for decoding an external command signal to generate an internal command signal; And
Activation control means for controlling the activation of the final internal command signal output in response to the internal command signal according to the detection signal
A semiconductor memory device having a.
The method of claim 1,
And the internal voltage is a negative voltage having a lower voltage level than the ground power supply voltage.
The method of claim 2,
And the negative voltage is applied to a word line connected to the memory cell.
The method of claim 1,
And the internal command signal is activated during an active operation.
The method of claim 1,
The voltage detection means,
A voltage dividing unit configured to receive an external power supply voltage and the internal voltage and distribute the same at a predetermined ratio; And
And a voltage comparator for comparing a reference voltage with an output voltage of the voltage divider and outputting the detection signal corresponding to the result.
The method of claim 1,
And a memory bank that is activated in response to the last internal command signal.
Generating an active signal by decoding an external command signal;
Detecting a point when the negative low voltage reaches a predetermined voltage level;
Limiting an activation time of the active signal in response to the signal output from the detecting step; And
Activating a memory bank in response to the active signal
Method of driving a semiconductor memory device comprising a.
The method of claim 7, wherein
Activating the memory bank,
Applying a positive high voltage to a word line corresponding to an externally input address among a plurality of word lines arranged in the memory bank; And
And applying the negative low voltage to the remaining word lines of the plurality of word lines.
The method of claim 7, wherein
And the memory bank is activated after the negative low voltage reaches a predetermined voltage level.
The method of claim 7, wherein
And wherein the negative low voltage has a lower voltage level than the ground power supply voltage.

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