KR20110103142A - Method for accessing data in non-volatile memory storage and recorded medium storing program for performing the same - Google Patents

Abstract

Disclosed are a data access method of a nonvolatile memory device and a recording medium recording a program for performing the same. The data access method of the nonvolatile memory device temporarily stores the provided write request when the size of the provided write request page is smaller than the size of the superpage, which is a set of simultaneously accessible pages, and collects the temporarily stored at least one write request page. After configuring the size of the super page, the logical page number of the write request pages composed of the size of the super page is mapped to the contiguous virtual page numbers to generate the write requests in units of superpages, and the write requests in units of the superpages are generated in nonvolatile memory. To the device. Accordingly, each memory chip of the nonvolatile memory device can be simultaneously accessed in parallel, thereby improving the overall performance of the nonvolatile memory device.

Description

TECHNICAL FOR ACCESSING DATA IN NON-VOLATILE MEMORY STORAGE AND RECORDED MEDIUM STORING PROGRAM FOR PERFORMING THE SAME}

The present invention relates to data input / output of a nonvolatile memory device, and more particularly, to a method of accessing a data of a nonvolatile memory device which can be applied to a storage device connected to a plurality of nonvolatile memory chips in a multi-channel, and a program for performing the same. It relates to a recording medium.

Since the flash memory device is superior in access speed, power consumption, noise, durability, vibration, etc., compared to the conventional hard disk drive, the ratio used in portable electronic devices is increasing rapidly.

In addition, flash memory may be used as a portable storage device as a nonvolatile memory itself, or may be used as a secondary cache to reduce the bottleneck between the hard disk and the disk cache and to reduce the power consumption of the disk cache. A hybrid hard disk (hybrid HDD) combined with a hard disk or a plurality of flash memory chips may be utilized as a solid state disk (SSD), which is configured as one storage device.

The flash memory may be classified into a NOR flash memory having many characteristics of a conventional random memory and a NAND flash memory having many characteristics of a storage medium such as a hard disk.

NAND flash memory performs read and write operations in units of pages, erase operations in units of blocks, and when data is updated, the area can be overwritten with updated data. It has a characteristic that new data can be written to the location only if the corresponding block is deleted. Due to the above characteristics, the NAND flash memory cannot immediately overwrite the updated data in the position where the data was previously written, but must update the position information after writing the data in the new position.

Due to the features of the NAND flash memory described above, a flash translation layer emulates NAND flash memory as if it were a hard disk between the file system of the host system designed based on the hard disk and the NAND flash memory. Layer software, hereinafter referred to as 'FTL'.

The FTL hides the inherent characteristics of NAND flash memory from the host system's file system and provides a logical address from the file system to perform the same input / output operations as the hard disk. It performs the function of mapping with physical address.

The density of NAND flash memory is increasing every year, but because it is considerably smaller than hard disks and NAND flash memory itself is slower than conventional buses such as Small Computer System Interface (SCSI) or Serial Advanced Technology Attachment (SATA), It is not suitable for use as a storage medium. Accordingly, SSDs use a plurality of NAND flash memories in parallel and use a multi-channel and multi-way structure to improve processing speed.

1 is a block diagram illustrating a configuration of an SSD device having a four-channel two-way structure.

Referring to FIG. 1, a general SSD device 10 may include a host interface 11, a buffer 12, a controller 13, a NAND controller 14, and a plurality of flash memory chips 15. The channel has a two-way structure.

The host interface 11 performs an interface function between the host device such as a computer and the SSD device 10, and is configured to support one of standards such as Ultra DMA mode 6, SATA 1, or SATA 2.

The buffer 12 may be configured as a DRAM and used as a write buffer that is temporarily stored until data provided from the host device through the host interface 11 is written to the corresponding flash memory chip.

The controller 13 performs a Flash Tranlation Layer (FTL) function that interprets a read or write command provided from a host device, converts it to correspond to the operation of the flash memory, and processes the same. Perform top level control.

The NAND control unit 14 receives data from the buffer 12 under the control of the control unit 13, and converts the received data into a low level command corresponding to the flash memory device to the flash memory chip 15. To pass. Instructions processed by the NAND controller 14 include a write page, a read page, an erase page, a copyback page, and the like.

Each of the plurality of flash memory chips 15 is composed of a NAND flash memory, and data is substantially recorded.

In the SSD device 10 shown in FIG. 1, the buffer 12 and the NAND controller 14 are connected by four buses (that is, four channels) each having a predetermined bandwidth. In addition, each NAND controller 14 is connected to a plurality of flash memory chips 15 through a channel having the predetermined bandwidth. In addition, each NAND controller 14 is connected to four flash memory chip pairs in which two flash memory chips are paired through their channels.

In the SSD device 10 having a four-channel two-way structure as shown in FIG. 1, the NAND control unit 14 exists in each channel, thereby allowing simultaneous access to each channel. In addition, a pair of two-way chips on a single channel share a control pin and a data bus so that they can be accessed simultaneously through interleaving. That is, in the four-channel two-way SSD device 10 shown in FIG. 1, a total of eight chips 16 may be simultaneously accessed.

FIG. 2 is a conceptual diagram illustrating the concept of a super page, and illustrates a part of a specific block having the same page index among the eight chips 16 simultaneously accessible in the SSD device shown in FIG. 1.

As illustrated in FIG. 2, pages having the same page index among chips simultaneously accessible in the SSD device are referred to as superpages. When the SSD device inputs and outputs, the more the super page access, the more the parallelism between the chips can be utilized to improve the overall performance.

Therefore, in the multi-channel multi-way SSD device, the FTL uses a page mapping method in units of superpages in order to maximize the parallelism between chips.

3 is a conceptual diagram illustrating a process in which a write request is performed in the SSD device shown in FIG. 1, FIG. 3A illustrates an initial state of the SSD device, and FIG. 3B illustrates sequential writes from the host device. 3 illustrates a write operation when a request is provided, and FIG. 3C illustrates a write operation when a random write request is received from a host device.

SSD in the case where a sequential write request for writing 16 to 16 pages of logical page number (LPN) is provided as shown in (b) of FIG. 3 in an initial state as shown in (a) of FIG. The device only needs to write two superpages sequentially, so it takes time to execute two write commands overall.

However, when a random write request is provided from the host as shown in (c) of FIG. 3, other pages (that is, LPN) as well as a time to execute two write commands to process a request to write two pages. Since the reading time is required to move 0 to 6 and 9 to 15), the overall time is longer than that of the case of performing the instruction to write the 16 pages shown in FIG.

As shown in FIG. 3, a non-volatile memory device having a multi-channel multi-way structure shows excellent performance when a sequential input / output request is provided from a host. However, when a random input / output request is provided, the parallelism of the device cannot be utilized. This has a problem of deterioration.

An object of the present invention to solve the above problems is to provide a data access method of a nonvolatile memory device that can take full advantage of the parallelism of the nonvolatile memory device.

Another object of the present invention is to provide a recording medium on which a program for performing a data access method of the nonvolatile memory device is recorded.

A data access method of a nonvolatile memory device according to an aspect of the present invention for achieving the above object of the present invention is provided when the size of the provided write request page is smaller than the size of the super page which is a set of simultaneously accessible pages. Temporarily storing a write request, collecting at least one temporarily stored write request page to configure a size of the superpage, and converting logical page numbers of write request pages configured to the size of the superpage into consecutive virtual page numbers. Generating a write request in units of superpages and providing the generated write request in units of superpages to a nonvolatile memory device. The step of collecting the temporarily stored at least one write request page and configuring the size of the super page may include: a write request unit provided from a file system of a host, a process in which a write request is generated, and whether the file accessed through the write request is the same; In consideration of at least one, at least one write request page among the temporarily stored write request pages may be collected and configured to have a size of the superpage. The mapping of the logical page numbers of the write request pages configured with the size of the super page into consecutive virtual page numbers to generate a write request in units of super pages may include: creating a new virtual super for the write request pages configured with the size of the super page; Allocating a page, configuring the virtual superpage by mapping logical page numbers of the write request pages to virtual page numbers, and updating a mapping table to which the logical page numbers and the virtual page numbers are mapped. It may include. The data access method of the nonvolatile memory device may include: when an update occurs for the same logical page number, changing an existing virtual page number mapped to the logical page number where the update occurred in the mapping table to a new virtual page number; The method may further include updating the garbage collection list. The providing of the generated superpage unit write request to a nonvolatile memory device may include writing the superpage unit write request and invalidated existing virtual page number information when an update occurs for the same logical page number. It can be provided to a nonvolatile memory device. The data access method of the nonvolatile memory device may include calculating a remainder obtained by dividing the provided write request page by the superpage size when the size of the provided write request page is greater than or equal to the superpage, and dividing the write request page by the superpage. If there is a remainder divided by the page size, the method may further include temporarily storing the remainder.

In addition, the data access method of the nonvolatile memory device according to another aspect of the present invention for achieving the object of the present invention, the step of temporarily storing the provided read request, and mapping the logical page number of the temporarily stored read request page mapping table Reconstructing a read request by collecting the read request pages that access different nonvolatile memory chips among at least one read request page temporarily stored based on the converted virtual page number by referring to the virtual page number; Providing the reconstructed read request to the nonvolatile memory device. The converting the logical page numbers of the temporarily stored read request pages into virtual page numbers by referring to a mapping table may include setting a time limit for the temporarily stored read request and logical pages of the temporarily stored read request pages within the time limit. The method may include converting the number into a virtual page number by referring to the mapping table. The reconfiguring of the read request may include obtaining a remainder obtained by dividing the converted virtual page number by the number of pages constituting a superpage, which is a set of simultaneously accessible pages, and reading the obtained remainder with different virtual page numbers. Reconstructing the request.

In addition, the data access method of the nonvolatile memory device according to another aspect of the present invention for achieving the object of the present invention, if the number of available superpages in the list of available superpages is less than a predetermined threshold value super Selecting a page as a sacrificial super page, reading and temporarily storing at least one valid page included in the sacrificial super page, and sequentially storing a new virtual page number of each of the at least one valid page stored temporarily. Generating a write request in units of a superpage by changing to a virtual page number and providing the generated virtual page number information to the nonvolatile memory device. If the number of available superpages in the available superpage list is less than a preset threshold, selecting the superpage with the smallest valid page as the victim superpage may be based on the garbage collection list in which the invalid page list is stored. You can choose a small superpage as your victim superpage. The step of generating a write request on a super page basis by changing an existing virtual page number of each of the temporarily stored at least one valid page into a new consecutive virtual page number may include: And after changing the virtual page number to a new consecutive virtual page number, updating the garbage collection list and the available superpage list.

In addition, a recording medium for recording a program for performing a data access method of a nonvolatile memory device according to an aspect of the present invention for achieving another object of the present invention is a set of pages that can be simultaneously accessed the size of the write request page provided. Temporarily storing the provided write request when the size of the superpage is smaller, collecting at least one temporarily stored write request page, configuring the size of the superpage, and writing write page pages of the size of the superpage. A program is performed that maps logical page numbers into consecutive virtual page numbers to generate a write request in units of superpages and provides the generated write requests in units of superpages to a nonvolatile memory device.

As described above, in the data access method of the nonvolatile memory device according to the embodiment of the present invention, when a randomly provided write operation is performed, the provided write request is converted into a successive write request in units of superpages and provided to the nonvolatile memory device. do. In addition, when performing a read request, the read request is reconfigured into a superpage including read requests having different chip IDs, and provided to the nonvolatile memory device. In addition, garbage collection is performed in preparation for lack of virtual superpage.

Therefore, when performing a write or read request of data, each memory chip of the nonvolatile memory device can be simultaneously accessed in parallel, thereby improving the overall performance of the nonvolatile memory device.

1 is a block diagram illustrating a configuration of an SSD device having a four-channel two-way structure.
2 is a conceptual diagram illustrating the concept of a super page.
3 is a conceptual diagram illustrating a process in which a write request is performed in the SSD device shown in FIG. 1.
4 is a block diagram illustrating a configuration of a system to which a data access method of a nonvolatile memory device according to an embodiment of the present invention is applied.
5 is a flowchart illustrating a process of performing a write operation among a data access method of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 6 is a conceptual diagram illustrating an example of a write operation process of the nonvolatile memory device illustrated in FIG. 5.
FIG. 7 is a conceptual diagram illustrating an example of an operation process when an update occurs during a write operation of the nonvolatile memory device illustrated in FIG. 5.
FIG. 8 is a conceptual diagram illustrating a reordering process during a write operation of the nonvolatile memory device shown in FIG. 5.
9 is a flowchart illustrating a process of performing a read operation in a data access method of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 10 is a conceptual diagram illustrating an example of a read operation process of the nonvolatile memory device illustrated in FIG. 9.
11 is a flowchart illustrating a garbage collection process in a data access method of a nonvolatile memory device according to an embodiment of the present invention.
12 to 14 are conceptual views illustrating an example of a garbage collection process illustrated in FIG. 11.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. Hereinafter, the same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

Hereinafter, it is assumed that a data access method of a nonvolatile memory device according to an embodiment of the present invention is applied to a nonvolatile memory device having a multichannel multiware structure. However, this is only for convenience of description, and the data access method of the nonvolatile memory device according to the embodiment of the present invention may be applied to all storage devices configured to simultaneously access a plurality of nonvolatile memory chips.

4 is a block diagram illustrating a configuration of a system to which a data access method of a nonvolatile memory device according to an embodiment of the present invention is applied.

Referring to FIG. 4, when a random write request is generated, the host 100 stores all non-contiguous Logical Page Numbers (LPNs) 101 in consecutive Virtual Page Numbers (VPNs) 103. After mapping, update the mapping table 110, write requests are provided to the nonvolatile memory device 200, such as SSD, in units of superpages, and the nonvolatile memory device 200 The write operation is performed to the physical address 201 corresponding to the virtual page number 103 of the write request provided from the host 100 by referring to the mapping table 210.

Alternatively, when a read request is generated, the host 100 reorders the virtual page numbers 103 with reference to the mapping table 110 so as to make the best use of the parallelism of the nonvolatile memory device 200. The read request is provided to the nonvolatile memory device 200, and the nonvolatile memory device 200 refers to the mapping table 210 to the physical address 201 corresponding to the virtual page number 103 of the read request. Read the recorded data.

5 is a flowchart illustrating a process of performing a write operation among a data access method of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 5, first, when a write request is generated in the host device (step 301), the size of the generated write request page is determined (step 303), and the write request page is larger than the size of the preset superpage. If it is determined to be small, the generated write request is stored in a queue (step 305).

Here, the superpage means a set of pages that can be simultaneously accessed (input or output) as shown in FIG. 2. For example, when a data access method of a nonvolatile memory device according to an embodiment of the present invention is applied to an SSD device having a four-channel two-way structure illustrated in FIG. 1, the superpage may include eight pages. .

Thereafter, the host determines whether the write requests stored in the queue have reached the superpage size (step 307), and if it is determined that the write requests stored in the queue satisfy the superpage size, the available virtual superpage (VSP: Vertual SuperPage) is determined. A new virtual superpage is allocated by allocating a virtual superpage number (VSPN) available in the free list managing free pages (step 309).

Here, when collecting random write requests smaller than the size of the superpage stored in the queue and configuring the virtual superpage in units of superpages, it is preferable to configure the virtual superpage in consideration of the locality of the page.

For example, a host may include write request units provided from the file system in one virtual superpage in consideration of write request units provided from the file system, or include write requests generated from the same process in one virtual superpage. In addition, the parallelism of a nonvolatile memory device can be maximized by including a write request for accessing the same file in one virtual superpage.

Thereafter, the host allocates the virtual page number VPN to the logical page number LPN of the write requests collected in the superpage size among the write requests stored in the queue, and simultaneously updates the mapping table (step 311). Here, the host determines whether an update has occurred for the same logical page number (step 313), and if it is determined that no update has occurred for the same logical page number, the host requests a new write request having a size of a superpage unit. To the device (step 315).

Or, if it is determined that an update has occurred for the same logical page number, the host changes an existing virtual page number to a new virtual page number in the mapping table (step 317), and updates the garbage collection list (step 319). ).

Thereafter, the host provides the nonvolatile memory device with the new write request and the invalidated virtual page number information having the size of a superpage unit (step 321). Here, the invalidated existing virtual page number may be provided to the nonvolatile memory device using a trim command.

In the data access method of the nonvolatile memory device according to an embodiment of the present invention, the host maps a logical page number to a virtual page number and provides a write request in units of virtual page numbers to the nonvolatile memory device. And nonvolatile memory devices use different addressing schemes. That is, the nonvolatile memory device does not know whether to update data because the nonvolatile memory device receives a write request of a superpage size and performs a write operation accordingly. Therefore, when existing data is updated with new data, information about the invalidated existing data must be provided to the nonvolatile memory device. For this purpose, the virtual page number of the invalidated data is provided by using the trim command. To provide.

If the size of the write request page generated in step 303 is greater than or equal to the size of the preset superpage, the remainder obtained by dividing the write request page by the size of the superpage is calculated (step 323), and it is determined whether there is a remainder (step 325). If it is determined that there is a remainder (i.e., the write request page does not divide by the size of the superpage), the write request for the remaining pages divided by the size of the superpage is queued (step 327). In step 307, the subsequent steps are performed.

Or, if it is determined in step 325 that no remainder exists (i.e., the write request page is divided by the size of the superpage), then a virtual superpage number (VSPN) is assigned to the generated write request pages. (Step 329), the virtual page number VPN is sequentially mapped to each logical page number LPN of the write request pages (step 331), and the generated write request is provided to the nonvolatile memory device (step 333). .

FIG. 6 is a conceptual diagram illustrating an example of a write operation process of the nonvolatile memory device illustrated in FIG. 5.

Referring to FIG. 6, if a write request of Write (0,1), Write (5,2), Write (15,3), and Write (9,2) is provided from the host's file system, the host may have a superpage size. Gather write requests in units, assign an available virtual superpage number (VSPN) from the list of available superpages (for example, 0), and then assign it to each logical page number (LPN) of a given write request. Allocate a virtual page number (VPN) and update the mapping table.

Thereafter, the host provides a successive write request (Write (0,8)) in units of superpages to the nonvolatile memory device (eg, SSD), and the nonvolatile memory device refers to the mapping table to provide the virtual superpage. The data is recorded at the physical address corresponding to the virtual page number included in the.

As shown in FIG. 6, in the data access method of a nonvolatile memory device according to an exemplary embodiment of the present invention, when performing a write operation, the parallelism is maximized by converting a randomly provided write request into consecutive write requests in units of superpages. This can improve the overall performance of the device.

FIG. 7 is a conceptual diagram illustrating an example of an operation process when an update occurs during a write operation of the nonvolatile memory device illustrated in FIG. 5.

After a write operation as shown in FIG. 6 is performed, a write request of Write (4,1), Write (8,2), Write (32,3) and Write (16,2) is received from the host's file system. If provided, the host collects write requests in units of superpages and then checks the free list of available pages to assign a new virtual superpage number (VSPN = 1).

The host determines whether the data is updated during the provided write request, and if the data is updated, converts the virtual page number mapped to the existing logical page number into a new virtual page number and invalidates the virtual page for recycling. Include the number in the garbage collection list (GC list).

For example, since logical page numbers 9, 16, and 17 are updated as shown in FIG. 6, existing virtual page numbers 3, 6, and 7 mapped to the logical page numbers are 10, 14, and 15, respectively. The garbage collection list (GC list) is updated accordingly.

As a result, the virtual page numbers included in the new virtual superpage (that is, VSPN = 1) become 8 to 15, and the host issues a superpage-based write request (that is, Write (8,8)) to the nonvolatile memory device. To provide.

At the same time, the host also uses the trim command (that is, Trim (3), Trim (6), Trim (7)) to determine which virtual page numbers (that is, 3, 6, and 7) invalidated by the update. To a memory device.

FIG. 8 is a conceptual diagram illustrating a reordering process during a write operation of the nonvolatile memory device shown in FIG. 5.

Referring to FIG. 8, when a write request of Write (8,1), Write (64,4), Write (32,7), and Write (16,4) is provided from the host's file system, the host is a superpage. After collecting the write requests in units, the virtual superpage is constructed by rearranging the write requests in consideration of the locality of the page.

For example, if a virtual superpage is configured in the order of write requests provided from the file system, locality is reduced because Write (32,7) is divided into two virtual superpages.

To solve the above problem, the host considers the write request unit provided and writes the write request sequence in Write (8,1), Write (64,4), Write (32,7), Write (16,4). Reorder 8,1), Write (32,7), Write (64,4), Write (16,4) to include Write (32,7) requests in one virtual superpage and then reorder The virtual page number is assigned to each logical page number.

9 is a flowchart illustrating a process of performing a read operation in a data access method of a nonvolatile memory device according to an embodiment of the present invention.

9, if a read request is generated from the host's file system (step 401), the host stores the read request in a queue (step 403). Here, the host sets a wait timeout for each read request stored in the queue, collects the read requests stored in the queue within the wait timeout, and performs subsequent steps (ie, steps 405 to 411) so that the read request is queued. The quality of service can be guaranteed by preventing response delay time that may occur as the waiting time increases.

Thereafter, the host converts the logical page number of the read request stored in the queue into the virtual page number by referring to the mapping table (step 405), and then, based on the converted virtual page number, the chip ID corresponding to each virtual page number ( chip ID) (step 407). Here, the host may obtain the chip ID based on the remainder obtained by dividing each converted virtual page number by the number of pages constituting the superpage, which is a set of simultaneously accessible pages.

In the data access method of the nonvolatile memory device according to an embodiment of the present invention, when a write request is always processed in units of superpages, the remainder of dividing the virtual page number by the number of pages of the superpage corresponds to each virtual page number. It becomes the ID of the chip (that is, the ID of the chip in which the physical address corresponding to each virtual page number exists).

After acquiring a chip ID corresponding to each virtual page number as described above, the host configures the superpage with the virtual page numbers having different chip IDs (step 409), and deactivates a read request corresponding to the configured superpage. Provided to the volatile memory device (step 411).

FIG. 10 is a conceptual diagram illustrating an example of a read operation process of the nonvolatile memory device illustrated in FIG. 9.

Referring to Figure 10, a read request of Read (32,3), Read (0,1), Read (16,2), Read (9,1) and Read (4,3) is provided from the host's file system. When the host stores the read requests, the host converts the logical page number of each read request into a virtual page number by referring to a mapping table.

After that, the host obtains the remainder obtained by dividing the converted virtual page number by the size of the superpage (that is, the number of pages constituting the superpage) as the chip ID, and configures the superpage with virtual page numbers having different chip IDs. In addition, the read request corresponding to the configured superpage is provided to the nonvolatile memory device (SSD).

As shown in FIGS. 9 and 10, in a read operation of a nonvolatile memory device according to an embodiment of the present invention, a read request is reconfigured into a superpage including read requests having different chip IDs. By providing parallel access to each memory chip in a nonvolatile memory device.

11 is a flowchart illustrating a garbage collection process in a data access method of a nonvolatile memory device according to an embodiment of the present invention.

In the data access method of the nonvolatile memory device according to an embodiment of the present invention, the virtual page number that is invalidated increases and the available virtual superpage number increases when data is frequently updated because the data access method is performed in units of virtual superpages when a write request is performed. Inadequate situations can result. In this case, garbage collection is performed on the invalid virtual page number to increase the available virtual superpage.

Specifically, the host checks the free list of available superpages (step 501), and if the number of virtual superpage numbers (VSPNs) included in the available superpage list is less than the preset threshold (step 503), garbage The virtual superpage having the smallest number of valid virtual page numbers is selected as a victim superpage by referring to a GC list (step 505). The reason for selecting the virtual superpage having the smallest valid virtual page number in step 505 is to minimize the additional read request.

Thereafter, the host reads the valid pages included in the victim superpage selected in step 505 and stores them in the queue (step 507). Here, when the valid page is stored in the main memory (or buffer) of the host, the valid page may be read from the main memory.

Thereafter, the host generates a write request for storing valid pages stored in the queue in units of superpages (step 509). As described above, the host may generate a write command by combining valid pages stored in a queue with a super page size (for example, eight pages).

After generating a write request as described above, the host allocates a new virtual superpage number available in the free list of available superpages (step 511) and updates the existing virtual page number in the mapping table with the new virtual. Change to the page number (step 513). At the same time, the host updates the garbage collection list (GC list) and the free superpage list (free list) (step 515).

Thereafter, the host provides the nonvolatile memory device with the write request having the size of a super page unit and the existing virtual page number information invalidated (step 517).

12 to 14 are conceptual diagrams illustrating an example of a garbage collection process illustrated in FIG. 11, and illustrates an example of garbage collection when there is one list of available superpages.

Hereinafter, the garbage collection process illustrated in FIG. 11 will be described in more detail with reference to FIGS. 12 to 14.

First, as shown in FIG. 12, when there is only one virtual superpage to be allocated to a write request in the free list, the host stops garbage collection for invalid pages. To get the available virtual superpages.

Specifically, the host selects a virtual superpage having the smallest valid virtual page number as a victim superpage by referring to a garbage collection list (GC list). For example, in FIG. 12, the virtual superpage number 0 has valid virtual page numbers 5, 6, and 7, and the virtual superpage number 1 has valid virtual page numbers 8, 10, 12, 14, and 15, and the virtual superpage. Since the number 2 is a valid virtual page number 16 to 23, the host selects the virtual super page numbers 0 and 1 having the smallest number of valid virtual page numbers as victim superpages.

Thereafter, the host selects valid pages (ie, 5, 6, 7, 8, 10, 12, 14, and 15) included in the virtual superpage selected as the sacrificial superpages 0 and 1, as shown in FIG. Requests for reading Read (5,3), Read (8,1), Read (10,1), Read (12,1) and Read (14,2) are generated to read valid pages and store them in the queue. Here, the read request is generated for the virtual page number because the read request should be performed at the actual physical address of the nonvolatile memory device.

In addition, as shown in FIG. 14, the host write requests for valid pages stored in the queue, Write (5,3), Write (8,1), Write (10,1), Write (12,1), and Write. Produces (14,2). Here, the write request is generated for the virtual page number.

Thereafter, the host first allocates a new virtual superpage number (ie, VSPN = 3) in order to process the write request generated as described above in units of superpages, and sets an existing virtual page corresponding to the write command in the mapping table. Change the number to the new virtual page number. At the same time, the garbage collection list is updated by deleting invalid page numbers included in the garbage collection list, and the newly acquired virtual super page number is recorded in the free list. Update the.

After the virtual superpage is configured as described above, the host invalidates the virtual page number information Trim (5), Trim (6), and Trim (7) through the write request Write (24,8) and garbage collection process of the superpage size. ), Trim (8), Trim (10), Trim (12), Trim (14), and Trim (15) are provided to the nonvolatile memory device.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

100: host 200: nonvolatile memory device

Claims (13)

Temporarily storing the provided write request when the size of the provided write request page is smaller than the size of the superpage which is a set of simultaneously accessible pages;
Collecting at least one temporarily stored write request page and configuring the size of the superpage;
Generating a write request in units of superpages by mapping logical page numbers of write request pages configured in the size of the superpage into consecutive virtual page numbers; And
And providing the generated write request in units of superpages to a nonvolatile memory device. The method of claim 1, wherein collecting the temporarily stored at least one write request page and configuring the size of the super page comprises:
Collecting at least one write request page among the temporarily stored write request pages by considering at least one of a write request unit provided from a host file system, a process in which a write request is generated, and whether a file accessed through the write request is identical A data access method of a nonvolatile memory device, characterized in that the page size. The method of claim 1, wherein the mapping of the logical page numbers of the write request pages configured with the size of the superpage into consecutive virtual page numbers to generate a write request in units of superpages includes:
Allocating a new virtual superpage for write request pages configured with the size of the superpage;
Configuring the virtual super page by mapping logical page numbers of the write request pages to virtual page numbers; And
And updating the mapping table to which the logical page number and the virtual page number are mapped. The data access method of claim 3, wherein the data access method of the nonvolatile memory device comprises:
If an update occurs for the same logical page number, changing an existing virtual page number mapped to the logical page number where the update occurred in the mapping table to a new virtual page number; And
And updating the garbage collection list. The method of claim 1, wherein the providing of the generated super page write request to a nonvolatile memory device comprises:
And if an update occurs for the same logical page number, providing the write request and invalidated existing virtual page number information of the super page unit to the nonvolatile memory device. The data access method of claim 1, wherein the data access method of the nonvolatile memory device comprises:
Calculating a remainder obtained by dividing the provided write request page by the superpage size when the size of the provided write request page is greater than or equal to the superpage; And
And when the remainder obtained by dividing the write request page by the superpage size, temporarily storing the remainder. Temporarily storing the provided read request;
Converting logical page numbers of temporarily stored read request pages into virtual page numbers by referring to a mapping table;
Reconstructing a read request by collecting read request pages that access different nonvolatile memory chips among at least one read request page temporarily stored based on the converted virtual page number; And
Providing a reconstructed read request to the nonvolatile memory device. The method of claim 7, wherein converting the logical page numbers of the temporarily stored read request pages into virtual page numbers by referring to a mapping table,
Setting a time limit for a temporarily stored read request; And
And converting the logical page numbers of the temporarily stored read request pages into virtual page numbers with reference to a mapping table within the time limit. The method of claim 7, wherein reconstructing the read request,
Obtaining a remainder obtained by dividing the converted virtual page number by the number of pages forming a superpage, which is a set of simultaneously accessible pages;
And reconstructing the read request with different virtual page numbers obtained from the obtained remainders. Selecting a superpage having the smallest valid page as a victim superpage when the number of available superpages in the available superpage list is less than a preset threshold;
Reading and temporarily storing at least one valid page included in the victim super page;
Generating a write request in units of a super page by changing an existing virtual page number of each of the at least one valid page temporarily stored into a new consecutive virtual page number; And
And providing the generated virtual page number information and the invalidated virtual page number information to the nonvolatile memory device. The method of claim 10, wherein when the number of available superpages in the available superpage list is less than a preset threshold, selecting a superpage having the smallest valid page as a victim superpage
And selecting a superpage having the smallest valid page as a victim superpage based on a garbage collection list in which an invalid page list is stored. The method of claim 11, wherein the step of generating a write request in units of superpages by changing an existing virtual page number of each of the temporarily stored at least one valid page into a new consecutive virtual page number,
Changing the existing virtual page number of each of the at least one valid page stored temporarily to a new consecutive virtual page number, and then updating the garbage collection list and the available superpage list. Data access method of memory device. In the recording medium in which a program of instructions that can be executed by a digital processing device that performs data access of a nonvolatile memory device is tangibly implemented, and records a program that can be read by the digital processing device,
Temporarily storing the provided write request when the size of the provided write request page is smaller than the size of the superpage which is a set of simultaneously accessible pages;
Collecting at least one temporarily stored write request page and configuring the size of the superpage;
Generating a write request in units of superpages by mapping logical page numbers of write request pages configured in the size of the superpage into consecutive virtual page numbers; And
And a program for providing the generated write request in units of superpages to a nonvolatile memory device.

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