KR20110101405A - Method for forming pattern of the semiconductor device - Google Patents
Method for forming pattern of the semiconductor device Download PDFInfo
- Publication number
- KR20110101405A KR20110101405A KR1020100020383A KR20100020383A KR20110101405A KR 20110101405 A KR20110101405 A KR 20110101405A KR 1020100020383 A KR1020100020383 A KR 1020100020383A KR 20100020383 A KR20100020383 A KR 20100020383A KR 20110101405 A KR20110101405 A KR 20110101405A
- Authority
- KR
- South Korea
- Prior art keywords
- pattern
- exposure
- photosensitive film
- exposure process
- exposure mask
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
- G03F7/2022—Multi-step exposure, e.g. hybrid; backside exposure; blanket exposure, e.g. for image reversal; edge exposure, e.g. for edge bead removal; corrective exposure
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
- G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
The present invention relates to a method of forming a pattern of a semiconductor device, and discloses a technique of forming a hole pattern of 40 nm or less by performing a negative type double exposure process.
In the method of forming a pattern of a semiconductor device according to the present invention, forming an etched layer and a photoresist film on a semiconductor substrate, and performing a first exposure process on the photoresist film using an exposure mask to form an unexposed first region. Moving the exposure mask to perform a second exposure process on the photosensitive film to form an unexposed second region, and developing the first photosensitive film and the second region on the photosensitive film. And forming a photosensitive film pattern on the overlapping portion.
Description
The present invention relates to a method of forming a pattern of a semiconductor device. In particular, it relates to a double exposure process.
Recently, since semiconductor devices are required to operate at a high speed and have a large storage capacity, developments have been made to improve electrical characteristics that enable a large amount of data to be processed quickly.
In particular, as the degree of integration increases, the design rule is reduced, so that the technology for implementing the pattern has been variously developed. For this purpose, the wavelength of the exposure source for implementing the pattern is gradually shortened.
However, the critical dimension of the pattern currently under development is required to be 40 nm or less, and since it is very difficult to form a pattern satisfying such a condition, it is almost impossible to form a pattern using one exposure mask as before.
Therefore, we are developing technologies for implementing a desired pattern using two or three exposure masks, which are conventionally patterned with one exposure mask, and for this purpose, double patterning technology (hereinafter referred to as 'DPT'), Spacer patterning technology and the like have been proposed, but there is a limit in making a hole pattern of 40 nm or less using this.
An object of the present invention is to form a pattern having a fine line width by performing a negative type double exposure process.
In the method of forming a pattern of a semiconductor device according to the present invention, forming an etched layer and a photoresist film on a semiconductor substrate, and performing a first exposure process on the photoresist film using an exposure mask to form an unexposed first region. Moving the exposure mask to perform a second exposure process on the photosensitive film to form an unexposed second region, and developing the first photosensitive film and the second region on the photosensitive film. Forming a photosensitive film pattern by superimposing the.
Here, the photosensitive film may be a positive or negative photosensitive film. The exposure mask may include a plurality of light blocking patterns, and the light blocking patterns may have a rectangular shape. The light blocking patterns are spaced apart by one third of the light blocking pattern line width.
Preferably, the secondary exposure process is performed by moving the exposure mask along the X and Y axes, and more preferably, moves the exposure mask by 2/3 of the light shielding pattern line width.
In the method of forming a pattern of a semiconductor device according to the present invention, a negative pattern double exposure process may be performed to form a hole pattern of 40 nm or less.
1A and 1B are cross-sectional views illustrating positive and negative exposure methods.
2 is a layout showing an exposure mask according to the present invention;
3A to 3C are plan views illustrating a method of forming a pattern of a semiconductor device according to the present invention.
Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.
1A and 1B are cross-sectional views illustrating a positive type exposure process and a negative type exposure process.
Referring to FIG. 1A, a positive type exposure process is illustrated. An exposure process is performed using an
Referring to FIG. 1B, a negative type exposure process is illustrated. An exposure process is performed using an
2 shows a layout of an exposure mask according to the present invention.
Referring to FIG. 2, the
Each of the
3A to 3C are plan views illustrating a pattern formation method of a negative tone double exposure process using the exposure mask of FIG. 2 described above. Here, the negative type double exposure is an exposure method having the feature that the non-exposed areas that have never been exposed are removed.
Referring to FIG. 3A, an etched layer (not shown) is formed on a semiconductor substrate (not shown), and a photosensitive film 300 is coated on the etched layer (not shown). Here, the photosensitive film 300 may use a positive photosensitive film (Positive PR) or a negative photosensitive film (Negative PR). Since the negative type exposure process can be performed according to the kind of developing solution in a subsequent process, you may use what kind of photosensitive film. For example, in the case of using a positive photoresist film, it is possible to use a supernatant and a rinse liquid to remove the unlighted portion.
Then, the first exposure process is performed on the photosensitive film 300 using the above-described exposure mask of FIG. 2. In this case, the light corresponding to the
3B and 3C, the second exposure process is performed on the photosensitive film 300 on which the first exposure process is performed. In this case, a portion where light is not transmitted is defined as the second non-exposed area 300b.
The above-described secondary exposure process uses an exposure mask used in the primary exposure process without replacing the exposure mask, but it is preferable to move the exposure mask by a certain distance. In this case, the second exposure process is preferably moved in the X and Y directions by '2 / 3W' of the light shielding pattern (210 in FIG. 2). That is, it shifts by 1/2 pitch of the light shielding pattern (210 of FIG. 2). As such, by using the first and second exposure processes as one exposure mask, an overlay error may be minimized during the double exposure process.
Here, since the secondary exposure process is performed on the photoresist film 300 on which the primary exposure process is performed, it may be divided into a region exposed once or a region exposed twice and an area not exposed.
However, in the negative type of exposure process, it is meaningless whether the exposure is performed once or twice. Therefore, it is possible to distinguish between an exposure area and an unexposed area where exposure is never performed. Here, the non-exposed
Next, the development process is performed to form the
Here, the portion where the first
Next, a hole pattern is formed by etching the lower etching layer (not shown) using the
As described above, the negative type double exposure process may be performed to form a hole pattern having a fine line width.
It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.
300:
310:
310b: second non-exposed area 320: hole
Claims (7)
Performing a first exposure process on the photosensitive film using an exposure mask to form an unexposed first region;
Moving the exposure mask to perform a second exposure process on the photosensitive film to form an unexposed second region; And
Developing the photoresist to form a photoresist pattern by overlapping the first region and the second region;
Pattern forming method of a semiconductor device comprising a.
The photosensitive film is a pattern forming method of a semiconductor device, characterized in that the positive or negative photosensitive film.
The exposure mask includes a plurality of light blocking patterns.
The light shielding pattern has a rectangular shape pattern forming method of a semiconductor device.
The light blocking patterns may be arranged to be spaced apart by 1/3 of the light shielding pattern line width.
And the second exposure process is performed by moving the exposure mask to the upper, lower, left and right sides.
And wherein the secondary exposure step is performed by moving the exposure mask by 2/3 of the light shielding pattern line width.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100020383A KR20110101405A (en) | 2010-03-08 | 2010-03-08 | Method for forming pattern of the semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020100020383A KR20110101405A (en) | 2010-03-08 | 2010-03-08 | Method for forming pattern of the semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20110101405A true KR20110101405A (en) | 2011-09-16 |
Family
ID=44953427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020100020383A KR20110101405A (en) | 2010-03-08 | 2010-03-08 | Method for forming pattern of the semiconductor device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR20110101405A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324563B2 (en) | 2013-07-11 | 2016-04-26 | Samsung Electronics Co., Ltd. | Methods of forming patterns |
-
2010
- 2010-03-08 KR KR1020100020383A patent/KR20110101405A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9324563B2 (en) | 2013-07-11 | 2016-04-26 | Samsung Electronics Co., Ltd. | Methods of forming patterns |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100843870B1 (en) | Method for manufacturing fine pattern of a semiconductor device | |
KR20020060269A (en) | Semiconductor integrated circuit device and method of producing the same, and method of producing masks | |
KR20090131889A (en) | Method for forming fine patterns of semiconductor device | |
KR101154007B1 (en) | Method for fabricating fine pattern | |
TWI722454B (en) | Method and system for improving critical dimension uniformity | |
KR20090001130A (en) | Exposure mask and method for manufacturing semiconductor device using the same | |
JP2004054115A (en) | Pattern layout method for photo-mask for pattern transfer and method of manufacturing photo-mask for pattern transfer and semiconductor device | |
CN103066070B (en) | Integrated circuit method with triple patterning | |
KR20110101405A (en) | Method for forming pattern of the semiconductor device | |
CN106610563B (en) | Mask and double patterning method | |
US20120214103A1 (en) | Method for fabricating semiconductor devices with fine patterns | |
US20100304568A1 (en) | Pattern forming method | |
US6767672B2 (en) | Method for forming a phase-shifting mask for semiconductor device manufacture | |
KR101159689B1 (en) | Method for forming overlay vernier in semiconductor device | |
KR101096191B1 (en) | Method for forming contact hole | |
KR100801738B1 (en) | Photo mask and the method for fabricating the same | |
JPH11133585A (en) | Mask for exposure and its production | |
KR101096209B1 (en) | Method for manufacturing the semiconductor device | |
KR20140096750A (en) | Exposing method and method of forming a pattern using the exposing method | |
KR20040046702A (en) | Method for forming fine pattern of semiconductor device using double exposure | |
KR20080073622A (en) | A photolithography method using dual tone scattering bar patterns | |
KR20120081653A (en) | Method for manufacturing mask of semiconductor device | |
KR100955168B1 (en) | Exposure mask and method for forming semiconductor device by using the same | |
KR100972910B1 (en) | Exposure mask and method for forming semiconductor device by using the same | |
KR20110101404A (en) | Method for manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WITN | Withdrawal due to no request for examination |