KR20110100875A

KR20110100875A - Delay circuit

Info

Publication number: KR20110100875A
Application number: KR1020100019947A
Authority: KR
Inventors: 김연옥
Original assignee: 주식회사 하이닉스반도체
Priority date: 2010-03-05
Filing date: 2010-03-05
Publication date: 2011-09-15

Abstract

The delay circuit of the present invention includes a variable resistor unit capable of receiving an adjustment signal and changing an internal resistance impedance value, and a variable capacitor unit capable of receiving an adjustment signal and changing an internal capacitor impedance value and receiving an input signal to the variable resistor. The delay time is adjusted according to the internal resistance impedance of the negative part and the internal capacitor impedance of the variable capacitor part to output an output signal.

Description

Delay Circuit

The present invention relates to a semiconductor integrated circuit, and more particularly to a delay circuit.

The delay circuit is a circuit that delays an input signal for a predetermined time and then outputs it. It is essentially used in securing a data settling time of a sense amplifier in a semiconductor memory and a non-overlap clock signal generating circuit. .

As a delay circuit of the semiconductor memory device, a delay circuit formed by connecting a plurality of inverter stages is used. In the delay circuit, a plurality of inverter stages use a CMOS MOS transistor in which a PMOS transistor and an NMOS transistor are connected in series. The delay circuit includes a capacitor and a resistor in the configuration of the CMOS transistor through an RC delay. Delay the input signal to generate the output signal.

1 is a circuit diagram of a general delay circuit. As shown in FIG. 1, the delay circuit includes a resistor (R) and a capacitor (C) in an inverter configuration of a PMOS transistor P and an NMOS transistor N which share an input signal in to each gate to receive the input signal. do. The delay circuit outputs the input signal in as an output signal out by varying the degree of delay according to the impedance capacity of the resistor R and the capacitor C inserted into the delay circuit.

In the delay circuit shown in FIG. 1, a resistor R is connected between the output terminal and the NMOS transistor N, but a delay circuit configured by connecting the resistor R between the output terminal and the PMOS transistor P also exists. The delay circuit includes a delay circuit configured by connecting a resistor R between an output terminal and a PMOS transistor P and a single delay circuit connecting a resistor R to an output terminal and an NMOS transistor N as shown in FIG. 1. Can be configured by connecting two dogs.

The delay time of such a delay circuit cannot be further adjusted after the production process is finished after the semiconductor device is produced. During semiconductor device development, if the semiconductor device development does not perform the desired operation because the delay time designed by the designer and the delay time required for the operation of the product after the package production process do not match, redesign and mask to reset the delay time. Development time and costs such as reproduction of revision and semiconductor device development products will increase. This increases the cost of semiconductor device development and extends the semiconductor device development period.

2 is a block diagram of a delay circuit group including a delay circuit according to the prior art.

The delay circuit group shown in FIG. 2 is configured by connecting a plurality of delay circuits according to the prior art in series and connecting the connection parts to the respective delay circuits. As described, the amount of time that the output signal (out) is output in the delay circuit compared to the time when the input signal (in) is input, that is, the delay time is determined according to the impedance capacity of the resistor (R) and the capacitor (C) . Since the impedance capacitances of the resistor R and the capacitor C are fixed, one delay circuit has a predetermined delay time. This delay circuit with a fixed delay time is applied as a disadvantage to ease of development and to response to changes in process characteristics during mass production. A delay circuit group including a plurality of delay circuits is configured as shown in FIG. 2 in case the delay time set during the semiconductor device development design and the delay time of the produced test product are different, and the optimal delay time should be set. The delay circuit group shown in FIG. 2 has delay times of 2 ns, 3 ns, 4 ns and 5 ns, depending on the design of the connection. If the delay time required during semiconductor device development changes, only the connection part can be redesigned, the mask can be changed, and reproduced to control the delay time. The necessity of redesigning and producing the connection according to the delay time required is a disadvantage in that the development period is long for the development of the semiconductor device and the cost of the semiconductor device development is increased. This disadvantage is also applied to mass-produced semiconductor devices. If the delay time is changed due to changes in process characteristics of the mass-produced semiconductor devices, there is a need to redesign and produce the semiconductor device to revert the changed delay time. Even in this case, a delay circuit with a fixed delay time is applied as a weak point. In the delay circuit group shown in FIG. 2, the delay time is adjusted in four steps of 2ns, 3ns, 4ns, and 5ns. If the delay time step is further adjusted as needed, the number of internal delay circuits required and the area of the total delay circuit group also need to be adjusted, which is a disadvantage in terms of semiconductor device development and area. In the delay circuit group shown in FIG. 2, the point of designing the connection in advance for the adjustment of the delay time also applies as a disadvantage in terms of the area of the semiconductor device.

SUMMARY OF THE INVENTION The present invention has been drawn to solve the above problems, and there is a technical problem to provide a delay circuit having strengths in process characteristics change during semiconductor device development and mass production. In addition, there is a technical problem to provide a delay circuit that can be easily divided by adjusting the delay time.

Delay circuit according to an embodiment of the present invention for achieving the above-described technical problem is a variable resistor unit that can receive an adjustment signal to change the internal resistance impedance value, can receive an adjustment signal to change the internal capacitor impedance value And a variable capacitor unit, and receives an input signal and outputs an output signal by adjusting a delay time according to the internal resistance impedance of the variable resistor unit and the internal capacitor impedance of the variable capacitor unit.

In addition, the inverted delay circuit according to an embodiment of the present invention for achieving the above-described technical problem is a variable resistor unit that can change the internal resistance impedance value by receiving a control signal, the internal capacitor impedance value is changed by receiving the control signal A variable capacitor unit that receives an input signal and adjusts a delay time according to the internal resistance impedance of the variable resistor unit and the internal capacitor impedance of the variable capacitor unit to invert and delay the input signal and output the output signal as an output signal. Contains wealth.

In addition, the edge delay circuit according to an embodiment of the present invention for achieving the above-described technical problem is to receive an input signal and a control signal and to invert and delay the input signal by varying the delay time according to the control signal to the first internal A first delay inverting unit for outputting as an output signal, the first internal output signal and the control signal are input, and a delay time is varied according to the control signal to invert and delay the first internal output signal to thereby delay the second internal output signal. And a second delay inversion unit for outputting the second delay inversion unit and an edge determination unit for receiving one of the input signal and the second internal output signal and selecting one of the input signal and the second internal output signal and outputting the selected one as an output signal.

The delay circuit of the present invention can diversify the test mode options of the semiconductor device and create the effect of reducing the cost and duration of the development of the semiconductor device.

In addition, the delay circuit of the present invention creates an effect of easily subdividing and controlling the delay time according to the control signal.

1 is a circuit diagram of a delay circuit according to the prior art,
2 is a block diagram of a delay circuit group according to the prior art;
3 is a block diagram of a delay circuit according to an embodiment of the present invention;
4 is a detailed block diagram of an exemplary embodiment of the variable resistor unit illustrated in FIG. 3;
5 is a detailed circuit diagram of the variable resistor unit shown in FIGS. 3 and 4;
6 is a detailed block diagram of an exemplary embodiment of the variable capacitor unit shown in FIG. 3;
7 is a detailed circuit diagram of the variable capacitor unit shown in FIGS. 3 and 6;
8 is a circuit diagram and a block diagram of an inversion delay circuit according to an embodiment of the present invention;
9 is a circuit diagram of an edge delay circuit according to another embodiment of the present invention.

3 is a block diagram of a delay circuit according to an embodiment of the present invention.

The delay circuit according to an embodiment of the present invention includes a variable resistor unit 100 and a variable capacitor unit 200.

The variable resistor unit 100 receives a control signal CTRL to change an internal resistance impedance value.

The variable capacitor unit 200 receives the control signal CTRL to change an internal capacitor impedance value.

The delay circuit receives an input signal in and outputs an output signal out through an RC delay. In a delay circuit using RC delay, the delay time depends on the resistance impedance and the capacitor impedance. The delay circuit may adjust the delay time by adjusting the resistance impedance in the variable resistor unit 100 and the capacitor impedance in the variable capacitor unit 200. In addition, since the resistance impedance and the capacitor impedance for adjusting the delay time of the delay circuit are adjusted according to the control signal CTRL, not a one-time recording device such as a fuse, the delay circuit is not fixed and fixed by the delay time. It can be flexibly adjusted according to the control signal CTRL.

A test mode signal TM may be used as the control signal CTRL.

FIG. 4 is a more detailed block diagram of the variable resistor unit 100 shown in FIG. 3.

The variable resistor unit 100 includes a bypass unit 110 and a resistor unit 120.

The bypass unit 110 is activated according to the control signal CTRL. The bypass unit 110 is connected to the resistor unit 120 to determine the operation as the resistance impedance of the resistor unit 120.

The resistor unit 120 is connected to the bypass unit 110, and an operation as a resistance impedance is determined according to whether the bypass unit 110 is activated.

The variable resistor unit 100 may be configured to operate as a resistance impedance depending on whether the bypass unit 110 and the bypass unit 110 are activated according to the control signal CTRL. The internal resistance impedance value is changed by adjusting the control signal CTRL input to the bypass unit 110 by including a plurality of combinations of the units 120.

FIG. 5 is a detailed circuit diagram of an example of the variable resistor unit 100 shown in FIGS. 3 and 4.

The variable resistor unit 100 shown in FIG. 5 includes the bypass unit 110 and the resistor unit 120 as shown in FIG. 4.

The bypass unit 110 includes a first resistance NMOS transistor RN1 connected between the first node n1 and the second node n2. The first resistance NMOS transistor RN1 is turned on or turned off in response to the first resistance control signal Rctrl1 receiving the first resistance control signal Rctrl1, which is the control signal CTRL, at a gate terminal thereof.

The resistor unit 120 includes a first resistor R1 connected between the first node n1 and the second node n2. The first resistor R1 is connected in parallel to the first resistor NMOS transistor RN1. When the first resistance control signal Rctrl1 is activated and the first resistance NMOS transistor RN1 is activated, the first resistance NMOS transistor RN1 is turned on to operate as a bypass of the first resistor R1. Therefore, the first resistor R1 connected between the first node n1 and the second node n2 does not operate as a resistance impedance. On the contrary, when the first resistance control signal Rctrl1 is inactivated and the first resistance NMOS transistor RN1 is inactivated, the first resistance NMOS transistor RN1 is turned off to bypass the first resistance R1. Since it does not operate as a pass, the first resistor R1 connected between the first node n1 and the second node n2 may be regarded as operating as a resistance impedance.

The variable resistor unit 100 shown in FIG. 5 includes a plurality of configurations, such as a connection of the first resistor NMOS transistor RN1 and the first resistor R1, to the first node n1 and the third node. It was configured between the nodes (n3) and configured by connecting n, for example. The control signal CTRL includes the first resistance control signal Rctrl1 to the nth resistance control signal Rctrln input to each of the first to nth resistance NMOS transistors RN1 to RNn. Accordingly, the variable resistance unit 100 may change an internal resistance impedance value by changing a combination of a plurality of resistance impedances according to the control signal CTRL.

FIG. 6 is a more detailed block diagram of the variable capacitor unit 200 shown in FIG. 3.

The variable capacitor unit 200 includes a switch unit 210 and a capacitor unit 220.

The switch unit 110 is activated according to the control signal CTRL. The switch unit 110 is connected to the capacitor unit 220 to determine the operation as the capacitor impedance of the capacitor unit 220.

The capacitor unit 220 is connected to the switch unit 210 and the operation as the capacitor impedance is determined according to whether the switch unit 210 is activated.

The variable capacitor unit 200 may be configured to operate as a capacitor impedance depending on whether the switch unit 210 and the switch unit 210 are activated according to the control signal CTRL. The internal capacitor impedance value is changed by adjusting the control signal CTRL input to the switch unit 210 by including a plurality of combinations of 220.

FIG. 7 is a detailed circuit diagram of an example of the variable capacitor unit 200 shown in FIGS. 3 and 6.

The variable capacitor unit 200 shown in FIG. 7 includes the switch unit 210 and the capacitor unit 220 as shown in FIG. 6.

The switch unit 210 includes a first capacitor NMOS transistor CN1 connected to a fourth node n4. The first capacitor NMOS transistor CN1 receives a first capacitor control signal Cctrl1, which is the control signal CTRL, at a gate terminal thereof and is turned on or off according to the first capacitor control signal Cctrl1.

The capacitor unit 220 includes a first capacitor C1 connected to the first capacitor NMOS transistor CN1. The first capacitor C1 is connected in series to the first capacitor NMOS transistor CN1. When the first capacitor control signal Cctrl1 is activated and the first capacitor NMOS transistor CN1 is activated, the first capacitor NMOS transistor CN1 is turned on to operate as a switch of the first capacitor C1. The first capacitor C1 connected to the fourth node n4 may be regarded as operating as a capacitor impedance. On the contrary, when the first capacitor control signal Cctrl1 is inactivated and the first capacitor NMOS transistor CN1 is inactivated, the first capacitor NMOS transistor CN1 is turned off to switch the first capacitor C1. Since the first capacitor C1 connected to the fourth node n4 does not operate as a capacitor impedance, the first capacitor C1 does not operate as a capacitor impedance.

The variable capacitor unit 100 illustrated in FIG. 7 includes a plurality of configurations, such as a connection between the first capacitor NMOS transistor CN1 and the first capacitor C1, and for example, n may be connected to each other. Configured. The control signal CTRL includes the first capacitor control signal Cctrl1 to n-th capacitor control signal Cctrln input to each of the first to n th capacitor NMOS transistors CN1 to CNn. Accordingly, the variable capacitor unit 200 may change an internal capacitor impedance value by changing a combination of a plurality of capacitor impedances according to the control signal CTRL.

8 is a circuit diagram and a block diagram of an inversion delay circuit according to an embodiment of the present invention shown in FIG. 3.

The inverted delay circuit shown in FIG. 8 includes a variable resistor unit 100 capable of receiving an adjustment signal CTRL and changing an internal resistance impedance value, and a variable capacitor unit capable of receiving an adjustment signal and changing an internal capacitor impedance value ( 200 and the input signal in, the delay time is adjusted according to the operation of the variable resistor unit 100 and the variable capacitor unit 200 to invert and delay the input signal in and delay the output signal (out). It includes an inverting unit 300 to output as ().

The variable resistor unit 100 is connected between the first node n1 and the second node n2 and receives the control signal CTRL. The variable capacitor unit 200 is connected to the second node n2 and receives the control signal CTRL. The variable resistor unit 100 and the variable capacitor unit 200 may be configured by the circuits shown in FIGS. 5 and 7, respectively.

The inverting unit 300 is connected between a power supply voltage Vdd and the second node n2 to receive the input signal in. The inverted PMOS transistor P0, the first node n1, and the ground are connected to each other. And an inversion NMOS transistor N0 connected between voltages to receive the input signal in. The inverting unit 300 receives the input signal in and delays according to the resistance impedance and the capacitor impedance determined by the variable resistor unit 100 and the variable capacitor unit 200 according to the control signal CTRL. Invert and delay by varying the time, and output as the output signal out.

9 is a circuit diagram of an edge delay circuit according to another embodiment of the present invention.

The edge delay circuit shown in FIG. 9 receives an input signal in and a control signal CTRL, and inverts and delays the input signal in by varying a delay time according to the control signal CTRL to thereby provide a first internal structure. The first delay inverting unit 400 outputs as an output signal int1, the first internal output signal int1, and the control signal CTRL are received, and the delay time is varied according to the control signal CTRL. The second delay inversion unit 500 and the input signal in and the second internal output signal int2 that invert, delay, and output the first internal output signal int2 as the second internal output signal int2 are outputted. An edge determination unit 600 receives an input and selects one of the input signal in and the second internal output signal int2 and outputs the output signal as an output signal out.

The first delay inversion unit 400 may be configured with the inversion delay circuits shown in FIGS. 5, 7, and 8. Like the inversion delay circuit shown in FIG. 7, the variable resistor unit 100, the variable capacitor unit 200, and the inversion unit 300 are included. Except for the names of the input and output signals are configured in the same manner, detailed description thereof will be omitted.

The second delay inversion unit 500 is similar in configuration to the first delay inversion unit 400. Like the inversion delay circuit shown in FIG. 8, the variable resistor unit 100, the variable capacitor unit 200, and the inversion unit 300 are included. Unlike the first delay inversion unit 400, a portion corresponding to the variable resistor unit 100 of the second delay inversion unit 500 is connected between the output node and the PMOS transistor. This is because the variable resistor unit 100 is set to be positioned in the current path in the delay operation of the first delay inversion unit 400 and the second delay inversion unit 500. The operation principle of the delay is the same. .

The edge determiner 600 includes a first inverter IV1 and a first NAND gate ND1. The first NAND gate ND receives the input signal in and the second internal output signal int2 to perform a NAND operation. Since the signal output from the NAND gate ND is inverted through the first inverter IV1, the edge determination unit 600 performs an AND operation on the input signal in and the second internal output signal int2. It outputs as the said output signal out.

The first internal output signal int1 is a signal in which the input signal in is delayed and inverted, and the second internal output signal int2 is a signal in which the first internal output signal int1 is delayed and inverted. The second internal output signal int2 is a delayed signal of the input signal in. The delay time of the second internal output signal int2 compared to the input signal in is the sum of the delay time of the first delay inversion unit 400 and the delay time of the second delay inversion unit 500.

The edge determining unit outputs the output signal out at a low level, which is the voltage level of the input signal in, regardless of the second internal output signal int2 when the input signal in is at a low level. If the signal in is at the high level, the output signal out is output at the voltage level of the second internal output signal int2 according to the voltage level of the second internal output signal int2.

As a result, the edge delay circuit shown in FIG. 9 directly outputs the input signal in if the input signal in is low level when the input signal in swings at high and low levels. ) And if the input signal in is at a high level, the input signal in is delayed and output as an output signal out. As a result, the waveform of the signal is delayed rising edge (rising edge) and falling edge (falling edge) is not delayed. The presence or absence of the delay of the rising edge and the falling edge shown in FIG. 9 is exemplified and according to the design of a person skilled in the art, that is, it is also possible to configure an edge delay circuit in which the rising edge is not delayed and the falling edge is delayed.

The delay circuit including the variable resistor unit 100 and the variable capacitor unit 200 shown in FIGS. 3, 8, and 9 may adjust the resistance impedance and the capacitor impedance by adjusting the control signal CTRL. Adjust. In addition, the delay time of the delay circuit is adjusted by adjusting the resistance impedance and the capacitor impedance. In addition, the delay time is not set and fixed, but may be fluidly changed according to the control signal CTRL. A test mode signal TM may be used as the control signal CTRL.

The delay time can be flexibly changed according to the control signal CTRL, which is an advantage in the development of a semiconductor device. When the delay time is changed by adjusting the control signal CTRL, it is not necessary to redesign or reproduce the delay time to change the delay time as in the conventional delay circuit. In addition, since the characteristics of the semiconductor device according to the changed delay time can be obtained faster than in the case of the semiconductor device using the delay circuit according to the prior art, it is easy to develop. This advantage also applies to mass production semiconductor devices. As the mass production of semiconductor devices proceeds, the characteristics of the semiconductor device may change according to the change in the characteristics of the process. The delay time also changes according to the characteristics of the semiconductor device. The changed delay time may be adjusted by adjusting the control signal CTRL.

In the delay circuit group using the delay circuit according to the related art shown in Fig. 2, a connection designed in advance for adjusting the delay time is required. When the delay time needs to be adjusted, the connection is redesigned and the semiconductor device is reproduced. These connections occupy additional area and are a weak point in the integration of semiconductor devices. In the delay circuit according to the present invention, since the control signal CTRL is adjusted to adjust the delay time, the connection unit is not required, and thus, the delay circuit is applied to the integration of semiconductor devices.

In the delay circuit group using the delay circuit according to the related art shown in Fig. 2, the adjustable delay times are four steps of 2ns, 3ns, 4ns and 5ns. Further subdivision of the delay time which can be controlled is also applied as a weak point in the integration of semiconductor devices because the necessary connection is increased according to the subdivision of the stage. In the delay circuit according to the present invention, the resistance impedance and the capacitor impedance may be adjusted according to the control signal CTRL, and the adjustment signal CTRL may be configured in plural as shown in FIGS. 5, 7, and 9. By combining the signals CTRL, the delay time can be easily segmented and adjusted.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: variable resistance section 110: bypass section
120: resistor 200: variable capacitor
210: switch portion 220: capacitor portion
300: inversion unit 400: first delay inversion unit
500: second delay inversion unit 600: edge determination unit

Claims

A variable resistor unit configured to receive an adjustment signal and change an internal resistance impedance value;
And a variable capacitor unit configured to receive the control signal and change an internal capacitor impedance value, and adjust an delay time according to the internal resistance impedance of the variable resistor unit and the internal capacitor impedance of the variable resistor unit by receiving an input signal. Delay circuit for outputting.

The method of claim 1,
And the variable resistor unit changes the internal resistance impedance value by changing a combination of a plurality of resistance impedances according to the control signal.

The method of claim 2,
The variable resistor unit may include a bypass unit activated according to the control signal; And
And a resistor unit connected to the bypass unit and configured to determine an operation as a resistance impedance depending on whether the bypass unit is activated.

The method of claim 3, wherein
And the bypass unit comprises a MOS transistor activated according to the control signal.

The method of claim 1,
And the variable capacitor unit changes the internal capacitor impedance value by changing a combination of a plurality of capacitor impedances according to the control signal.

The method of claim 5, wherein
The variable capacitor unit is a switch unit that is activated in accordance with the control signal; And
And a capacitor unit connected to the switch unit and determining an operation as a capacitor impedance depending on whether the switch unit is activated.

The method according to claim 6,
And the switch unit comprises a MOS transistor activated according to the control signal.

A variable resistor unit configured to receive an adjustment signal and change an internal resistance impedance value;
A variable capacitor unit configured to receive the control signal and change an internal capacitor impedance value;
An inversion delay circuit that receives an input signal and adjusts a delay time according to the internal resistance impedance of the variable resistor unit and the internal capacitor impedance of the variable capacitor unit to invert, delay, and output the input signal as an output signal. .

The method of claim 8,
And the variable resistor unit changes the internal resistance impedance value by changing a combination of a plurality of resistance impedances according to the control signal.

The method of claim 9,
The variable resistor unit may include a bypass unit activated according to the control signal; And
And a resistor unit connected to the bypass unit and configured to determine an operation as a resistance impedance depending on whether the bypass unit is activated.

The method of claim 10,
And the bypass unit comprises a MOS transistor activated according to the control signal.

The method of claim 8,
And the variable capacitor unit changes the internal capacitor impedance value by changing a combination of a plurality of capacitor impedances according to the control signal.

The method of claim 12,
The variable capacitor unit is a switch unit that is activated in accordance with the control signal; And
And a capacitor unit connected to the switch unit and determining an operation as a capacitor impedance depending on whether the switch unit is activated.

The method of claim 13,
And the switch unit comprises a MOS transistor activated according to the control signal.

A first delay inversion unit which receives an input signal and a control signal and inverts and delays the input signal by varying a delay time according to the control signal and outputs the first internal output signal;
A second delay inversion unit which receives the first internal output signal and the control signal and inverts and delays the first internal output signal by varying a delay time according to the control signal and outputs the second internal output signal as a second internal output signal; And
And an edge determination unit which receives the input signal and the second internal output signal and selects one of the input signal and the second internal output signal and outputs the output signal as an output signal.

The method of claim 15,
The first delay inverting unit may include a variable resistor unit configured to change an internal resistance impedance value by receiving the control signal;
A variable capacitor unit configured to receive the control signal and change an internal capacitor impedance value;
And a reversing unit configured to receive the input signal, invert the input signal by adjusting a delay time according to the internal resistance impedance of the variable resistor unit and the internal capacitor impedance of the variable capacitor unit, and invert and delay the input signal as the first internal output signal. Edge delay circuit, characterized in that.

17. The method of claim 16,
And the variable resistor unit changes the internal resistance impedance value by changing a combination of a plurality of resistance impedances according to the control signal.

The method of claim 17,
The variable resistor unit may include a bypass unit activated according to the control signal; And
And a resistor unit connected to the bypass unit and configured to determine an operation as a resistance impedance depending on whether the bypass unit is activated.

The method of claim 18,
And the bypass unit comprises a MOS transistor activated according to the control signal.

17. The method of claim 16,
And the variable capacitor unit changes the internal capacitor impedance value by changing a combination of a plurality of capacitor impedances according to the control signal.

The method of claim 20,
The variable capacitor unit is a switch unit that is activated in accordance with the control signal; And
And a capacitor unit connected to the switch unit and determining an operation as a capacitor impedance depending on whether the switch unit is activated.

The method of claim 21,
And the switch unit comprises a MOS transistor activated according to the control signal.

The method of claim 15,
The second delay inversion unit may include a variable resistor unit configured to change an internal resistance impedance value by receiving the control signal;
A variable capacitor unit configured to receive the control signal and change an internal capacitor impedance value;
And an inverting unit receiving the first internal output signal and inverting the delayed input signal by delaying the delayed signal according to the operation of the variable resistor unit and the variable capacitor unit, and outputting the second internal output signal as the second internal output signal. Edge delay circuit.

The method of claim 23,
And the variable resistor unit changes the internal resistance impedance value by changing a combination of a plurality of resistance impedances according to the control signal.

The method of claim 24,
The variable resistor unit may include a bypass unit activated according to the control signal; And
And a resistor unit connected to the bypass unit and configured to determine an operation as a resistance impedance depending on whether the bypass unit is activated.

The method of claim 25,
And the bypass unit comprises a MOS transistor activated according to the control signal.

The method of claim 23,
And the variable capacitor unit changes the internal capacitor impedance value by changing a combination of a plurality of capacitor impedances according to the control signal.

The method of claim 27,
The variable capacitor unit is a switch unit that is activated in accordance with the control signal; And
And a capacitor unit connected to the switch unit and determining an operation as a capacitor impedance depending on whether the switch unit is activated.

29. The method of claim 28,
And the switch unit comprises a MOS transistor activated according to the control signal.

The method of claim 15,
And the edge determining unit selects one of the input signal and the second internal output signal according to the input signal and outputs the selected output signal as an output signal.