KR20110095676A - Fabrication method of single crystalline silicon stacked array and 3d nand flash memory array using the same - Google Patents

Abstract

PURPOSE: A method for forming a single crystal STAR(Stacked Array) structure and a three dimensional NAND flash memory array using the same are provided to independently contact each layer through one photolithography process by etching each semiconductor layer of a contact unit with a step shape. CONSTITUTION: A contact unit(116) is formed by vertically laminating a plurality of single crystal semiconductor layers while interposing an insulation layer. A cell forming unit(216) is connected to each single crystal semiconductor layer of the contact unit through two or more lines. The insulation layer is formed between the lines. The plurality of single crystal semiconductor layers is vertically laminated. A plurality of control gates(300) vertically surrounds two or more lines adjacent to a plurality of line selection gates and is horizontally separated while interposing the insulation layer with a charge storage layer. A ground selection gate vertically surrounds two or more lines while interposing the gate insulation layer.

Description

FIELD OF THE INVENTION Single crystal star structure formation method and three-dimensional NAND flash memory array using the same

The present invention relates to a method of manufacturing a semiconductor memory array having a three-dimensional structure, and to a NAND flash memory array using the same. More specifically, a stacked array structure of single crystal silicon (STAR structure: STACKed ARray structure, hereinafter referred to as 'star structure') And a three-dimensional NAND flash memory array using the same.

The semiconductor memory field has continuously pursued high integration in order to reduce costs per bit, and low power driving has become a major issue as it is applied as a core component to mobile devices.

As there is a certain limitation in the process of scaling down and densifying memory cells having a conventional two-dimensional planar structure, memory cells having various three-dimensional structures, such as vertical channels, have recently been developed.

One of the memory cells having a three-dimensional structure is formed in a star structure, which is described by the applicant of Korean Patent Application No. 10-2008-0102209 (a semiconductor device having a star structure and a method of manufacturing the same) and Korean Patent Application No. No. 10-2009-0062653 (NAND flash memory array having a star structure and a manufacturing method thereof) has been filed in advance.

In the above-mentioned patent document, the semiconductor layer used as the active region is not necessarily limited to a single crystal semiconductor (for example, single crystal silicon), but it is preferable to form a star structure with a single crystal semiconductor for low power driving.

However, even if a star structure is formed of a single crystal semiconductor, the above-mentioned patent document discloses that a partitioning layer and a groove filling material having the same or similar etch rate are formed around the semiconductor layer (single crystal semiconductor layer) to form a partition between layers and bits. When supporting between lines and then forming an insulating film (eg, ONO) including the gate insulating film or the charge storage layer, the area is consumed by the thickness of the insulating film including the gate insulating film or the charge storage layer, which may adversely affect the degree of integration. If a word line is formed of a gate material immediately after forming an insulating film including a gate insulating film or a charge storage layer without forming a partition, there is a problem in that each semiconductor layer (monocrystalline semiconductor layer) cannot be properly supported.

Moreover, in the star structure, the technique of contacting each semiconductor layer (single-crystal semiconductor layer) laminated vertically independently or all the semiconductor layers simultaneously is desired.

Therefore, the present invention has been proposed to solve the problems of the prior art, in forming a star structure in which a plurality of single crystal semiconductor layers are stacked vertically, each semiconductor layer is sufficiently supported so as not to collapse during the process, and To provide a method of forming a single crystal star structure capable of electrically separating each semiconductor layer so as not to stick to each other and contacting each semiconductor layer independently or simultaneously, and a three-dimensional NAND flash memory array using the same. There is this.

In order to achieve the above object, the method for forming a single crystal star structure according to the present invention is to repeat the "stacking layer-> single crystal semiconductor layer" two or more times n times by epitaxial method on a predetermined semiconductor substrate. a first step of forming an n + 1 th stacking layer once more on the n th single crystal semiconductor layer, and then forming a first etching mask on the n + 1 th stacking layer; Forming a fence-like laminated structure having a contact portion and a cell forming portion by sequentially etching the n + 1th stacking layer from the n + 1th stacking layer using the first etching mask A second step; Depositing and planarizing an insulating film on the entire surface of the substrate, and then forming a second etching mask; Anisotropically etching the insulating film using the second etching mask to expose the stacked structure of the fence shape, and then etching only the single crystal semiconductor layer by etching the exposed stacking layer; Removing the second etching mask, depositing and planarizing an insulating layer on the entire surface of the substrate, and forming a third etching mask so as to cover a portion opened by the second etching mask; Anisotropically etching the insulating film using the third etching mask to expose the laminated structure of the fence shape, and then etching only the single crystal semiconductor layer by etching the exposed stacking layer; And removing the third etching mask, and depositing and planarizing an insulating layer on the entire surface of the substrate.

In addition, in order to contact each single crystal semiconductor layer constituting the contact portion by the method for forming a single crystal star structure according to the present invention,

After the seventh step, a fourth etching mask is formed to cover each single crystal semiconductor layer and to be aligned with the end of the contact portion, and the insulating layer is anisotropically etched using the fourth etching mask to end the contact portion. An eighth step of revealing; A ninth step of forming a sidewall spacer in contact with an end of the contact portion by laminating and anisotropically etching an spacer material layer having the same or similar etch rate as that of the single crystal semiconductor layer on the entire surface of the substrate; A tenth step of depositing an insulating film on the entire surface of the substrate and flattening the sidewall spacers to be exposed; Or an eleventh step of performing isotropic etching so that the single crystal semiconductor layers forming the contact portion by etching the sidewall spacers are etched in a step shape, or

The first etching mask of the first step may be formed with different thicknesses to form one or more steps on the contact part, and the contact part may be formed with one or more steps in the fence-like stacked structure of the second step. And an eighth step of anisotropically etching the insulating film after the seventh step to expose each step of the contact portion. A ninth step of depositing at least one sidewall spacer in contact with each step of the contact portion by laminating and anisotropically etching a spacer material layer having the same or similar etch rate as the single crystal semiconductor layer on the entire surface of the substrate; Depositing an insulating film on the entire surface of the substrate and etching anisotropically to form at least one insulating film spacer next to each sidewall spacer; The method may further include an eleventh step of etching the sidewall spacers and performing isotropic etching so that the single crystal semiconductor layers forming the contact portion are etched in a step shape.

The NAND flash memory array having a single crystal star structure according to the present invention is a single crystal star structure manufactured by the method of forming a single crystal star structure according to the present invention, and has a single protruding length with an insulating film interposed therebetween as a line on a semiconductor substrate. A fence-shaped contact portion in which a plurality of single crystal semiconductor layers different from each other are vertically stacked; A fence-shaped cell forming part connected to each of the single crystal semiconductor layers of the contact portion by two or more lines, and having a single insulating semiconductor layer stacked vertically with each other having an insulating film therebetween; A plurality of line selection gates formed on one side of the cell forming unit and vertically wrapped with one gate insulating layer interposed therebetween; A plurality of control gates vertically wrapped with two or more lines adjacent to the plurality of line selection gates with an insulating layer including a charge storage layer interposed therebetween and spaced apart at a predetermined distance from each other; And a ground select gate formed around the plurality of control gates and vertically surrounding the two or more lines with a gate insulating layer interposed therebetween.

Here, each of the control gate and the ground selection gate is electrically connected to a word line and a ground selection line in a direction perpendicular to each line of the cell forming unit, and each of the line selection gates is in a direction perpendicular to the word line. A bit selection line may be electrically connected, and a bit line may be electrically connected to one protrusion of each single crystal semiconductor layer of the contact portion in a direction parallel to the bit selection line.

In addition, another type of NAND flash memory array having a single crystal star structure according to the present invention is a single crystal star structure manufactured by the method of forming a single crystal star structure according to the present invention, wherein a single line on a semiconductor substrate is provided between insulating films. A fence-shaped contact portion in which a plurality of single crystal semiconductor layers having different protrusion lengths from each other are vertically stacked; A fence-shaped cell forming part connected to each of the single crystal semiconductor layers of the contact portion with nCr lines and having a single insulating semiconductor layer stacked vertically with an insulating film therebetween; A plurality of line select gates formed on one side of the cell forming unit and vertically wrapped with r gate insulating films interposed therebetween; A plurality of control gates formed vertically surrounding the nCr lines adjacent to the plurality of line selection gates with an insulating layer including a charge storage layer interposed therebetween and spaced apart at a predetermined distance from each other; And a ground select gate formed to vertically surround the nCr lines with a gate insulating layer therebetween adjacent to the plurality of control gates, wherein each of the control gate and the ground select gate includes each line of the cell forming unit; Word lines and ground select lines are electrically connected in a vertical direction, respectively, and the plurality of line select gates are electrically connected to n bit select lines in a direction parallel to the word line, respectively. The bit line is electrically connected to one side of the single crystal semiconductor layer in a direction perpendicular to the n bit selection lines, and r is a natural number close to the median of the number n of bit selection lines.

In the method of forming a single crystal star structure according to the present invention, the epitaxial growth of the single crystal semiconductor layer using the stacking layer and the two insulating film replacement processes are sufficient to support each semiconductor layer during the process so that they do not stick to each other and are etched through the spacer. By etching each semiconductor layer of the contact portion in a step shape, it is possible to contact each layer independently in a single photolithography process.

In addition, an NAND flash memory array having a single crystal star structure according to the present invention may utilize an insulating film (eg, ONO) including a gate insulating film or a charge storage layer between word lines while taking advantage of a star structure capable of increasing bit lines vertically. This solves the problem of the conventional area consumption, which takes up as much as the thickness, and forms r line selection gates for each line of the cell forming unit and connects them to n bit selection lines, where r is a natural number close to the median of n. By making it possible to select as many horizontal bit lines nCr as possible, it is possible to relatively reduce the number of bit selection lines, thereby reducing the area of the bit selection line driving circuit.

1 to 9 is a process perspective view showing each embodiment step by step according to the method of forming a single crystal star structure of the present invention.
FIG. 10A is a cross-sectional view taken along the AA ′ cutting line of FIG. 9 and illustrates an example in which a plurality of single crystal semiconductor layers are etched in a step shape through polysilicon sidewall spacer etching, and FIGS. 10B and 10C are polysilicon sidewalls. Another example showing that a plurality of single crystal semiconductor layers can be etched in a step shape by using a spacer and an insulating film spacer.
FIG. 11 illustrates one vertical stacked structure manufactured according to the method for forming a single crystal star structure according to the present invention, having one side having a stepped contact portion and three line forming vertically connected contact portions with three lines. It is an illustration.
12 and 13 are partial exploded perspective views schematically illustrating a three-dimensional NAND flash memory array that may be manufactured by the method for forming a single crystal star structure of the present invention.
FIG. 14 is a circuit diagram illustrating the formation of line select gates per line for maximally selecting the horizontal bit lines of FIG. 13 and an arrangement of bit select lines connected to the line select gates.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

Example of Forming Single Crystal Star Structure

An embodiment according to the method for forming a single crystal star structure of the present invention will be described with reference to FIGS. 1 to 9.

First, as predicted in FIG. 1A, the "layered layer 21-> single crystal semiconductor layer 31" is repeatedly laminated two or more times on a predetermined semiconductor substrate 10 by an epitaxy method. After forming (repetitively formed three times in FIG. 1A for convenience of drawing), the n + 1th stacking layer (the fourth stacking medium in FIG. 1A) on the nth single crystal semiconductor layer (35th single crystal semiconductor layer: 35 in FIG. 1A). After the layer 27) is formed once more, a first etching mask (not shown) is formed on the n + 1 th stacking layer 27 (first step), and as shown in FIG. 1A, the first etching is performed. Fence shape having contact portion 110 and cell forming portion 210 by sequentially etching the n + 1 th stacking layer 27 to the n " single crystal semiconductor layer / stacking layer " To form a laminated structure (second step).

Here, the stacking layers 21, 23, 25, and 27 are epitaxially grown to separate the single crystal semiconductor layers 31, 33, and 35 from the substrate 10 to be spaced vertically apart. It is used for laminating and electrically separating each single crystal semiconductor layer (hereinafter, abbreviated as " semiconductor layer ") by filling it with an insulating film 40, followed by etching. .

Therefore, the lamination media layer 21, 23, 25, 27 has a lattice structure similar to the material of the substrate 10 and the semiconductor layers 31, 33, 35, so that the lamination by epitaxy is performed. Any material can be used as long as it is easy and the material and the etching selectivity of the semiconductor layers 31, 33, 35 are large. For example, when the material of the substrate 10 and the semiconductor layers 31, 33, 35 is silicon (Si), the material of the stacking media layers 21, 23, 25, 27 is silicon germanium (SiGe). Is preferably. In this case, the content ratio of germanium in the silicon germanium (SiGe) is preferably adjusted within about 28% in consideration of the etching selectivity with silicon.

The material of the first etching mask (not shown) may be any material as long as the material has a high etching selectivity with respect to the stacking layers 21, 23, 25, and 27 and the semiconductor layers 31, 33, and 35. In the case where the material of the stacked media layers 21, 23, 25, 27 is silicon germanium (SiGe), and the material of the semiconductor layers 31, 33, 35 is silicon (Si), nitride is preferable. Do.

On the other hand, the specific shape of the fence-shaped contact portion and the cell formation portion formed by the repeated lamination of the "layered layer-> semiconductor layer" is determined according to the pattern of the first etching mask.

That is, as shown in FIG. 1A, the cell forming unit 210 is formed of two or more lines (eg, 27a, 27b, and 27c), and one side of the cell forming unit 210 is connected in common with each of the lines. One line (eg, 27) may be formed to form the contact portion 110.

1A may be applied to a NAND flash memory as described later. In this case, the contact unit 110 may contact each semiconductor layer 31, 33, 35 independently to provide a kind of vertical structure. It acts as a bit line, and the cell forming unit 210 is stiffened into two or more lines (a kind of horizontal bit line) like a finger in the vertical bit lines 31, 33, and 35 of each layer, and connected to the bit select line. The line select gates, the control gates connected to the word line, and the ground select gate connected to the ground select line are formed to form various selection transistors or memory cells.

In addition, as shown in FIG. 1B, the cell forming unit 220 is formed of two or more lines (eg, 28a, 28b, 28c), and two of the cell forming units 220 are connected to one side of the cell forming unit 220. The contact line 120 may be formed by the above line.

1B may be applied to a NOA flash memory, in which case each semiconductor layer of each line (eg, a line: 32a, 34a, 36a) may be used as one word line. The contact unit 120 is a part for contacting each word line independently, and the cell forming unit 220 is a part in which bit lines for contacting the source / drain of each cell are vertically intersecting each line.

Since the method of manufacturing a Noah flash memory array using a fence-like stacked structure as shown in FIG.

Thereafter, as shown in FIG. 2, the insulating film 40 is deposited and planarized on the entire surface of the substrate, and a second etching mask is formed (third step).

Here, the insulating film 40 may be an oxide film, and the second etching mask may be a nitride film, and the first etching mask may be removed before deposition of the insulating film 40, but the first etching mask is formed of a nitride film. If it is, it can be left and used as an etch stopper when the oxide film is planarized to CMP after deposition.

Subsequently, as shown in FIG. 3, the insulating layer is anisotropically etched using the second etching mask 52 to expose the fence-shaped stacked structure 210, and as shown in FIG. The stacking layer (eg, 27a1) is etched to expose only the single crystal semiconductor layer (eg, 35a) (fourth step).

Thereafter, the third and fourth steps are repeated, the second etching mask 52 is removed, the insulating film 40 is deposited and planarized on the entire surface of the substrate, and the second etching mask is as shown in FIG. 5A. Forming a third etching mask 54 so as to cover the opened portion (fifth step), and stacking the fence-shaped layer that was covered by anisotropically etching the insulating layer using the third etching mask 54. After revealing the structure 212, the layered layer of the exposed layered structure 212 is etched to reveal only the single crystal semiconductor layer (sixth step).

At this time, the third etching mask 54 during the fifth step process, as shown in Figure 5b, is formed to cover the other side of the cell forming portion 210 together, the cell forming portion 210 if necessary later In each line of the edge, a "silicon germanium layer-> single-crystal silicon layer" is repeatedly stacked on a P-type silicon substrate, and a common source line is electrically connected to the top layer doped with N-type impurities. 13b).

Thereafter, the third etching mask 54 is removed, and the insulating film 40 is deposited and planarized on the entire surface of the substrate (seventh step).

As described above, by performing the second insulating film replacement process, each semiconductor layer can be sufficiently supported so as not to stick to each other during the process.

Hereinafter, a step for forming a step, that is, a step shape, in one end of the semiconductor layers surrounded by the insulating layer 46 in the contact portion 110 will be described.

This is performed immediately after the second insulating film replacement process as shown in FIGS. 6A and 6B, but after forming the line selection gate 200 and the control gate 300 in the cell forming unit 212 as shown in FIG. 6C. You can also proceed. Although the latter may be the case, the process number is used for convenience of description.

After the seventh step, as shown in FIGS. 6A to 6C, each of the single crystal semiconductor layers is covered (of course, when the line selection gate and the control gate are formed as shown in FIG. 6C, they are also covered). The fourth etching masks 56 and 57 are formed to be aligned with the ends of the 112 and 122, and the insulating layers 46 and 47 are anisotropically etched using the fourth etching masks 56 and 57, respectively. The end of the contact portion is revealed (step 8).

The fourth etching masks 56 and 57 may be formed of nitride, similar to each of the previous etching masks.

Subsequently, as shown in FIG. 7, a layer of a spacer material having the same or similar etch rate as that of the single crystal semiconductor layer is deposited on the entire surface of the substrate, and then anisotropically etched to form a sidewall spacer 60 in contact with the end of the contact portion. ).

Here, when the single crystal semiconductor layer is made of single crystal silicon, the spacer material layer preferably uses a silicon-based material layer (for example, polysilicon, amorphous silicon, etc.) for deposition and etching.

Thereafter, as shown in FIG. 8, an insulating film 48, such as an oxide film, is deposited on the entire surface of the substrate and planarized so that the sidewall spacer 60 is exposed (step 10). In this case, when the fourth etching mask 56 is formed of nitride, the fourth etching mask 56 serves as an etching stopper in the planarization process by CMP.

Next, as shown in FIG. 9, the isotropic etching is performed to etch the sidewall spacers 60 and to form the stepped portions of the single crystal semiconductor layers 31, 33, and 35 forming the contact portion 112 (second step). Step 11).

In this case, a known chemical dry etcher may be used for isotropic etching.

The process principle according to the eleventh step is illustrated in cross-sectional view taken along line AA ′, which is a cutting line passing through the single crystal semiconductor layers 31, 33, and 35 forming the contact portion 112 in FIG. 9.

That is, the sidewall spacers 60 having the same or similar etch rate as the single crystal semiconductor layers 31, 33, and 35 are first etched by isotropic etching, so that the upper semiconductor layers are large and the lower semiconductor layers are relatively small. It becomes a staircase shape.

By performing the etching process through the spacer as described above, there is an advantage that the contact problem of each semiconductor layer, which is essentially required in the vertical stacked structure (ie, the star structure), can be solved by a single photolithography process.

The etching process through the spacer may be applied and implemented as follows.

That is, when the single crystal semiconductor layer of the contact portion 112 to give a step-shaped step increases, some of the single crystal semiconductor layers of the contact portion 112 are first etched to form a step, and then the sidewall spacer is formed using the step. And isotropic etching may be performed using the insulating film spacer.

As a specific example, the first etching mask of the first step is formed with different thicknesses to form one or more steps on the contact portion 110, and then, in the second step, the first etching mask is used. In this case, the relatively thin first etch mask portion may be etched more so that the fence-shaped contact portion 110 may form at least one step.

Thereafter, the process may be performed as follows instead of the eighth to eleventh steps.

After the seventh step, the insulating layer is anisotropically etched to expose each step of the contact portion (eighth step).

Subsequently, a spacer material layer (eg, a silicon-based material layer) having the same or similar etch rate as that of the single crystal semiconductor layer (eg, single crystal silicon) is deposited on the front surface of the substrate, and anisotropically etched to contact each step of the contact portion and at least one sidewall. Spacers 62 and 64 are formed (ninth step, see Fig. 10B).

Next, an insulating film 40 such as an oxide film is again deposited on the entire surface of the substrate, and anisotropically etched to form one or more insulating film spacers 41 and 43 next to each of the side wall spacers 62 and 64 (step 10). , See FIG. 10B).

Thereafter, as shown in FIG. 10C, each of the single crystal semiconductor layers 31, 32, 33 (34, 35, 36) forming the contact portion 110 by etching each of the sidewall spacers 62 and 64 is a step. An isotropic etching is performed to etch into the shape (step 11).

Therefore, when the insulating film is anisotropically etched after the etching process through the spacer in the state as shown in FIG. 6A, a vertical stacked structure having a fence shape having the contact portion 114 and the cell forming portion 214 as shown in FIG. 11 is obtained. It becomes possible.

<First Embodiment of NAND Flash Memory Array Structure>

Next, an example of a NAND flash memory array structure having a single crystal star structure manufactured by the embodiment of the method for forming a single crystal star structure will be described.

12, the plurality of single crystal semiconductor layers 31 ′, 33 ′, 35 ′, and 37 ′ having different protruding lengths on one side with the insulating layer 46 interposed therebetween as one line on the semiconductor substrate 10. A fence-shaped contact portion 114 in which vertically stacked); Each single crystal semiconductor layer (eg, 37 ') of the contact portion 114 is connected to two or more lines (eg, BL41, BL42, BL43) and has an insulating film 46 therebetween for each line (eg, BL41). A wall-shaped cell forming unit 214 in which a plurality of single crystal semiconductor layers (eg, BL11, BL21, BL31, BL41) are vertically stacked; A plurality of line select gates 200 formed on one side of the cell forming unit and vertically wrapped with one gate insulating layer (not shown) between each line (eg, BL43); The two or more lines (eg, BL41, BL42, BL43) are vertically wrapped with an insulating layer (not shown) including a charge storage layer interposed therebetween adjacent to the plurality of line selection gates 200, and horizontally constant. A plurality of control gates 300 spaced apart from each other; A ground selection gate 400 formed to vertically surround the two or more lines (eg, BL41, BL42, BL43) with a gate insulating layer (not shown) adjacent to the plurality of control gates 300. It is configured by.

Of course, a plurality of single crystal semiconductor layers (eg, BL11, BL42, BL31, BL41) in which the plurality of line selection gates 200, the plurality of control gates 300, and the ground selection gate 400 are not formed. Each part of) is implanted with impurities.

However, when the plurality of control gates 300 are formed to be spaced apart within a predetermined distance (about 50 nm), the source / drain of each cell may be electrically formed by a fringing field. In this case, it is not necessary to implant impurity ions between the plurality of control gates 300.

Further, since the structure obtained as a result of the embodiment relating to the single crystal star structure forming method, each memory cell has a double gate structure.

In this case, in order for each memory cell to have a complete double gate structure, the n + 1 th stacking layer is formed as the first etching mask (for example, a nitride film) and is left as it is, leaving the first layer on the top layer of FIG. 12. It is desirable to have an etch mask.

The gate insulating layer of each of the line selection gate and the ground selection gate may be formed of an insulating layer (eg, an ONO layer) including the charge storage layer.

As shown in FIG. 12, each of the control gate 300 and the ground selection gate 400 has a word in a direction perpendicular to each line (eg, BL43) of the cell forming unit 214. A line (eg, WL3) and a ground select line (GSL) are electrically connected through the contact plug 72, and each of the line select gates 200 selects bits in a direction perpendicular to the word line (eg, WL1). A line (eg, BSL3) is electrically connected through the contact plug 76, and the bit selection line (eg, BSL3) is provided at one protrusion (eg, 31 ′) of each single crystal semiconductor layer of the contact portion 114. The bit line (eg, BL1) may be electrically connected through the contact plug 74 in a direction parallel to the direction of the contact plug 74.

By constructing a NAND flash memory array having a single crystal star structure as described above, an insulating film (eg, ONO) including a gate insulating film or a charge storage layer is interposed between word lines while taking advantage of a star structure capable of increasing bit lines vertically. It is possible to fundamentally solve the conventional area consumption problem, which takes up unnecessary amount of thickness.

In addition, although not shown in FIG. 12, "silicon germanium layer-> single-crystal silicon layer" is repeatedly stacked on the P-type silicon substrate 10 at each line of the edge of the cell forming portion adjacent to the ground selection gate 400. The common source line may be electrically connected to the top layer doped with the N-type impurity.

By doing the above, the silicon substrate 10 and the first silicon germanium layer (eg, 21a) can be insulated by a PN junction, but can be grounded through a common source line to each line of the cell forming unit 214. have.

Second Embodiment of NAND Flash Memory Array Structure

This is another example of the NAND flash memory array structure having the single crystal star structure manufactured by the embodiment of the method for forming the single crystal star structure, but unlike the first embodiment of the array structure, there are r pieces for each line of the cell formation portion. By forming line select gates and connecting n bit select lines, r is a natural number close to the median of n, so that as many horizontal bit lines (nCr) can be selected as possible, the number of bit select lines can be relatively reduced. It is designed to be.

Specifically, as shown in FIG. 13A, a plurality of single crystal semiconductor layers 31 ″, 33 ′, 35 ″ having different protruding lengths on one side with the insulating film 46 interposed therebetween on the semiconductor substrate 10. A wall-shaped contact portion 116 vertically stacked; Each single crystal semiconductor layer (eg, 37 '') of the contact portion is connected to nCr lines (eg, BL401, BL402, BL403, BL404, BL405, BL406, BL407, BL408, BL409, BL410) and each line (eg A fence-shaped cell forming portion 216 in which a plurality of single crystal semiconductor layers (eg, BL110, BL210, BL310, and BL410) are vertically stacked with an insulating film 46 therebetween for each BL410; A plurality of line select gates 200 formed on one side of the cell forming unit and vertically wrapped with r gate insulating films (not shown in FIG. 13A) between each line (eg, BL410); The nCr lines (eg, BL401, BL402, BL403, BL404, BL405, BL406, BL407, BL408, BL409, BL410) adjacent to the plurality of line selection gates 200 may include an insulating layer including a charge storage layer ( A plurality of control gates 300 which are vertically wrapped with a space between them and are horizontally spaced apart from each other; The nCr lines (eg, BL401, BL402, BL403, BL404, BL405, BL406, BL407, BL408, BL409, BL410) are adjacent to the plurality of control gates 300 between a gate insulating film (not shown). And a ground selection gate 400 which is formed to be wrapped vertically, and each control gate 300 and the ground selection gate 400 are perpendicular to each line (eg, BL410) of the cell forming unit 216. A word line (eg, WL3) and a ground select line (GSL) are electrically connected to each other through a contact plug 71 in one direction, and the word line (eg, WL1) is connected to the plurality of line select gates 200. N bit selection lines BSL1, BSL2, BSL3, BSL4, and BSL5 are electrically connected to each other through a contact plug in a direction parallel to each other, and the single crystals of the contact portion 116 The n bit selector is formed on one side of the semiconductor layer (eg, 31 ''). Bit lines (e.g., BL1) are electrically connected through the contact plug 73 in a direction perpendicular to the fields BSL1, BSL2, BSL3, BSL4, and BSL5, and r is an intermediate value of the number of bit selection lines n. It is a close natural number (e.g., n = 2r if n is even, n = 2r + 1 or n = 2r-1 if n is odd), and nCr is calculated as in Equation 1 below.

[Equation 1]

nCr = nPr / (r!) = n! / [(n-r)! r!]

Here, as in the first embodiment of the array structure, a plurality of single crystal semiconductor layers in which the plurality of line selection gates 200, the plurality of control gates 300 and the ground selection gate 400 are not formed Each part of them is implanted with impurities.

However, when the plurality of control gates 300 are formed to be spaced apart within a predetermined distance (about 50 nm), the source / drain of each cell may be electrically formed by a fringing field. In this case, it is not necessary to implant impurity ions between the plurality of control gates 300.

Further, since the structure obtained as a result of the embodiment relating to the single crystal star structure forming method, each memory cell has a double gate structure.

In this case, in order for each memory cell to have a complete double gate structure, the n + 1 th stacking layer is formed of the first etching mask (eg, nitride), and is left as it is, leaving the first layer on the top layer of FIG. 13A. It is desirable to have an etch mask.

The gate insulating layer of each of the line selection gate and the ground selection gate may be formed of an insulating layer (eg, an ONO layer) including the charge storage layer.

In addition, as shown in FIG. 13B, each line (eg, 37''a) of the edge 218 of the cell forming portion adjacent to the ground select gate 400 is formed on the P-type silicon substrate 10 by " silicon germanium layer. The single crystal silicon layer "may be repeatedly stacked and the common source line CSL may be electrically connected through the contact plug 75 on the top layer (eg, 37''a) doped with N-type impurities.

By doing so, the silicon substrate 10 and the first silicon germanium layer (eg, 21'a) are insulated by a PN junction while being grounded through a common source line (CSL) on each line of the cell formation unit 218. Can be enabled.

Therefore, unlike the first embodiment of the array structure, the second embodiment of the present array structure can relatively reduce the number of bit selection lines (BSLs), thereby reducing the area of the bit selection line driving circuit. It will work.

Formation of line select gates per line for maximally selecting horizontal bit lines BLn01, BLn02, BLn03, BLn04, BLn05, BLn06, BLn07, BLn08, BLn09, BLn10 according to the second embodiment of the present array structure And an example of an arrangement of bit select lines BSL1, BSL2, BSL3, BSL4, and BSL5 connected to the line select gates, are illustrated in FIG.

FIG. 14 is an electrical circuit diagram showing electrical connections in any layer in the structure shown at 200 in FIG. 13A or 13B.

10: Substrate
11, 13, 14: trench
21, 23, 25, 27: stacked media (eg, silicon germanium)
27a, 27b, 27c: stacking layer of cell forming portion connected to 27
31, 33, 35: single crystal semiconductor layer (e.g., single crystal silicon layer)
40, 48: insulating film (for example, oxide film)
41, 43: insulating film spacer
52, 54, 56, 57: etching mask
60, 62, 64: polysilicon sidewall spacer
71, 72, 73, 74, 75, 76: contact plug
110, 112, 114, 115, 120, 122: contact portion
200: line select gate
210, 212, 214, 216, 220, 222: cell forming portion
300: control gate
400: ground selection gate

Claims (12)

After "Layered Media-> Single Crystal Semiconductor Layer" is repeatedly stacked two or more times n times on a predetermined semiconductor substrate by an epitaxy method, the n + 1th stacking media layer is placed on top of the nth Single Crystal Semiconductor layer once. Further forming a first etching mask on the n + 1 th stacking layer;
Forming a fence-like laminated structure having a contact portion and a cell forming portion by sequentially etching the n + 1th stacking layer from the n + 1th stacking layer using the first etching mask A second step;
Depositing and planarizing an insulating film on the entire surface of the substrate, and then forming a second etching mask;
Anisotropically etching the insulating film using the second etching mask to expose the stacked structure of the fence shape, and then etching only the single crystal semiconductor layer by etching the exposed stacking layer;
Removing the second etching mask, depositing and planarizing an insulating layer on the entire surface of the substrate, and forming a third etching mask so as to cover a portion opened by the second etching mask;
Anisotropically etching the insulating film using the third etching mask to expose the laminated structure of the fence shape, and then etching only the single crystal semiconductor layer by etching the exposed stacking layer;
And removing the third etch mask and depositing and planarizing an insulating film on the entire surface of the substrate.
The method of claim 1,
The fence-shaped stacked structure of the second step may be configured to form the cell forming part with two or more lines, and to form the contact part with one line so as to be connected in common with the respective lines on one side of the cell forming part. Single crystal star structure formation method.
The method of claim 1,
The fence-shaped stack structure of the second step may be configured to form the cell forming portion with two or more lines, and to form the contact portion with two or more lines so as to be connected to each of the lines on one side of the cell forming portion. Formation of single crystal star structure.
The method according to claim 2 or 3,
The substrate and the single crystal semiconductor layer is silicon (Si),
The stacking layer is silicon germanium (SiGe),
The third etching mask of the fifth step is formed so as to cover the other side portion of the cell forming portion together.
The method according to any one of claims 1 to 3,
After the seventh step, a fourth etching mask is formed to cover each single crystal semiconductor layer and to be aligned with the end of the contact portion, and the insulating layer is anisotropically etched using the fourth etching mask to end the contact portion. An eighth step of revealing;
A ninth step of forming a sidewall spacer in contact with an end of the contact portion by laminating and anisotropically etching an spacer material layer having the same or similar etch rate as that of the single crystal semiconductor layer on the entire surface of the substrate;
A tenth step of depositing an insulating film on the entire surface of the substrate and flattening the sidewall spacers to be exposed;
And an eleventh step of performing isotropic etching so that the single crystal semiconductor layers forming the contact portion by etching the sidewall spacers are etched in a step shape.
The method according to any one of claims 1 to 3,
The first etching mask of the first step is formed with varying thickness to form one or more steps on the contact portion,
The method of claim 1, wherein the contact portion is formed by forming one or more steps in the fence-shaped stacked structure of the second step.
The method according to claim 6,
An eighth step of anisotropically etching the insulating film after the seventh step to expose each step of the contact portion;
A ninth step of depositing at least one sidewall spacer in contact with each step of the contact portion by laminating and anisotropically etching a spacer material layer having the same or similar etch rate as the single crystal semiconductor layer on the entire surface of the substrate;
Depositing an insulating film on the entire surface of the substrate and etching anisotropically to form at least one insulating film spacer next to each sidewall spacer;
And an eleventh step of performing isotropic etching so that the single crystal semiconductor layers forming the contact portion are etched into the sidewall spacers.
In a single crystal star structure prepared by claim 1,
A fence-shaped contact portion in which a plurality of single crystal semiconductor layers having different protrusion lengths on one side are vertically stacked with an insulating film interposed therebetween on a semiconductor substrate;
A fence-shaped cell forming part connected to each of the single crystal semiconductor layers of the contact portion by two or more lines, and having a single insulating semiconductor layer stacked vertically with each other having an insulating film therebetween;
A plurality of line selection gates formed on one side of the cell forming unit and vertically wrapped with one gate insulating layer interposed therebetween;
A plurality of control gates vertically wrapped with two or more lines adjacent to the plurality of line selection gates with an insulating layer including a charge storage layer interposed therebetween and spaced apart at a predetermined distance from each other;
NAND flash memory array having a single crystal star structure comprising a ground selection gate formed to surround the two or more lines vertically with a gate insulating film between the plurality of control gates.
The method of claim 8,
A word line and a ground selection line are electrically connected to each of the control gate and the ground selection gate in a direction perpendicular to each line of the cell forming unit.
A bit selection line is electrically connected to each of the line selection gates in a direction perpendicular to the word line;
NAND flash memory array having a single crystal star structure, characterized in that the bit line is electrically connected to one side of each of the single crystal semiconductor layer of the contact portion in a direction parallel to the bit selection line.
In a single crystal star structure prepared by claim 1,
A fence-shaped contact portion in which a plurality of single crystal semiconductor layers having different protrusion lengths on one side are vertically stacked with an insulating film interposed therebetween on a semiconductor substrate;
A fence-shaped cell forming part connected to each of the single crystal semiconductor layers of the contact portion with nCr lines and having a single insulating semiconductor layer stacked vertically with an insulating film therebetween;
A plurality of line select gates formed on one side of the cell forming unit and vertically wrapped with r gate insulating films interposed therebetween;
A plurality of control gates formed vertically surrounding the nCr lines adjacent to the plurality of line selection gates with an insulating layer including a charge storage layer interposed therebetween and spaced apart at a predetermined distance from each other;
And a ground select gate formed to vertically surround the nCr lines with a gate insulating layer therebetween adjacent to the plurality of control gates,
A word line and a ground selection line are electrically connected to each of the control gate and the ground selection gate in a direction perpendicular to each line of the cell forming unit.
The plurality of line select gates are electrically connected to n bit select lines in a direction parallel to the word line,
Bit lines are electrically connected to one protrusion of each of the single crystal semiconductor layers of the contact portion in a direction perpendicular to the n bit selection lines.
And wherein r is a natural number close to the middle value of the number n of bit select lines.
The method according to any one of claims 8 to 10,
On each line of the edge of the cell forming portion adjacent to the ground selection gate, a “silicon germanium layer-> single crystal silicon layer” is repeatedly stacked on a P-type silicon substrate and a common source line is electrically connected to a top layer doped with N-type impurities. NAND flash memory array having a single crystal star structure, characterized in that.
The method of claim 11,
And a gate insulating film of each of the line select gate and the ground select gate is formed of an insulating film layer including the charge storage layer.

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