KR20110094535A

KR20110094535A - Method for fabricating flexible substrate, thin film transitor and method for fabricating using the same

Info

Publication number: KR20110094535A
Application number: KR1020100013990A
Authority: KR
Inventors: 황춘섭
Original assignee: 주식회사 엔엔피
Priority date: 2010-02-17
Filing date: 2010-02-17
Publication date: 2011-08-24

Abstract

Disclosed are a method of manufacturing a flexible substrate, a thin film transistor using the same, and a method of manufacturing the same. In the method for manufacturing a flexible substrate according to an embodiment of the present invention, after preparing a mold substrate having a predetermined relief pattern, the mold substrate is combined with a first rotating roller to form a roller mold. Thereafter, the first substrate is passed between the roller mold and the second rotating roller formed to correspond to the first rotating roller at the lower portion of the roller mold, thereby forming a negative pattern on the first substrate.

Description

Method for manufacturing flexible substrate, thin film transistor using same and manufacturing method therefor {METHOD FOR FABRICATING FLEXIBLE SUBSTRATE, THIN FILM TRANSITOR AND METHOD FOR FABRICATING USING THE SAME}

Embodiments of the present invention relate to a technology for manufacturing a thin film transistor, and more particularly, to a technology for forming a thin pattern on a flexible substrate and manufacturing the thin film transistor using the same.

As the development of the information society is accelerated, people come into contact with various and vast information. The display device is a device that outputs such information as an image so that a person can visually contact it.

Conventionally, a cathode ray tube (CRT) is mainly used as the display device. However, due to a problem of heavy weight and bulkiness and high power consumption, a flat panel display (FPD) has recently been replaced. There is a situation.

The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), a vacuum fluorescent display (VFD), and an electroluminescence display (ELD).

As the flat panel display market expands rapidly, domestic and overseas flat panel display manufacturers are conducting a lot of research on manufacturing methods that can increase the area and significantly lower the process cost compared to the existing processes.

In particular, in the manufacturing process of the backplane (cost), which requires expensive equipment and complicated processes compared to other processes, studies to lower the manufacturing cost has been actively conducted.

In general, a backplane of a flat panel display includes a thin film transistor. To manufacture a thin film transistor, a process of depositing an electrode, an insulating film, and a semiconductor layer using a plurality of vacuum deposition methods, and photolithography for patterning each deposited layer into a desired shape ( Photo Lithography process is required.

1 is a view showing the structure of a conventional thin film transistor.

Referring to FIG. 1, a gate wiring 11 and a gate electrode are formed on a substrate 10, and a gate insulating layer 12 is formed on the substrate 10 to surround the gate wiring 11 and the gate electrode. do. The data line 13 is formed on the gate insulating layer 12 to cross the gate line 11 perpendicularly. Here, for the convenience of description, the process of forming other components will be omitted.

As described above, in the conventional thin film transistor, the gate wiring 11 and the gate electrode are formed on the substrate 10, so that the thickness of the thin film transistor is as thick as the thickness of the gate wiring 11 and the gate electrode. In this case, there is a problem against the tendency of light and small size of the flat panel display.

In addition, the surface of the substrate of the thin film transistor is not flat due to the step difference in the gate wiring 11 and the gate electrode. In this case, when the alignment layer is formed on the surface of the thin film transistor array substrate and the rubbing process is performed, Since the rubbing process is not properly performed in the stepped portion, it becomes impossible to control the liquid crystal molecules in a desired direction.

On the other hand, in order to minimize the problems caused by the steps present in the gate wiring 11 and the gate electrode, a method of reducing the thickness of the gate wiring 11 and the gate electrode has been proposed, in this case, the gate wiring 11 and the gate A signal delay occurs due to an increase in the resistance of the electrode, and a change in luminance occurs according to the signal delay, resulting in a problem of deterioration of image quality.

Embodiments of the present invention allow the gate electrode to be embedded in the intaglio pattern formed on the flexible substrate, thereby eliminating the step on the substrate formed by the gate electrode.

Other technical problems by the embodiments of the present invention can be understood by the following description, which can be realized by the means and combinations thereof shown in the claims.

Method for manufacturing a flexible substrate according to an embodiment of the present invention, (A) preparing a mold substrate having a predetermined relief pattern; (B) combining the mold substrate with a first rotating roller to form a roller mold; And (C) passing a first substrate between the roller mold and a second rotating roller formed below the roller mold to correspond to the first rotating roller to form an intaglio pattern corresponding to the embossed pattern on the first substrate. It includes a step.

A method of manufacturing a thin film transistor according to an embodiment of the present invention, in the method of manufacturing a thin film transistor having a substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, a drain electrode, and a protective film, (a) predetermined intaglio Forming a flexible substrate on which a pattern is formed; And (b) embedding a gate electrode in the engraved pattern.

A thin film transistor according to an embodiment of the present invention, a thin film transistor having a substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, a drain electrode, and a protective film, the substrate is formed with a negative pattern, the gate electrode Is embedded in the intaglio pattern of the substrate.

According to the exemplary embodiment of the present invention, the gate electrode is embedded in the intaglio pattern formed on the substrate, thereby reducing the thickness of the thin film transistor by the thickness of the gate electrode.

In addition, since there is no step on the substrate due to the gate electrode, a subsequent rubbing process may be smoothly performed, thereby improving the yield of the product.

In addition, since it is not necessary to reduce the thickness of the gate electrode, it is possible to prevent signal delay that appears as the thickness of the gate electrode is reduced.

In addition, by forming the intaglio pattern of the substrate through a stamp process, it is possible to simplify the manufacturing process of the flexible substrate, to reduce the manufacturing cost and manufacturing time, and to mass production. In addition, since the environmental waste is not generated in the process of forming the intaglio pattern, it is possible to implement an environmentally friendly process.

1 is a view showing the structure of a conventional thin film transistor.
2 is a view showing the structure of a gate buried thin film transistor according to an embodiment of the present invention.
3 to 10 are a cross-sectional view and a perspective view showing a method of manufacturing a gate buried thin film transistor of the present invention.
11 illustrates a substrate engravation method according to an embodiment of the present invention.
12 illustrates a substrate engravation method according to another embodiment of the present invention.
FIG. 13 is a SEM (Scanning Electron Micoscope) photograph showing a state in which a negative pattern is formed on a substrate according to an embodiment of the present invention. FIG.

Hereinafter, a method of manufacturing the flexible substrate, a thin film transistor using the same, and a method of manufacturing the same will be described with reference to FIGS. 2 to 13. However, this is only an exemplary embodiment and the present invention is not limited thereto.

In describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

As a result, the technical spirit of the present invention is determined by the claims, and the following examples are one means for efficiently explaining the technical spirit of the present invention to those skilled in the art to which the present invention pertains. It is only.

2 is a view showing the structure of a gate buried thin film transistor according to an embodiment of the present invention.

2, the gate buried thin film transistor includes a substrate 100, a gate electrode 110, a pad electrode 120, a gate insulating layer 130, a semiconductor layer 140, an ohmic contact layer 150, and a source electrode ( 160, a drain electrode 170, and a passivation layer 180.

The first intaglio pattern 101 and the second intaglio pattern 102 are formed to be spaced apart from each other so that the gate electrode 110 and the pad electrode 120 are embedded in the substrate 100. As the substrate 100, a flexible material (eg, a plastic film) may be used.

Here, the plastic film may be any one of polyethylene terephthalate, polycarbonate, polyimide, and polyethylenenaphthalate. However, the substrate 100 is not limited to the plastic film, and various materials other than the above may be used.

The gate electrode 110 and the pad electrode 120 are embedded in the first intaglio pattern 101 and the second intaglio pattern 102, respectively. The gate electrode 110 and the pad electrode 120 are, for example, gold (Au), silver (Ag), chromium (Cr), titanium (Ti), copper (Cu), aluminum (Al), tantalum ( Metals such as Ta, molybdenum (Mo), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), or metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) Or the like.

The pad electrode 120 is formed for electrical connection with an external device. For this purpose, the pad electrode 120 is removed by removing the gate insulating layer 130 and the passivation layer 180 formed on the pad electrode 120. To be exposed. The pad electrode 120 is formed to be connected to the gate electrode 110.

The gate insulating layer 130 is formed on the substrate 100. The gate insulating layer 130 may be, for example, an oxide film such as a silicon oxide film, a silicon nitride film, an aluminum oxide film, a tantalum oxide film, or an organic material such as polyvinyl phenol, polyvinyl alcohol, or polyimide. It may be made of.

The semiconductor layer 140 is formed in a region corresponding to the gate electrode 110 on the gate insulating layer 130. The semiconductor layer 140 forms a channel between the source electrode 160 and the drain electrode 170.

The semiconductor layer 140 may be formed of, for example, an inorganic material such as silicon (Si), germanium (Ge), zinc oxide (ZnO), or indium zinc oxide (IZO), or a pentacene-based or polythiophene. It may be made of organic materials such as series, Tetracene (Tetracene) series.

The ohmic contact layers 150 are formed to be spaced apart from each other on the semiconductor layer 140. The ohmic contact layer 150 is for ohmic contact between the source electrode 160, the drain electrode 170, and the semiconductor layer 140. The semiconductor layer 140 may be formed of an oxide semiconductor or amorphous silicon (n + a-Si: H) doped with impurities.

The source electrode 160 and the drain electrode 170 are formed on the gate insulating layer 130 to cover the side surface of the semiconductor layer 140 and to the upper portion of the ohmic contact layer 150, respectively.

The source electrode 160 and the drain electrode 170 are, for example, gold (Au), silver (Ag), chromium (Cr), titanium (Ti), copper (Cu), aluminum (Al), tantalum ( Metals such as Ta, molybdenum (Mo), tungsten (W), nickel (Ni), palladium (Pd), platinum (Pt), or metal oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) Or the like.

In addition, in order to electrically connect the drain electrode 170 to the outside, a portion of the passivation layer 180 formed on the drain electrode 170 is removed.

The passivation layer 180 is formed on the gate insulating layer 130, the source electrode 160, the semiconductor layer 140, and the drain electrode 170. The passivation layer 180 is to protect the thin film transistor from external shock and the environment. The passivation layer 180 may be formed of, for example, silicon oxide, silicon nitride, aluminum oxide, tantalum oxide, silicon oxynitride (SiON), or the like.

According to the exemplary embodiment of the present invention, the gate electrode 110 and the pad electrode 120 are embedded in the substrate 100 to form a thin film having a thickness of the gate electrode 110 and the pad electrode 120. The thickness of the transistor can be reduced.

In addition, since there is no step in the substrate 100, a subsequent rubbing process may be performed smoothly, thereby improving the yield of the product.

In addition, since it is not necessary to reduce the thickness of the gate electrode 110 and the pad electrode 120, it is possible to prevent signal delay that appears as the thickness of the gate electrode 110 and the pad electrode 120 is reduced. do.

3 to 10 are cross-sectional views and perspective views showing a method of manufacturing a gate-embedded thin film transistor of the present invention.

First, the first intaglio pattern 101 and the second intaglio pattern 102 are respectively formed in an area where the gate electrode of the substrate 100 is to be embedded and an area in which the pad electrode is to be embedded (FIG. 3). Here, the first intaglio pattern 101 and the second intaglio pattern 102 may be formed through a stamp process, which will be described later.

Next, the gate electrode 110 and the pad electrode 120 are embedded in each of the first intaglio pattern 101 and the second intaglio pattern 102 of the substrate 100 (FIG. 4). For example, the gate electrode 110 and the pad electrode 120 may be embedded in the first intaglio pattern 101 and the second intaglio pattern 102 of the substrate 100, for example, as follows. Method can be used.

1) Screen printing of the conductive paste on the substrate 100 using a squeegee. Then, the conductive paste may be filled in the first intaglio pattern 101 and the second intaglio pattern 102 to form the gate electrode 110 and the pad electrode 120. At this time, the conductive paste remaining in the other area on the substrate 100 is removed by pushing back to the squeegee. Meanwhile, the gate electrode 110 and the pad electrode 120 may be formed by further performing a plating process on the conductive paste filled in the first intaglio pattern 101 and the second intaglio pattern 102.

2) A conductive layer having a predetermined height is formed on the substrate 100 through a sputtering process. In this case, the height of the conductive layer is formed to be equal to the depth of the first intaglio pattern 101 and the second intaglio pattern 102. Thereafter, the conductive layer on the substrate 100 is removed through a polishing process or the like. Then, the conductive layer remains only on the first intaglio pattern 101 and the second intaglio pattern 102, thereby forming the gate electrode 110 and the pad electrode 120.

3) A mask is formed in an area except for portions in which the first intaglio pattern 101 and the second intaglio pattern 102 are formed, and a conductive layer having a predetermined height is formed through a sputtering process or the like. In this case, the height of the conductive layer is formed to be equal to the depth of the first intaglio pattern 101 and the second intaglio pattern 102. Thereafter, the mask is removed through a lift off process. Then, the mask and the conductive layer formed on the mask are removed, and the conductive layer remains only on the first intaglio pattern 101 and the second intaglio pattern 102 so that the gate electrode 110 and the pad electrode 120 are formed. Can be formed.

Next, a gate insulating layer 130 is formed on the substrate 100, and the semiconductor layer 140 and the ohmic contact layer 150 are formed in a region corresponding to the gate electrode 110 on the gate insulating layer 130. Formed sequentially (FIG. 5).

Next, a source / drain electrode layer 165 is formed on the gate insulating layer 130 to surround the semiconductor layer 140 and the ohmic contact layer 150 (FIG. 6).

Next, a portion of the source / drain electrode layer 165 is removed to form a source electrode 160 and a drain electrode 170 spaced apart from each other on the ohmic contact layer 150 (FIG. 7). The source electrode 160 and the drain electrode 170 may be formed on the gate insulating layer 130 to cover the side surface of the semiconductor layer 140 and to the upper portion of the ohmic contact layer 150, respectively.

Next, the portion exposed to the outside of the ohmic contact layer 150 is removed (FIG. 8). This is to prevent the source electrode 160 and the drain electrode 170 from being electrically connected to each other. At this time, the upper surface of the semiconductor layer 140 is exposed to the outside.

Next, a passivation layer 180 is formed on the gate insulating layer 130, the source electrode 160, the semiconductor layer 130, and the drain electrode 170 (FIG. 9).

Next, the gate insulating layer 130 and the passivation layer 180 formed on the pad electrode 120 are removed to expose the pad electrode 120 to the outside, and the passivation layer formed on the drain electrode 170. A portion of the 180 is removed to expose the drain electrode 170 to the outside (FIG. 10). In this case, the pad electrode 120 and the drain electrode 170 may be electrically connected to the outside.

The gate insulating layer 130, the semiconductor layer 140, the ohmic contact layer 150, the source / drain electrode layer 165, and the passivation layer 180 may be, for example, vacuum vapor deposition or chemical vapor deposition. ), Organic vapor phase deposition, spin coating, ink jet printing, offset printing, or the like.

11 is a view showing a substrate engravation method according to an embodiment of the present invention.

Referring to FIG. 11, first, a mold substrate 200 having a first embossed pattern 201 and a second embossed pattern 202 repeatedly formed is prepared (FIG. 11A). Here, the first embossed pattern 201 and the second embossed pattern 202 are formed in a shape corresponding to the first engraved pattern 101 and the second engraved pattern 102 of the substrate 100, respectively.

Next, the mold substrate 200 is bonded to the first rotating roller 220 to form a roller mold 250 (FIG. 11B). In this case, the mold substrate 200 and the first roller 200 may be bonded to each other by using an adhesive or the like.

Next, the substrate 100 is passed between the roller mold 250 and the second rotating roller 230 corresponding to the roller mold 250 so that the first intaglio pattern 101 and the first recess pattern are formed on the substrate 100. 2 intaglio pattern 102 is formed (FIG. 11C). This method is called a roller-to-roller method.

In this case, the substrate 100 may be a plastic film such as polyethyleneterephthalate, polycarbonate, polyimide, polyethylenenaphthalate, or the like.

Here, the process of forming the first intaglio pattern 101 and the second intaglio pattern 102 by passing the substrate 100 between the roller mold 250 and the second rotating roller 230 is 10 ℃ ~- It is carried out at a low temperature of 50 ° C.

This is because when the substrate 100 passes between the roller mold 250 and the second rotating roller 230, heat is generated by friction, and the substrate 100 may be deformed. Therefore, the process of forming the first intaglio pattern 101 and the second intaglio pattern 102 may include cooling means (not shown) for cooling the heat generated by the friction.

As such, when the intaglio pattern is formed using the roller-to-roller method, the substrate 100 on which the first intaglio pattern 101 and the second intaglio pattern 102 are formed can be manufactured in a short time. . In addition, the manufacturing process can be simplified compared to the case of forming the intaglio pattern by a photolithography process or an etching process, and there is an advantage of being environmentally friendly since no waste is generated.

That is, when the intaglio pattern is formed by a photolithography process or an etching process, environmental waste such as a chemical solution is generated in the process of forming the intaglio pattern, but according to an embodiment of the present invention, such an environmental waste does not occur, It is possible to implement friendly processes.

Meanwhile, the first intaglio pattern is formed through a stamping process using a mold substrate 200 on which the first relief pattern 201 and the second relief pattern 202 are formed as a master, without using a roller-to-roller method. The substrate 100 on which the 101 and the second intaglio patterns 102 are formed may be manufactured.

For example, the mold substrate 200 on which the first embossed pattern 201 and the second embossed pattern 202 are formed is positioned on the substrate 100, the mold substrate 200 is pressed, and then the mold substrate is pressed. When the 200 is removed, the first intaglio pattern 101 and the second intaglio pattern 102 may be formed on the substrate 100.

12 illustrates a substrate engravation method according to another embodiment of the present invention.

Referring to FIG. 12, first, a liquid UV curable resin 300 is coated on a substrate 100 ′ on which a negative pattern is formed by a roller-to-roller method, and then the UV curable resin 300 is cured ( 12a).

Next, the UV curable resin 300 is separated from the substrate 100 ′ (FIG. 12B). Here, in order to easily separate the UV curable resin 300 from the substrate 100 ', before applying the liquid UV curable resin 300 on the substrate 100', the substrate 100 ' A release layer (not shown) may be formed on the first.

Next, the UV curable resin 300 is placed on the substrate 100 (eg, a plastic film), and then the UV curable resin 300 is pressed (FIG. 12C). That is, a stamp process is performed using the UV curable resin 300 as a master.

Next, when the UV cured resin 300 is removed from the substrate 100, a first intaglio pattern 101 and a second intaglio pattern 102 are formed on the substrate 100 (FIG. 12D).

FIG. 13 is a SEM (Scanning Electron Micoscope) photograph showing a state in which a negative pattern is formed on a substrate according to an embodiment of the present invention. FIG.

Referring to FIG. 13, the intaglio pattern may be repeatedly formed on the substrate, and the intaglio pattern may be neatly formed. Here, the depth of the intaglio pattern was formed to be 23.71 μm.

Although the present invention has been described in detail with reference to exemplary embodiments above, those skilled in the art to which the present invention pertains can make various modifications to the above-described embodiments without departing from the scope of the present invention. Will understand.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

100: substrate 101: first intaglio pattern
102: second intaglio pattern 110: gate electrode
120 pad electrode 130 gate insulating film
140: semiconductor layer 150: ohmic contact layer
160: source electrode 165: source / drain electrode layer
170: drain electrode 180: protective film
200 mold substrate 201 first embossed pattern
202: second embossed pattern 220: first rotating roller
230: second rotating roller 250: roller mold
300: UV Curing Resin

Claims

(A) preparing a mold substrate on which a predetermined relief pattern is formed;
(B) combining the mold substrate with a first rotating roller to form a roller mold; And
(C) a first substrate is passed between the roller mold and a second rotating roller formed below the roller mold to correspond to the first rotating roller, thereby forming an intaglio pattern corresponding to the embossed pattern on the first substrate. Comprising the steps of: manufacturing a flexible substrate.

The method of claim 1,
The substrate,
The manufacturing method of the flexible substrate which is a plastic film.

The method of claim 1,
After the step (C),
(D) hardening after applying a liquid UV curable resin on the first substrate on which the intaglio pattern is formed;
(E) separating the cured UV curable resin from the first substrate to form an embossed pattern corresponding to the intaglio pattern on the UV curable resin; And
(F) after placing the UV cured resin having the embossed pattern formed on the second substrate, pressurizing to form a negative pattern corresponding to the embossed pattern on the second substrate, the manufacturing method of the flexible substrate .

The method of claim 3,
Between the steps (C) and (D),
(C-1) A method of manufacturing a flexible substrate, further comprising forming a release layer on the first substrate on which the intaglio pattern is formed.

In the method of manufacturing a thin film transistor having a substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, a drain electrode, and a protective film,
(a) forming a flexible substrate having a predetermined intaglio pattern; And
(b) embedding a gate electrode in the intaglio pattern to form the thin film transistor.

The method of claim 5,
In step (a),
(a-1) preparing a mold substrate having an embossed pattern corresponding to the engraved pattern;
(a-2) combining the mold substrate with a first rotating roller to form a roller mold; And
(a-3) passing the flexible substrate between the roller mold and the second rotating roller formed to correspond to the first rotating roller at the lower portion of the roller mold to form an intaglio pattern corresponding to the embossed pattern on the flexible substrate. Comprising the steps of: manufacturing a thin film transistor.

The method of claim 5,
In step (a),
(a-10) preparing a mold substrate having an embossed pattern corresponding to the engraved pattern;
(a-20) pressing the mold substrate on which the embossed pattern is formed on the flexible substrate and then pressing the mold substrate; And
(a-30) separating the mold substrate from the flexible substrate to form an intaglio pattern corresponding to the embossed pattern on the flexible substrate.

The method of claim 5,
In step (b),
(b-1) screen-printing a conductive paste on the flexible substrate to fill the intaglio pattern with the conductive paste; And
(b-2) removing the conductive paste on the flexible substrate by pushing the upper portion of the flexible substrate to a squeegee.

The method of claim 8,
After the step (b-2),
(b-3) A method of manufacturing a thin film transistor further comprising the step of performing a plating process on the conductive paste filled in the intaglio pattern.

The method of claim 5,
In step (b),
(b-10) forming a conductive layer on the flexible substrate through a sputtering process; And
(b-20) removing the conductive layer formed on the flexible substrate through a polishing process.

The method of claim 5,
In step (b),
(b-100) forming a mask in an area of the flexible substrate except for a portion in which an intaglio pattern is formed;
(b-200) forming a conductive layer on the flexible substrate; And
(b-300) removing the mask formed on the flexible substrate through a lift off process.

In a thin film transistor having a substrate, a gate electrode, a gate insulating film, a semiconductor layer, a source electrode, a drain electrode, and a protective film,
The substrate is formed with an intaglio pattern, the gate electrode is embedded in the intaglio pattern of the substrate, a thin film transistor.

The method of claim 12,
The substrate,
Thin film transistor, which is a plastic film.