KR20110094240A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE: A nonvolatile semiconductor memory device is provided to satisfy high speed and reading accuracy by including a reading control circuit. CONSTITUTION: In a nonvolatile semiconductor memory device, a memory device has two electrodes. The discharge speed of charge between two electrodes is different in response to the logic value of stored information. A cell wiring is connected to one side electrode of a memory device. A sense amplifier(7A) has a sense node(SN). The sense node is connected to the cell wiring. A sense amplifier compares the electric potential of the sense node with reference potential. The sense amplifier reads out information logic value. A read control circuit converts a dynamic sense operation and a static sense operation. A dynamic sense operation precharges cell wiring. The cell wiring is charged and discharged through a dynamic sense operation A static sense operation performs reading while connecting current charge to the sense node.

Description

Nonvolatile Semiconductor Memory Device {NONVOLATILE SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a nonvolatile semiconductor memory device in which the charge discharge rate between two electrodes has a variable cell resistance (Rcell) different in response to a logic value of stored information.

BACKGROUND ART A nonvolatile memory device is known which applies a precharge voltage to a bit line and reads out the difference in its discharge rate.

As a representative of the nonvolatile semiconductor memory device to which such a reading method is applicable, there is (flash) EEPRPM.

On the one hand, in order to replace the FG type (flash) EEPROM, a resistive change type memory device is drawing attention as a nonvolatile memory device having a high speed of data rewriting.

As a resistance change type memory device, a so-called ReRAM is known which corresponds to a storage state in which a resistance change when conductive ions are inputted and outputted to a conductive film in a variable cell resistor (Rcell) (for example, K. Aratani, etc.). A Novel Resistance Memory with High Scalability and Nanosecond Switching ", Technical Digest IEDM 2007, pp. 783-786).

In order to ensure the reliability of the ReRAM rewrite characteristics, the storage characteristics, and the like, and furthermore, for the application to multi-value memories, a method of verifying VeriFi at the time of writing and erasing has been studied as with a general flash memory. For example, see Japanese Patent Laid-Open No. 2002-260377, Japanese Patent Laid-Open No. 2005-510005, and Japanese Patent Laid-Open No. 2004-164766.

Current control at the time of verify reading of a general flash memory verifies another threshold by changing the gate potential of the memory transistor so as to make the read current (sense current) almost constant. The merit of this operation method is that since the operating current is constant, it hardly depends on the threshold that the sense timing, the load of the sense node, etc. verify.

However, ReRAM has different limitations than flash memory.

The variable cell resistor (Rcell) of the ReRAM has only two terminals. That is, like the source terminal and the drain terminal in the flash memory, only two terminals through which current flows and no gate terminal. Here, when a different resistance value is read at the time of verification, the precharge voltage (= VR) applied to the ReRAM at the time of reading is constant, and the resistance (cell resistance) of the variable cell resistance (Rcell) of the ReRAM is set to Rcell. do. The read current then becomes (VR / Rcell). This means that the read current changes when the cell resistance Rcell changes.

In the case of ReRAM, the cell resistance (Rcell) varies depending on the logic value of the stored information. Therefore, if the VeriFi readout is to be performed at high speed for the above reasons, the control of the sense timing is indispensable as follows. do.

Specifically, when the bit line potential (hereinafter referred to as BL potential) is lowered by the discharge by the variable cell resistance Rcell and the readout is verified, the sensed resistance is high. Since the discharge is low, it is necessary to slow the sense timing. On the other hand, when the resistance to be sensed is a low resistance, it is necessary to speed up the sense timing because the discharge of the BL potential at the time of write verification is high speed. If the sense timing is delayed at the time of the writing and verification, the BL charge is lost and the normal sense operation cannot be performed.

In this way, the optimum sense timing differs depending on the logic value of the information to be read, but is not limited to ReRAM. In other words, if the method of reading the magnitude of the cell current by the dynamic discharge reading without performing the gate voltage control of the memory transistor, even in a nonvolatile memory device such as a flash EEPROM, such as a flash-eEPROM, an optimum sense timing misalignment occurs. .

Hereinafter, a method of reading the discharge rate of such precharge charge as it is without being regulated so as to make the discharge current substantially constant (by the transistor gate voltage or the like) is referred to as "dynamic lead". In contrast, a method of reading the discharge current with a substantially constant reading is called "static read".

The dynamic read and the static read are named separately from each other and are not limited to ReRAM, but are known as a reading method of a nonvolatile memory, and either one is usually used. For example, Patent Documents 1 and 2 disclose dynamic reads, and Patent Document 3 discloses static reads for an example of ReRAM.

Since the static sense method of the static read generally senses a static stable voltage, there is a merit that reading can be performed with high accuracy when the read timing is slow.

However, the static sense method cannot operate at a higher speed than the dynamic sense in that the precharge operation before the sense operation is required or the current load itself needs to be set up.

In contrast, the dynamic sense method does not need to be precharged immediately before the sense operation, and is suitable for high-speed reading.

On the other hand, in the dynamic sense system, timing cannot be set because high precision reading is not possible and malfunction margin is narrow. This difficulty in timing setting means that the dynamic lead cannot be applied only when the precision of the resistance change of the variable cell resistance Rcell to be read is high.

As described above, a dynamic lead and a static lead have one piece, and both of them have advantages, and a nonvolatile semiconductor memory having a circuit configuration having a relatively high reading accuracy at a certain high speed is desired.

The present invention provides a nonvolatile semiconductor memory device capable of satisfying high speed and read accuracy.

A nonvolatile semiconductor memory device according to the present invention includes a variable cell resistor (Rcell), a sense amplifier, and a read control circuit.

The variable cell resistance Rcell varies in charge discharge rate between two electrodes in response to a logic value of stored information.

The sense amplifier has a cell wiring connected to one electrode of the variable cell resistor Rcell, and a sense node connected to the cell wiring, and the potential of the sense node is compared with a reference potential to obtain the information. Read the logic value.

The read control circuit is a circuit that can switch between a dynamic sense operation and a static sense operation. In a dynamic sense operation, the cell wiring is precharged and the cell wiring is read by discharging or charging the cell wiring through the storage element. At this time, for example, reading is performed with a voltage difference between the precharge voltage and the voltage of the other electrode of the storage element. In the static sense operation, reading is performed while a current load is connected to the sense node.

According to the above structure, for example, when a very high reading precision is unnecessary, the read control circuit controls the sense amplifier to read the logic value (information) of the variable cell resistor Rcell only by the dynamic sense operation.

On the other hand, when high read accuracy is required, the read control circuit controls the sense amplifier to read the logic value (information) of the variable cell resistor Rcell only by the static sense operation.

In addition, although high reading accuracy is required, when performing high-speed reading, for example, at the start of the read operation, the cell wiring is discharged at high speed with the current load separated in the same manner as in the dynamic sense operation. When fast charging and discharging is performed to some extent, even if the potential of the cell wiring is not sufficient for the lead of the sense amplifier, the current load is connected to the sense node in the intermediate stage similarly to the static sense operation. Then, since the potential of the cell wiring changes stably and rapidly depending on the potential corresponding to the equivalent resistance value of the variable cell resistor Rcell, the cell wiring potential changes to a potential sufficient for the lead of the sense amplifier. By starting the sense amplifier there, relatively high speed and stable sensing are possible.

According to the present invention, it becomes possible to provide a nonvolatile semiconductor memory device capable of satisfying high speed and read accuracy.

1 is an equivalent circuit diagram of a memory cell common to the first to fourth embodiments and modifications.
2 is a device cross-sectional structural view of two adjacent memory cell portions.
3 is a diagram showing a cross section and operation of a variable cell resistor (memory element).
4 is a block diagram of an IC chip (memory device) according to the first to fourth embodiments.
5 is a circuit diagram of an X selector.
6 is a circuit diagram of a Y selector.
Fig. 7 is a circuit diagram of two WL driver units.
8 is a circuit diagram of a CSW driver unit.
9 is a schematic diagram of a column circuit configuration according to the first embodiment.
10 is a timing chart of a dynamic read.
11 is a timing chart of static reads.
12 is a timing chart of a hybrid lead.
13 is a diagram showing four examples of combinations of read modes.
14 is a schematic diagram of a column circuit configuration according to a second embodiment.
15 is a timing chart of a dynamic read.
16 is a timing chart of static reads.
17 is a timing chart of a hybrid lead.
18 is a schematic diagram of a column circuit configuration according to a third embodiment.
19 is a timing chart of a dynamic read.
20 is a timing chart of an electrostatic lead.
21 is a timing chart of a hybrid lead.
22 is a schematic diagram of a column circuit configuration according to a fourth embodiment.
23 is a timing chart of a dynamic read.
24 is a timing chart of static reads.
25 is a timing chart of a hybrid lead.

An embodiment of the present invention will be described with reference to the drawings in the following order, taking ReRAM as an example.

1. Opening

2. First Embodiment: Single-ended type sense amplifier.

3. Second Embodiment: In a single-ended sense amplifier, the cell current direction is reversed.

4. Third embodiment: current mirror type sense amplifier.

5. Fourth Embodiment: The cell current direction is reversed in the current mirror type sense amplifier.

6. Modifications

<1. Open>

The nonvolatile semiconductor memory device to which the present invention is applied has a "reading control circuit" including a configuration capable of controlling the connection and disconnection (disconnection) of the current load to the sense node of the sense amplifier.

This read control circuit is a circuit which can switch a dynamic sense operation and a static sense operation, and also includes the structure for precharge.

In this case, the dynamic sense operation refers to applying a precharge voltage to a cell wiring (for example, a bit line) and discharging or charging the cell wiring (for example, a bit line) through a memory element (for example, a variable cell resistor (Rcell)). This is the action for the sense. More specifically, in the dynamic operation, for example, the sense current flows through the variable cell resistor Rcell with the voltage difference between the cell wiring and the variable cell resistor Rcell and the opposite electrode (or wiring). Since there is no charge source from outside other than the precharge charge on the sense node side, the cell wiring potential drops or rises rapidly. Whether the cell wiring potential drops or rises depends on the polarity (direction of the voltage) of the precharge voltage and the voltage applied to the electrode (or wiring) on the opposite side.

The static sense operation refers to an operation for sense including charge / discharge operation of cell wiring in a state where a current load that supplies or discharges a substantially constant current to the sense node is connected. When the current flowing through the cell wiring is regulated in a constant or almost constant manner, the rate of change of the potential is slowed by that amount, but the change of the potential has a speed proportional to or almost proportional to the resistance of the variable cell resistor Rcell. Therefore, stable operation is possible. On the premise of this stable operation, it is easy to control the timing of the sense amplifier, and high precision reading is possible.

On the other hand, in the dynamic sense operation, since the charging and discharging is fast, the high speed is high, but the threshold setting of the sense amplifier and the control of the start timing are relatively difficult. Therefore, for example, in the case of the resistance change memory, it is not preferable to apply the dynamic sense operation unless any specific condition is arranged, such as when the resistance value is relatively large and the resistance change in response to the memory information is also large.

When the read control circuit according to the embodiment of the present invention knows to some extent whether the read target is low resistance or high resistance, for example, the read control circuit performs two sense operations in response to the information, for example, at the time of verifiable reading. Enable the switch. As the information, a read signal, an erase signal, or the like which commands an operation immediately before the verify operation (write or erase operation) can be used.

On the other hand, in normal reading, it is not known beforehand whether the object to be read is low or high resistance. However, it is determined whether the dynamic sense operation is suitable or the static sense operation is appropriate depending on the storage material, structure, reliability data, and the like of the variable cell resistor Rcell.

On the other hand, in another form, the hybrid sense operation which uses a dynamic sense operation and a static sense operation together is also possible. The switching control and the like will be described later. However, since it has the advantages (high speed and high precision) of the two sense operations, the hybrid system can be used in either write verification, read erasure verification, or normal reading. Is applicable.

Hereinafter, the embodiment of the present invention will be described in more detail by taking an example in which the three sense operations can be switched and using a ReRAM as an example of the nonvolatile memory.

<2. First embodiment>

Memory Cell Configuration

1A and 1B show an equivalent circuit diagram of a memory cell common to the embodiment of the present invention. In addition, although FIG. 1A shows the write current Iw and FIG. 1B shows the direction with respect to the erase current Ie, the memory cell structure itself is common in both figures.

The memory cell MC shown in FIG. 1 has one memory cell resistor Rcell as " variable cell resistor Rcell " and one access transistor AT.

One end of the memory cell resistor Rcell is connected to the plate line PL, the other end is connected to the source of the access transistor AT, the drain of the access transistor AT is connected to the bit line BL, and the gate is "accessed." Lines WL, respectively.

In addition, although the bit line BL and the plate line PL are orthogonal in FIG. 1, you may arrange | position the bit line BL and the plate line PL in parallel.

2 shows a device structure of a portion corresponding to two adjacent memory cells MC. 2 is a schematic sectional view and does not have an oblique line. In addition, the blank portion of FIG. 2, which is not particularly mentioned, is filled with an insulating film or constitutes (part of) another portion.

In the memory cell MC shown in FIG. 2, the access transistor AT is formed in the semiconductor substrate 100.

More specifically, two impurity regions formed of the source S and the drain D of the access transistor AT are formed in the semiconductor substrate 100, and the polysilicon is interposed between the gate regions on the substrate region therebetween. The gate electrode which consists of etc. is formed. In this case, the gate electrode constitutes a word line WL1 or WL2.

The drain D is shared by the two memory cells MC and is connected to the bit line BL formed by the first wiring layer 1M.

On the source S, the plug 104 and the landing pad 105 (formed from the wiring layer) are repeatedly stacked, and a memory cell resistor Rcell is formed thereon. The layer of the memory cell resistor Rcell is arbitrarily formed, but the memory cell resistor Rcell is formed in the fourth to fifth layers.

The memory cell resistor Rcell has a film structure (laminated body) having an insulator film 102 and a conductor film 103 between the lower electrode 101 and the upper electrode made of the plate line PL. have.

As a material of the insulating film 102, for example, and the like can be _{SiN, SiO 2, Gd 2 O} 3.

As a material of the conductor film 103, the metal film containing one or more metal elements selected from Cu, Ag, Zr, an alloy film (for example, CuTe alloy film), a metal compound film, etc. are mentioned, for example. . Moreover, as long as it has a property which is easy to ionize, you may use metal elements other than Cu, Ag, and Zr. Moreover, it is preferable that the element combined with at least 1 of Cu, Ag, Zr is at least 1 element of S, Se, and Te. The conductor film 103 is formed as an "ion supply layer".

3 shows an example of the current direction and the applied voltage value in an enlarged view of the memory cell resistance Rcell.

3 illustrates an example in which the insulator film 102 is formed of SiO 2 and the conductor film 103 is formed of an alloy compound (Cu-Tebased) of CuTe alloy base.

In FIG. 3A, a voltage having the insulator film 102 side as the negative electrode side and the conductor film 103 side as the positive electrode side is applied to the lower electrode 101 and the upper electrode (plate line PL). For example, the bit line BL is grounded to 0 [V], and +3 [V] is applied to the plate line PL, for example.

Then, Cu, Ag, and Zr contained in the conductor film 103 have the property of being ionized and attracted to the negative electrode side. Conductive ions of these metals are implanted into the insulator film 102. Therefore, the insulation property of the insulator film 102 falls, and it becomes electroconductive with the fall. As a result, the write current Iw in the direction shown in Fig. 3A flows. This operation is called recording (operation) or set (operation).

On the contrary, in FIG. 3B, a voltage having the insulator film 102 side as the positive electrode side and the conductor film 103 side as the negative electrode side is applied to the lower electrode 101 and the upper electrode (plate line PL). do. For example, the plate line PL is grounded to 0 [V], and +1.7 [V] is applied to the bit line BL, for example.

Then, the conductive ions injected into the insulator film 102 return to the conductor film 103 and are reset to a state where the resistance value before writing is high. This operation is called erasure (operation) or reset (operation). In reset, the erase current Ie in the direction shown in FIG. 3B flows.

In addition, hereinafter, a set refers to "fully injecting conductive ions into an insulator film", and a reset refers to "full drawing of conductive ions from an insulator film".

On the other hand, which state (set or reset) is set as the data recording state and the erase state is arbitrarily defined.

In the following description, the case where the insulation property of the insulator film 102 falls and the resistance value of the whole memory cell resistance Rcell falls to a sufficient level corresponds to "write" (set) of data. Conversely, the case where the insulation property of the insulator film 102 returns to its original initial state and the resistance value of the entire memory cell resistance Rcell rises to a sufficient level corresponds to "erasing" (reset) of the data.

Here, the arrow of the circuit symbol of the memory cell resistor Rcell shown in FIG. 1 is usually in the same direction as the current at the time of setting (here, writing).

By repeating the above-described set and reset, a binary memory which reversibly changes the resistance value of the memory cell resistor Rcell between a high resistance state and a low resistance state is realized. In addition, the memory cell resistor Rcell functions as a nonvolatile memory because data is retained even when the application of the voltage is stopped.

In addition, since the resistance value of the insulator film 102 changes with the amount of metal ions in the insulator film 102 at the time of setting, the "storage layer" in which data is stored and stored is stored in the insulator film 102. "Can be considered.

A memory cell is constructed using this memory cell resistor Rcell, and a large number of memory cells are provided to form a memory cell array of a resistance-variable memory. A resistance change type memory is comprised of this memory cell array and its drive circuit (peripheral circuit).

[IC chip configuration]

4 shows a block diagram of the IC chip.

The illustrated semiconductor memory device includes (M + 1) memory cells MC shown in Figs. 1 to 3 in a matrix (N + 1) in a row (row) direction and (N + 1) in a column (column) direction. And the memory cell array 1 arranged. The semiconductor memory device integrates the memory cell array 1 and its peripheral circuits on the same semiconductor chip. Here, "N" and "M" are relatively large natural numbers, the specific values of which are set arbitrarily.

In the memory cell array 1, (N + 1) word lines WL <0 commonly connected between gates of the access transistor AT in the (M + 1) memory cells MC arranged in the row direction. > To WL <N>) are arranged at predetermined intervals in the column direction. Further, in the (N + 1) memory cells MC arranged in the column direction, the (M + 1) bit lines BL <0> to BL <M> commonly connected between drains of the access transistor AT, respectively. ) Are arranged at predetermined intervals in the row direction.

(N + 1) plate lines PL for common connection of nodes opposite to the access transistor AT of the memory cell resistor Rcell in the row direction are arranged at predetermined intervals in the column direction.

Each of the (N + 1) plate lines PL is connected to a common line, and the common line is drawn out of the memory cell array 1.

The plate line PL may be arranged long in the column direction, and the number thereof may be (M + 1).

As shown in Fig. 4, the peripheral circuit includes an X (address) decoder (X Decoder) 2, a pre-decoder (Pre DEC) 3 that also serves as a Y (address) decoder, and a WL driver (WL_DRV) (4). , BLI switch 5, and CSW driver (CSW_DRV) 6. The peripheral circuit includes a sense amplifier 7 for each column and an I / O buffer 9. The peripheral circuit includes a write / erase driver (W / E DRV) 10, a control circuit (CONT.) 11, a plate driver (PL DRV) 12, and a control voltage generation circuit (P_CIR) 16. do.

In addition, although the sense amplifier 7 is not like that in FIG. 4, it is provided for every memory cell row. In addition, in FIG. 4, the generation control circuit etc. of a clock signal are abbreviate | omitted.

The X decoder 2 is configured based on an X selector (not shown) as a basic unit. The X decoder 2 is a circuit that decodes the X address signal input from the predecoder 3 and sends the selected X select signal X_SEL to the WL driver 4 based on the result of the decoding. The detail of X selector is mentioned later.

The predecoder 3 separates the input address signal Address into an X address signal and a Y address signal. The predecoder 3 sends the X address signal X_SEL to the X decoder 2, and decodes the Y address signal by the Y decoder.

The Y decode section of the predecoder 3 is configured with the Y selector (not shown) as a basic unit. The predecoder 3 is a circuit that decodes the input Y address signal and sends the selected Y select signal Y_SEL to the CSW driver 6 based on the result of the decoding. The detail of the Y selector is mentioned later.

The WL driver 4 includes (N + 1) WL driver units (not shown) for each word line WL. One of the (N + 1) word lines WL <0> to WL <N> is connected to the output of each WL driver unit. In response to the X select signal X_SEL input from the X decoder 2, one of the WL driver units is selected. The WL driver unit is a circuit which, when selected, applies a predetermined voltage to the word line WL connected to its output. Details of the WL driver unit will be described later.

The CSW driver 6 is configured based on the CSW driver unit. The CSW driver 6 is a circuit for controlling the BLI switch 5 and is a circuit for driving the column select lines CSL <0> to CSL <M>. In addition, the detail of a CSW driver unit is mentioned later.

The BLI switch 5 is, for example, an NMOS transistor (which may be a PMOS transistor) alone or a set of switches 51 constituted by a transfer gate shown in FIG. 4. Here, each switch 51 is connected for every bit line BL, and there are (M + 1) pieces in total.

Hereinafter, each switch which comprises the BLI switch 5 is called a transfer gate.

The write / erase driver 10 is connected to the I / O buffer 9, inputs external data from the I / O buffer 9, and can change the save data of the sense amplifier 7 in response to the input data. Control.

In the sense amplifier 7, the output node is connected to the I / O buffer 9. The sense amplifier 7 compares the potential change of the bit line BL input through the switch 51 in the on state with the reference potential.

The control circuit 11 inputs the write enable signal WRT, the erase enable signal ERS, and the data read signal RD, and operates on the basis of these three signals.

The control circuit 11 has the following five functions.

(1) A function of word line control for giving the WL select enable signal WLE to each WL driver unit in the WL driver 4.

(2) A function in which the CSW driver 6 is controlled (or directly) via the predecoder 3, whereby the switch 51 is individually turned on or off.

(3) A function of controlling the supply of an operating voltage by giving a write enable signal WRT and an erase enable signal ERS to the write / erase driver 10 during recording or erasing.

(4) A function of controlling the supply of an operating voltage by giving a write enable signal WRT and an erase enable signal ERS to the plate driver 12 as necessary, at the time of writing or erasing.

(5) A function of controlling the control voltage generating circuit 16 during a read or a verify read operation to perform an output such as a clamp voltage Vclamp.

In addition, only the code | symbol is shown in FIG. 4 for the various control signals output by the control circuit 11, The detail of a level change is mentioned later.

[Control system circuit]

Next, X selector which is the basic configuration of the X decoder 2 and Y selector which is the basic configuration of the Y decoder function of the predecoder 3 will be described. Subsequently, the WL driver unit which is the basic configuration of the WL driver 4 will be described.

5 shows a circuit example of the X selector 20.

The X selector 20 shown in FIG. 5 includes four inverters INV0 to INV3 in the first stage, four NAND circuits NAND0 to NAND3 in the middle, and four inverters INV4 to INV7 connected to the rear stage. Consists of

The X selector 20 inputs the X address bits X0 and X1, and activates one of the X select signals X_SEL0 to X_SEL3 (e.g., set to a high level) in response to the decoding result. to be.

Although FIG. 5 is an example of 2-bit decode, the X decoder 2 expands or multi-stages the configuration of FIG. 5 in response to the number of bits of the input X address signal, so that the input corresponds to other than 2 bits. It is possible to realize.

6 shows a circuit example of the Y selector 30.

The illustrated Y selector 30 is composed of four inverters INV8 to INV11 of the first stage, four NAND circuits NAND4 to NAND7 of the interruption, and four other inverters INV12 to INV15 connected to the rear stage. have.

The Y selector 30 inputs the Y address bits Y0 and Y1, and activates one of the Y select signals Y_SEL0 to Y_SEL3 (e.g., set to a high level) in response to the decoding result. to be.

Although FIG. 6 is an example of 2-bit decode, the predecoder 3 expands or multi-stages the configuration of FIG. 6 in response to the number of bits of the input Y address signal, thereby enabling the input to be coped with other than 2 bits. do.

FIG. 7 is a circuit diagram showing two portions of the WL driver unit 4A.

The illustrated WL driver unit 4A includes only the cell number N + 1 in the column direction in the WL driver 4.

The (N + 1) WL driver units 4A operate by one X select signal X_SEL0 or X_SEL1 selected (activated) by the X selector 20 or the like shown in FIG. The WL driver unit 4A activates one word line WL <0> or WL <1> in response to the X select signal X_SEL0 or X_SEL1.

The WL driver unit 4A shown in FIG. 7 is composed of a NAND circuit NAND8 and an inverter INV16.

The WL select enable signal WLE is input to one input of the NAND circuit NAND8, the X select signal X_SEL0 or X_SEL1 is input to the other input, and the output of the NAND circuit NAND8 is output of the inverter INV16. It is connected to the input. The word line WL <0> or WL <1> connected to the output of the inverter INV16 is activated or deactivated.

The WL select enable signal WLE shown in FIG. 7 is generated in the control circuit 11 in FIG. 4 and given to the row decoder 4.

8 shows a circuit example of two of the CSL driver units 6A.

The illustrated CSL driver unit 6A includes a NAND circuit NAND12 and an inverter INV21 connected to the output thereof.

The BLI enable signal BLIE is input to one input of the NAND circuit NAND12, and one Y select signal Y_SEL0 or Y_SEL1 selected (activated) by the Y selector 30 shown in FIG. 6 to the other input. ) Is entered. When both the Y select signal Y_SEL0 or Y_SEL1 and the BLI enable signal BLIE are active (high level), the output of the NAND circuit NAND12 becomes low level. Therefore, the potential of the column select line CSL <0> or CSL <1> connected to the output of the inverter INV21 transitions to the active level (high level in this example).

The potential of the column select line CSL <0> or CSL <1> is input to the gate of the corresponding switch 51 as shown in FIG.

[Configuration for switching between column circuit and constant current load]

9, the schematic of the column circuit structure which concerns on this embodiment is shown.

The configuration shown in FIG. 9 is a mode in which one memory cell MC (a series connection body of an access transistor AT and a memory cell resistor Rcell) is connected to one bit line BL as "cell wiring". Indicates. The gate of the access transistor AT of the memory cell MC is connected to the word line WL, and the source or drain opposite to the variable cell resistor Rcell of the access transistor AT is connected to the bit line BL. have. Further, the one side thereof is also connected to the source SL (here indicated by a circuit symbol of GND). In Fig. 9, the load capacitance of the bit line BL is indicated by the equivalent capacitance of the symbol "Cbl".

A configuration indicated by reference numeral 7A is a single-ended sense amplifier 7A for each bit line constituting the sense amplifier 7 of FIG.

The non-inverting input (+) of the sense amplifier 7A is connected to the sense node SN. A constant reference potential Vref is input to the inverting input "-" of the sense amplifier 7A from the control circuit 11 or the control voltage generation circuit 16 of FIG. 4. The potential of the sense node SN is shown by the sense node potential V0 in FIG.

To the sense node SN, a precharge transistor (PMOS) 71 for controlling the application of the read application voltage VR is connected. Although not shown in FIG. 4, the precharge transistor 71 is gated by a low active precharge signal / PRE supplied from the control circuit 11. The precharge transistor 71 may be connected to the bit line BL side. The read application voltage VR is set to a size such that no read disturb occurs in memory cells other than the memory cells to be read connected to the bit line BL.

The load disconnect switch 52 is connected between the bit line BL and the sense node SN (non-inverting input "+") of the sense amplifier 7A. Although not shown in FIG. 4, the load disconnect switch 52 is provided for each bit line between the switch 51 and the bit line BL. The load disconnect switch 52 serves to isolate the bit line BL from the load on the sense node side when controlling the bit line BL (cell wiring) to a constant voltage and amplifying the potential of the sense node SN. have. Although the load disconnection switch 52 is an NMOS transistor structure in the example shown in figure, you may have a PMOS transistor structure or the transfer gate structure which connected NMOS transistor and PMOS transistor in parallel.

In more detail, the load disconnect switch 52 operates as follows.

At the time of reading data, the clamp voltage Vclamp is applied from the control voltage generation circuit 16 of FIG. 4 to the gate of the load disconnect switch 52 (NMOS). When charging and discharging the variable cell resistor Rcell of the memory cell MC, current flows through the load disconnect switch 52. In the NMOS configuration, it is assumed that a discharge current flows from the sense node SN to the variable cell resistor Rcell. In this case, the source potential of the load disconnect switch 52 is clamp-controlled to the voltage (to a constant potential) lowered from the clamp voltage Vclamp by the voltage Vgs between the gate sources. Since the transistor is held at the turn-off point in the state where the clamp voltage is stable, the load on the sense node SN side is separated from the bit line BL.

In the column circuit of the present embodiment, the constant current load unit IRef is connected to the sense node SN via the first control switch 72. This is a configuration for switching control of the current load with respect to the sense node SN, and becomes part of the "reading control circuit" of the present invention. Since the current direction of the constant current load portion IRef is a direction for supplying the electrostatic charge (current) to the sense node SN here, the first control switch 72 has a PMOS transistor configuration.

In addition to this configuration, the read control circuit includes the control circuit 11 and the control voltage generation circuit 16 in FIG. 4. In addition, the X decoder 2, the pre decoder 3, the row decoder 4, the BLI switch 5 and the CSW driver 6 which control the memory cell array at the time of reading, and also the I / O buffer ( 9) may be arbitrarily included in the concept of the read control circuit.

[Overview of reading operation]

The read operation under the premise of FIG. 9 is as follows.

The single-ended sense amplifier 7A shown in FIG. 9 compares the sense node SN potential Vo with the reference potential Vref and performs logical determination (H / L determination) of stored information. In addition, by clamping the BL potential to the aforementioned (Vclamp-Vgs) with the NMOS source follower, the disturbance at the time of reading is avoided.

As described above, there are two kinds of readings: a dynamic sense operation and a static sense operation using the constant current load unit IRef shown in FIG. 9 as a current load.

Here, the period during which the sense amplifier reads the storage logic value from one cell and the operation of the plurality of sense amplifiers in parallel is called a read cycle. Performing the dynamic sense operation in one read cycle is referred to as "dynamic lead", and performing the static sense operation in one read cycle is called "static read". In the present embodiment, a dynamic sense operation is first performed in one read cycle, and the static sense operation is performed from the middle of the cycle.

The read control circuit according to the present embodiment can arbitrarily switch the modes of these three leads. In FIG. 4, these three read modes are executed by turning on or off the first control switch 72 shown in FIG. 9 by the control voltage generation circuit 16 under the control of FIG. 11.

[Dynamic Lead]

10A to 10C2 show timing charts of the dynamic reads.

The precharge signal / PRE shown in FIG. 10A is a pulse signal that becomes an active low for a predetermined period of time T1 to T2. In the dynamic read, since the first active load control signal / DC to the first control switch 72 of FIG. 9 is always set to "H", the first control switch 72 is turned on. Therefore, the current load is therefore not connected.

When precharging occurs at time T1, as illustrated in FIGS. 10C and 10C, the sense node potential Vo is precharged to the read BL voltage VR.

When the precharge ends at the time T2, the sense node is floated and cell discharge by the jersey voltage is performed. Therefore, the sense node potential Vo decreases rapidly.

In addition, Fig. 10 (C1) shows the change of sense node potential when the variable cell resistor (Rcell) is in the low resistance state, and Fig. 10 (C2) is the variable cell resistance (Rcell) in the high resistance state. In addition, the two discharge lines show the case where the resistance value of the variable resistance cell exceeds the target value and should be determined that the verification is successful (OK), and when the writing or erasing is insufficient, it is determined that the verification failure (NG). do. For example, in the case of low resistance, when the target resistance value is 10 [kΩ], the sense node potential of 9 [kΩ] having sufficient low resistance is set to Vo (RL), and the sense node of 11 [kΩ] having insufficient resistance is insufficient. The potential is represented by Vo (RH).

As described above, in the resistance change type memory, the discharge speed is influenced by the magnitude of the cell resistance value, and the smaller the cell resistance value, the faster the discharge is performed. Discharge proceeds with time, and finally, the potential change progresses until the sense node potential Vo becomes zero, but the slope varies greatly depending on the magnitude of the resistance value.

In the case of the dynamic lead, the discharge rate is slow in the high resistance reading, but the loss of the read charge is fast in the low resistance reading. Therefore, since it is necessary to control the reference potential Vref between sufficient discharge and insufficient discharge lines, setting of the sense timing is relatively difficult.

The case where it is a static lead by the same drawing to FIG. 11 (A)-(C2) is shown.

In the static read, the first load control signal / DC shown in FIG. 11B is controlled to be "L" active at time T2. Therefore, the discharge after time T2 becomes constant current drive. In the constant current drive, the potential change converges on the current through which the constant current load unit IRef flows and a stable point determined by the load resistance. Here, the load resistance includes the wiring resistance of the bit line and the on resistance of the switch transistor. The variable cell resistance (Rcell) dominates most of the size. Therefore, the sense node potential converges at a stable point corresponding to the size of the variable cell resistor Rcell.

In the low resistance shown in FIG. 11C, lower than the reference potential Vref is an OK cell having sufficient resistance (writing or erasing), and not lowering even after some time is insufficient. One NG cell. Each convergence potential becomes unique in response to each cell resistance value, and a state where a potential difference (window width) between the OK cell and the NG cell is large is obtained when time is taken. Therefore, when the sense amplifier is started, stable and reliable reading operation is possible.

On the other hand, at the high resistance shown in Fig. 11C2, the cell having a stable point higher than the reference potential Vref is an OK cell, and the cell below it is an NG cell. In the case of high resistance, it takes longer than in the case of low resistance until the judgment is made, but stable and reliable reading is possible after time passes.

However, there is a drawback that the static read has a slower read speed than the dynamic read.

10 and 11 are examples. For example, when the variable resistance element material changes, the speed of the discharge curve and the behavior of the stable point also change in various ways.

Therefore, if some resistive materials can be read by dynamic leads, accurate readings may not be possible without static leads.

Next, a hybrid lead which is a lead method peculiar to this embodiment will be described.

[Hybrid lead]

In FIG. 12, the case where it is a static lead by the same drawing is shown. The hybrid lead combines both the high speed of the dynamic lead and the stability of the static lead.

More specifically, the constant current load unit IRef can be switched to the PMOS switch (first control switch 72), and this is switched in response to the sense timing. At this time, the first or last sense is switched to the dynamic sense method (no IRef connection), and at least the latter is switched to the static sense method (IRef connection). Since the early stage of the sense is a dynamic read, high-speed reading is possible, and the late stage of the sense is a static read, and thus stable operation that does not require precision in sense timing is possible.

As shown in FIG. 12B, the timing of the transition of the first load control signal / DC to the active level "L" is different from the case of the static read in FIG. 11B. In the hybrid lead, the first control switch 72 of FIG. 4 is turned on at a time T3 delayed from the time T2, and switching from the active lead to the static lead is performed. Therefore, the discharge of the sense node, which has been rapidly being discharged by the active lead, is corrected since the current load is connected from the time T3. That is, in the low resistance of Fig. 12C1, since the NG cell having insufficient low resistance is excessive discharge, it changes relatively rapidly at the stable point due to rapid charging by the load current. This contributes to rapid charging even when the constant current load portion IRef is close to the sense node SN. On the other hand, the OK cell with sufficient low resistance has a stable point lower than the reference potential Vref, and therefore shifts to the stable point as it is.

This operation differs only in the inclination of the dynamic discharge line and is basically the same even at high resistance.

As described above, in the hybrid lead, since the dynamic discharge is first performed, the sense node potential decreases to a low level in a short time, and when discharge is started by the current load, the stable operation is performed in a relatively short time due to the reaction of the excessive decrease. You can. The large window width, and when opened to some extent, enables the sense operation by the sense amplifier, which is an advantage of the static lead, enabling high precision reading.

In addition, being able to read with high precision in this embodiment brings the advantage that the logic can be precisely determined even if the reference voltage is controlled at a fine pitch, for example, during the verification scan.

In Fig. 11, even in the time at the right end of the drawing, the NG cell at high resistance still does not sufficiently fall below the reference potential Vref, which is too fast for the start of the sensor amplifier. On the other hand, in Fig. 12, since the NG cell and the OK cell are also shifted to the prescribed area (the area to be originally processed) with reference to the reference potential Vref slightly later than the time T3, the sense is sensed at that time. The amplifier can be started. Therefore, in the hybrid lead, it is possible to shorten the time by several times than the static lead, and the stable reading similar to the static lead is possible.

The timing of the time T3 can be adjusted arbitrarily.

[Combination example of lead mode]

In the diagram of FIG. 13, four examples of the combination of the dynamic read, the static read and the hybrid read are shown for the write verification read, read verification read, and normal read.

The information of this combination is selected by the control circuit 11 using the one stored internally or by an external control means, and the control circuit 11 controls the control voltage generating circuit 16 and the like. , Run this

As in these four examples, in the write verification process, the static read S or the hybrid read H is executed, but the dynamic read D cannot be used because the discharge is too rapid.

In contrast, in erase erase read, it is not practical because the static read takes too much time.

Normal reading can be arbitrarily selected by the method which is easy to read according to the variable cell resistance material mentioned above. In this example, the static lead S or the hybrid H is preferable in view of stability, but the dynamic lead D is not excluded.

<3. Second Embodiment>

After this embodiment, the deformation | transformation of circuit structures, such as a sense amplifier, is shown. Therefore, the circuit and block structure other than the whole structure and a deformation | transformation, and also the basic of operation are common to 1st Embodiment. Therefore, the following description will focus on the change points.

14, the schematic of the column circuit structure which concerns on 2nd Embodiment is shown. 15 to 17 show control waveforms and timings of the dynamic lead, the static lead and the hybrid lead.

The pulses that correspond to the inverted conductivity type of the main transistors are also determined (Figs. 15A, 15B, 16A, 16B, and 17). A) and FIG. 17B). In addition, an inverted signal (a high active signal) in which the first load control signal / DC and the precharge signal / PRE are also " / " is provided from the control circuit 11 or the control voltage generation circuit 16.

Therefore, the relationship between discharge and charge is reversed, and when this is cooked, the temporal transition of discharge (or charge) becomes substantially the same in the first and second embodiments (but the waveform is inverted).

<4. Third embodiment>

18, the schematic of the column circuit structure which concerns on 3rd Embodiment is shown. 19 to 21 show control waveforms and timings of the dynamic lead, the static lead, and the hybrid lead.

The circuit configuration shown in FIG. 18 is different from that in FIG. 9 in that the voltage applied to the plate line PL connected to the variable cell resistor Rcell becomes the read BL voltage VR (> 0) and conversely precharges. The voltage line connected to the transistor 71 is a GND voltage supply line. In other words, the cell current direction is reversed. In addition, the precharge transistor 71 and the first control switch 72 are changed from the PMOS transistor to the NMOS transistor, and the load disconnection switch 52 is changed from the NMOS transistor to the PMOS transistor. The current source direction (current flowing direction) connected to the first control switch 72 is also reversed.

18 and 9 have a common configuration on the memory cell side other than that, and the basic operation is also the same.

The load disconnect switch 52, the precharge transistor 71 and the first control switch 72 are connected to the bit line BL to which the memory cell MC to be read is connected. Same as the embodiment.

On the other hand, the sense amplifier 7B in this embodiment is a mirror current differential type. In the single-ended type of Fig. 9, the inverting input (-) of the sense amplifier 7A is given from the control voltage generation circuit 16 or the like, but in this embodiment, it is generated internally in the memory cell array 1.

Specifically, a reference column in contrast to a normal memory column of an operation target is prepared. Since the reference column has a configuration similar to that of the memory cell MC, the description thereof will be omitted. Using the reference cell increases the circuit scale, but as shown in FIGS. 19 to 21, the timing design is easy because the reference potential Vref changes in accordance with the change of the sense node potential Vo.

<5. Fourth embodiment>

22, the schematic of the column circuit structure which concerns on 5th Embodiment is shown. 23 to 25 show control waveforms and timings of the dynamic lead, the static lead, and the hybrid lead.

As in the case of the single-ended type, the cell current direction is reversed to that in Fig. 18, thereby inverting the method of voltage supply and the conductivity type of the transistor.

As in the third embodiment, a reference column in contrast to the normal memory column to be operated is provided. Since the reference column has a configuration similar to that of the memory cell MC, the description thereof will be omitted.

Using the reference cell increases the circuit scale, but as shown in FIGS. 23 to 25, the timing design is easy because the reference potential Vref changes in accordance with the change of the sense node potential Vo.

<6. Modifications>

In the above four embodiments, ReRAM is taken as an example, but the present invention can be widely applied to a resistance change type memory such as a phase change memory other than ReRAM.

Also in other nonvolatile memories such as flash memories, there is a case where a read operation without word line control, that is, a constant current, is possible. For example, in the MCL-NOR type, there is a report of such an operation. If such an operation is performed, there is a significant difference in sense timing depending on the logic value of the information to be read or the type (mode) of the read. exist.

Therefore, the present invention is preferably applied to a resistance change type memory having a wide dynamic range of read current, but the description of the above embodiment does not mean that the application to other nonvolatile memories is excluded.

In the first to fourth embodiments and the first modification example described above, it is possible to provide a nonvolatile semiconductor memory device capable of satisfying high speed and read accuracy in a so-called dynamic read operation.

This invention is a priority claim application of Japanese Patent Application JP2010-030528 (2010.02.15).

The present invention may be variously modified, combined, replaced, etc. as needed by those skilled in the art within the scope of the appended claims.

1: memory cell array
4: low decoder
5: BLI switch
6: CSW driver
7, 7A, 7B: sense amplifier
9: I / O buffer
10: recording and erasing driver
11: control circuit
12: plate driver
16: control voltage generating circuit
20: X selector
30: Y selector
40: low decoder unit
51: switch
52: load disconnect switch
60: CSW driver
71: precharge transistor
72: the first control switch
101: lower electrode
102: insulator film
103: conductor film
Rcell: Variable Cell Resistance
MC: memory cell
RC: reference cell
BL: Bit line
WL: word line
PL: Plate Wire
AT: access transistor

Claims (11)

The charge discharge rate between the two electrodes is different from the other memory elements in response to the logic value of the stored information;
A cell wiring connected to one electrode of the memory element,
A sense amplifier having a sense node connected to the cell wiring and reading a logic value of the information by comparing the potential of the sense node with a reference potential;
It is possible to switch between the dynamic sense operation of performing reading by precharging the cell wiring and discharging or charging the cell wiring through the memory element, and the static sense operation of reading while the current load is connected to the sense node. A nonvolatile semiconductor memory device having a read control circuit. The method of claim 1,
The read control circuit may include a dynamic read that performs the dynamic sense operation in one read cycle, a static read that performs the static sense operation in one read cycle, and the static sense operation after the dynamic sense operation in one read cycle. It is possible to arbitrarily select the hybrid lead to switch, The nonvolatile semiconductor memory device characterized by the above-mentioned. The method of claim 2,
The combination of the dynamic read, the static read and the hybrid read is preset for the three read modes of the write verifi read after the write operation of the information, the erase verifi read after the erase operation, and the normal read. And the read control circuit controls the read operation in the set combination. The method of claim 1,
The read control circuit,
A precharge unit connected to the sense node;
A constant current load unit connected to the sense node through a first control switch,
And a control signal generator for generating a control signal for controlling said first control switch. The method of claim 4, wherein
And the sense amplifier is a single-ended sense amplifier which amplifies the potential of the sense node by comparing the potential of the sense node given to one input with a reference potential given to the other input. The method of claim 1,
The read control circuit,
A reference line,
A reference memory element connected to the reference line and having a resistance value equivalent to that of the memory element,
A diode-connected transistor connected to a reference node of the reference line via a second control switch and generating the reference potential at a gate;
A reference constant current load portion connected to the reference node,
It has a control signal generator for generating a control signal for controlling the first control switch and the second control switch,
The sense amplifier is provided with a mirror current load transistor connected to the sense node through a first control switch and whose gate is connected to the gate of the diode connection transistor, through which a mirror current of reference line current flows, and one input of the sense A non-volatile semiconductor memory device, characterized in that it is a current mirror type differential sense amplifier connected to a node and amplifying a sense node potential with respect to the reference potential given to the other input. The method of claim 1,
A load disconnecting switch is connected between the cell wiring and the sense node to control the cell wiring to a constant voltage and to amplify the potential of the sense node, and to disconnect the cell wiring from the load on the sense node side. Volatile semiconductor memory device. The method of claim 7, wherein
The load disconnect switch is formed of an NMOS transistor, a PMOS transistor, or a transfer gate circuit in which an NMOS transistor and a PMOS transistor are connected in parallel. The method of claim 7, wherein
The load disconnect switch is an NMOS transistor, and by applying a clamp voltage to the gate of the NMOS transistor from the read control circuit, the cell wiring is lowered from the clamp voltage by a voltage between the gate and the source of the NMOS transistor. And clamping the load and separating the sense node and the cell wiring in which the voltage amplitude is generated by a sense operation. The method of claim 1,
And the memory element is a resistance change type memory element whose logic value of write information differs depending on an applied voltage direction. The method of claim 6,
A nonvolatile semiconductor memory device characterized in that the memory element and the reference memory element are resistance change type memory elements having different logic values of write information in an applied voltage direction.

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