KR20110079439A - 3d image display device - Google Patents

Abstract

PURPOSE: A 3D image display device is provided to prevent a 3D cross talk by increasing the response speed of a liquid crystal and improve a MPRT(Motion Picture Response Time) without brightness lowering in a video. CONSTITUTION: A liquid crystal display panel displays a unit frame period as a cycle on a left eye image and a right eye image by turns. A data driving circuit drives data lines of a LCD panel. A gate driving circuit drives the gate lines of the LCD panel. A timing controller partitions a unit frame period into a subframe periods of N. The timing controller supplies unit frame data for subframe periods of N to data driving circuit repetition. The light source generates the light researched to the LCD panel. The light source control circuit generates a back light control signal for controlling lighting timing of light sources. A light source driving circuit altogether lights light sources in response to the back light control signal among the subframe periods of N in a final subframe period.

Description

Stereoscopic Image Display {3D IMAGE DISPLAY DEVICE}

The present invention relates to a stereoscopic image display device that can improve the display quality.

The stereoscopic image display device implements a 3D stereoscopic image (hereinafter, referred to as a '3D image') using a binocular parallax technique or an autostereoscopic technique.

The binocular parallax method uses a parallax image of the left and right eyes with a large stereoscopic effect, and there are glasses and no glasses, both of which are put to practical use. The autostereoscopic method is generally provided with an optical plate such as a parallax barrier for separating the optical axis of the left and right parallax images in front of or behind the display screen. The spectacle method displays left and right parallax images having different polarization directions on a liquid crystal display panel, and realizes a stereoscopic image using polarized glasses or liquid crystal shutter glasses.

The spectacle method may be roughly classified into a first polarization filter method using a pattern retarder film and polarizing glasses, a second polarization filter method using a switching liquid crystal layer and polarizing glasses, and a shutter glass method using liquid crystal shutter glasses.

In the first polarization filter method, the left eye image and the right eye image are alternately displayed in units of horizontal lines on the liquid crystal display panel, and the left eye image and the right eye image are switched by switching polarization characteristics incident on the polarizing glasses through the pattern retarder film on the liquid crystal display panel. 3D image is realized by spatially dividing the. In the second polarization filter method, the left eye image and the right eye image are alternately displayed on a liquid crystal display panel in units of frames, and the left and right eye images are spatiotemporally spaced by switching polarization characteristics incident on the polarizing glasses through the switching liquid crystal layer on the liquid crystal display panel. 3D image is realized by dividing into. In the case of the first and second polarization filter methods, the transmittance of the 3D image is reduced due to the pattern retarder film or the switching liquid crystal layer disposed on the liquid crystal display panel to serve as a polarization filter.

In the shutter glass method, a left eye image and a right eye image are alternately displayed in units of frames on a liquid crystal display panel, and 3D image is realized by opening and closing the left and right eye shutters of the liquid crystal shutter glasses in synchronization with the display timing. The liquid crystal shutter glasses open only the left eye shutter during the first frame period in which the left eye image (eg, a white (W) image) is displayed on the liquid crystal display panel as shown in FIG. 1, and the right eye image (eg, black (B) is opened on the liquid crystal display panel. Only the right eye shutter is controlled to open during the second frame period in which the image) is displayed, creating binocular parallax in a time division manner.

As shown in the requirements of FIG. 1, in order to make a good binocular parallax by turning on the backlight in the second period Tb of each frame, the response of the liquid crystal must be completed within the first period Ta of each frame. However, the actual response time of the liquid crystal is not completed within the first period Ta but extends to the second period Tb. Due to the slow response speed of the liquid crystal, a phenomenon in which the luminance is low in the white state and high in the black state occurs. In other words, assuming that the backlight is turned on in the second period Tb, in the white state, the backlight is turned on before the rising saturation, and the backlight is displayed at a luminance level lower than the desired luminance level. Before this polling session, the backlight is turned on and displayed at a luminance level higher than the desired luminance level. When the backlight is turned on during this period, which is not fully white or black, ghost-shaped 3D crosstalk is generated.

Accordingly, it is an object of the present invention to provide a stereoscopic image display apparatus capable of improving display quality by improving the response speed of liquid crystals.

In order to achieve the above object, a stereoscopic image display device according to an embodiment of the present invention includes a liquid crystal display panel for displaying the left eye image and the right eye image alternately in a unit frame period; A data driver circuit driving data lines of the liquid crystal display panel; A gate driving circuit driving gate lines of the liquid crystal display panel; The unit frame period is divided into N (N is a positive integer of 2 or more) subframe periods, and the same unit frame data for displaying the left eye image or the right eye image to the data driving circuit during the N sub frame periods. A timing controller for supplying repeatedly; Light sources generating light to be irradiated onto the liquid crystal display panel; A light source control circuit for generating a backlight control signal for controlling the timing of lighting of the light sources; And a light source driving circuit for lighting all of the light sources within the last sub frame period of the N sub frame periods in response to the backlight control signal.

The stereoscopic image display device according to the present invention can prevent the 3D crosstalk by increasing the response speed of the liquid crystal, and in particular, it is possible to improve the MPRT performance without lowering the luminance in the video, thereby greatly improving the overall display quality.

1 is a view for explaining the cause of 3D crosstalk due to a slow liquid crystal response in a conventional stereoscopic image display.
2 is a view showing a stereoscopic image display device according to an embodiment of the present invention.
3 to 5 show timing of writing data, turning on and off of light sources, and opening timing of left and right shutters at a unit frame frequency of 120 Hz.
6 to 8 show timing of writing data, turning on and off of light sources, and opening timing of left and right shutters at a unit frame frequency of 80 Hz.
9 is a view showing an example in which the levels of the driving current are adjusted according to the duty ratio of the PWM signal to compensate for the luminance deterioration.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 9.

2 shows a stereoscopic image display device according to an embodiment of the present invention.

2, a stereoscopic image display device according to an exemplary embodiment of the present invention includes a liquid crystal display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a light source control circuit 14. ), A light source driving circuit 15, a backlight unit 16, a shutter control circuit 17, a shutter glass 18, and a data modulation circuit 20.

The liquid crystal display panel 10 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL cross on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal cells Clc are arranged in a matrix form on the liquid crystal display panel 10 due to the cross structure of the data lines DL and the gate lines GL. In the lower glass substrate of the liquid crystal display panel 10, TFTs, pixel electrodes 1 of liquid crystal cells Clc connected to TFTs, storage capacitors Cst, and the like are formed.

The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 10. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and has an in plane switching (IPS) mode and a fringe field switching (FFS) mode. In the same horizontal electric field driving method, the pixel electrode 1 is formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 10, and an alignment layer for setting a pretilt angle of the liquid crystal is formed on an inner surface of the liquid crystal display panel 10 in contact with the liquid crystal.

The timing controller 11 is a timing control signal for controlling the operation timing of the data driver circuit 12 and the gate driver circuit 13 based on timing signals Vsync, Hsync, DE, DCLK from an external system circuit. Generate (DDC, GDC). The timing controller 11 multiplies the data timing control signal DDC and the gate timing control signal GDC to multiply the data driving circuit 12 and the gate driving circuit at a N (N is a positive integer of 2 or more) double speed subframe frequency. 13) to control the operation.

The timing controller 11 time divisions the unit frame period into N sub frame periods. Then, the unit frame data (3D DATA) of the 3D data format input from the data modulation circuit 20 is copied in frame units using a frame memory or the like. Then, the same left eye frame data displayed when the left eye of the shutter glass 18 is opened is repeatedly supplied to the data driving circuit 12 during the sub frame periods of the odd unit frame, and the right eye of the shutter glass 18 is opened. The same right eye frame data displayed when is repeatedly supplied to the data driving circuit 12 during the sub frame periods of the even-th frame.

The data driver circuit 12 includes a plurality of data drive integrated circuits. The data drive integrated circuit includes a shift register for sampling a clock signal, a register for temporarily storing digital data input from the timing controller 11, and one line for storing and storing data one line at a time in response to a clock signal from the shift register. A latch for simultaneously outputting minute data, a digital / analog converter for selecting a positive / negative gamma voltage under reference to a gamma reference voltage corresponding to a digital data value from the latch, and a positive / negative gamma voltage And a multiplexer for selecting a data line DL to which analog data converted by the same is supplied, and an output buffer connected between the multiplexer and the data line DL. The data driving circuit 12 converts left eye / right eye frame data into an analog data voltage based on the data timing control signal DDC synchronized to the N double speed sub frame frequency and applies the data to the data lines DL.

The gate driving circuit 13 includes a plurality of gate drive integrated circuits. The gate drive integrated circuit includes a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for driving a TFT of a liquid crystal cell, an output buffer, and the like. The gate driving circuit 13 sequentially outputs scan pulses (or gate pulses) to the gate lines GL based on the gate timing control signal GDC synchronized to the N-fold subframe frequency.

The backlight unit 16 includes a plurality of light sources to irradiate light to the liquid crystal display panel 10. The backlight unit 16 may be implemented as one of a direct type and an edge type. The direct type backlight unit 16 has a structure in which a plurality of optical sheets and a diffusion plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed below the diffusion plate. The edge type backlight unit 16 has a structure in which a plurality of optical sheets and a light guide plate are stacked below the liquid crystal display panel 10 and a plurality of light sources are disposed on the side of the light guide plate. The light sources can be implemented with line light sources such as Cold Cathode Fluorescent Lamps (CCFLs) or External Electrode Fluorescent Lamps (EEFLs), and are similar to Light Emitting Diodes (LEDs). It can be implemented with light sources.

The light source control circuit 14 generates a light source control signal LCS under the control of the timing controller 11, and modulates the light sources such that the light sources are simultaneously driven by blinking through the light source control signal LCS. Pulse Width Modulation, PWM). The light source control circuit 14 may control the light sources by pulse amplitude modulation (PAM) or pulse frequency modulation (PFM). Maximum duty ratio of PWM signal ) Can be preset in the range of 50% or 33% or less so that the moving picture response time (MPRT) performance can be improved along with 3D crosstalk cancellation. In other words, as the maximum duty ratio of the PWM signal is set smaller, the level of the driving current is set higher, which corresponds to an increase in the unlit time of the light sources 16 within the unit frame period. The light source control circuit 14 may adjust the duty ratio of the PWM signal within the maximum duty ratio range based on the analysis result of the unit frame data (3D DATA). The light source control circuit 14 may be built into the timing controller 11.

The light source control signal LCS includes a timing of turning on and off the light sources. The timing of lighting of the light sources is determined after the liquid crystals disposed in the middle horizontal line portion of the liquid crystal display panel 10 are saturated within the unit frame period in order to minimize the optical interference, but the timing of the PWM signal It can be determined differently. The timing of turning off the light sources may be fixed to the end of the unit frame period.

The light source driving circuit 15 lights all of the light sources within the last sub frame period of the N sub frame periods in response to the light source control signal LCS to thereby cause the light sources to blink.

The shutter control circuit 17 refers to the vertical synchronization signal Vsync input from the system circuit to determine whether the current unit frame is the odd unit frame in which the left eye frame data is to be displayed or the even unit frame in which the right eye frame data is to be displayed. Judge. The left eye shutter control signal STL for controlling the left eye shutter of the shutter glass 18 during the odd unit frame period, and the right eye shutter control for opening the right eye shutter of the shutter glass 18 during the even unit frame period. Generate signal STR.

The shutter glass 18 is a device worn by the viewer to stereoscopically view the left / right eye image displayed on the LCD panel 10 in units of frames. The shutter control signals STL and STR from the shutter control circuit 17 are displayed. His left / right shutters are alternately opened and closed in cycles of unit frames. As a result, different images are formed in the left and right sides of the shutter glass 18, and the viewers feel a three-dimensional effect.

The data modulation circuit 20 inserts interpolation frame data into image frame data supplied from a video source to generate unit frame data. For example, the data modulation circuit 20 may generate unit frame data synchronized with a unit frame frequency of 120 Hz by inserting one interpolation frame data per image frame data input at 60 Hz. In addition, the data modulation circuit 20 may generate unit frame data synchronized with a unit frame frequency of 80 Hz by inserting one interpolation frame data for every three image frame data input at 60 Hz. The data modulation circuit 20 supplies the generated unit frame data to the timing controller 11. The data modulation circuit 20 may be built in the system circuit or the timing controller 11.

3 to 5 show data writing to improve display quality, timing of turning on and off of light sources, and opening timing of left and right shutters at a unit frame frequency of 120 Hz.

3 and 4, when the unit frame frequency is 120 Hz, the timing controller divides the unit frame period into first and second sub frame periods SF1 and SF2 and doubling the unit frame data. Thereafter, the same unit frame data is repeatedly supplied to the data driving circuit during the first and second sub frame periods SF1 and SF2. The timing controller multiplies the unit frame frequency to control the gate and data driving circuits at a double speed subframe frequency (240 Hz). As a result, the same left eye frame data DATA (L) is repeatedly displayed on the LCD panel during the first and second sub-frames SF1 and SF2 of the odd frame, and the even-numbered unit frame The same right eye frame data DATA (R) is overlapped and displayed on the liquid crystal display panel during the first and second sub frames SF1 and SF2 of the Even Frame.

Since the response speed of the liquid crystal LC is inversely proportional to the capacitor component present in the liquid crystal display panel, and the capacitor component is inversely proportional to the frame frequency, as a result, the response speed of the liquid crystal LC is increased accordingly by doubling the unit frame frequency. . As a result, the time corresponding to the first subframe SF1 from immediately after the left eye frame data DATA (L) is written in the center of the liquid crystal display panel 10 in the odd frame. Before the elapsed time, the liquid crystal LC of the middle part is segmented and maintains this segmentation state until the second subframe SF2. In the odd unit frame, all of the light sources BL are turned on at the same time in the second sub frame period SF2 in which the center liquid crystal LC is maintained in the saturation state. The left eye shutter is opened during the odd frame.

In addition, a time for the first subframe SF1 has elapsed since the right eye frame data DATA (R) is written in the center of the liquid crystal display panel 10 in the even frame. Before the process, the liquid crystal LC of the center part is segmented and maintains this segmentation state until the second subframe SF2. In the even-even unit frame, all of the light sources BL are turned on at the same time in the second sub frame period SF2 in which the middle liquid crystal LC is maintained in the saturation state. The right eye shutter is opened during the even frame.

The timing of turning on the light sources BL may be differently determined according to the maximum duty ratio of the PWM signal as shown in FIG. 5. For example, the timing of turning on the light sources BL may be determined as the first time point t1 to implement a maximum duty ratio of 50%, and later than the first time point t1 to implement a maximum duty ratio of less than 50%. It may be determined as the second time point t2.

3 to 5, the response speed of the liquid crystal is improved compared to the conventional method, and 3D crosstalk is greatly reduced. However, since the lighting timing of the light sources is determined based on the middle portion of the liquid crystal display panel and the unit frame period is relatively short as 1 second / 120 (approximately 8.33 ms), the lower end liquid crystal of the liquid crystal display panel is written later than the middle portion. In response to the data it may still be in a transition state during the lighting period of the light sources. In this case, the degree of reduction of 3D crosstalk may decrease at the lower end of the liquid crystal display panel. In order to eliminate the 3D crosstalk alleviation deviation, it is necessary to sufficiently increase the time to be devoted to the liquid crystal response before the light source is turned on.

6 to 8 show data writing to improve display quality, timings of turning on and off light sources, and opening timing of left and right shutters at a unit frame frequency of 80 Hz.

6 and 7, when the unit frame frequency is 80 Hz, the timing controller divides the unit frame period into first to third sub frame periods SF1 to SF3 and triples the unit frame data. After that, the same unit frame data is repeatedly supplied to the data driving circuit during the first to third sub frame periods SF1 to SF3. In addition, the timing controller multiplies the unit frame frequency to control the gate and data driving circuit at the triple speed subframe frequency (240 Hz). As a result, the same left eye frame data DATA (L) is repeatedly displayed on the LCD panel during the first to third sub frame periods SF1 to SF3 of the odd unit frame (Odd Frame), and the even-numbered unit frame is displayed. During the first to third sub frame periods SF1 to SF3 of the Even Frame, the same right eye frame data DATA (R) is overlapped and displayed on the liquid crystal display panel.

The response speed of the liquid crystal LC is inversely proportional to the capacitor component present in the liquid crystal display panel, and the capacitor component is inversely proportional to the frame frequency. As a result, the response speed of the liquid crystal LC is increased by three times the unit frame frequency. . As a result, the time corresponding to the first subframe SF1 from immediately after the left eye frame data DATA (L) is written in the center of the liquid crystal display panel 10 in the odd frame. Before the elapsed time, the liquid crystal LC of the middle part is segmented and maintains this segmentation state until the third subframe SF3. In the odd unit frame, all of the light sources BL are turned on at the same time in the third sub frame period SF3 in which the center liquid crystal LC is maintained in the saturation state. The left eye shutter is opened during the odd frame.

In addition, a time elapsed by the first subframe SF1 from immediately after the right eye frame data DATA (R) is written in the center of the liquid crystal display panel 10 in the even frame. Before the process, the liquid crystal LC of the center part is segmented and maintains this segmentation state until the third subframe SF2. In the even-even unit frame, all the light sources BL are turned on at the same time in the third sub frame period SF3 in which the middle liquid crystal LC is maintained in the saturation state. The right eye shutter is opened during the even frame.

The timing of turning on the light sources BL may be differently determined according to the maximum duty ratio of the PWM signal as shown in FIG. 8. For example, the timing of the lighting of the light sources BL may be determined as the first time point t1 to implement the maximum duty ratio 33%, and later than the first time point t1 to implement the maximum duty ratio smaller than 33%. It may be determined as the second time point t2.

According to the driving of FIGS. 6 to 8, the response speed of the liquid crystal is improved compared to the related art, and 3D crosstalk is greatly reduced. Further, even if the timing of turning on the light sources is determined on the basis of the middle part of the liquid crystal display panel, no reduction in 3D crosstalk occurs. This means that the unit frame period is 1 second / 80 (that is, 12.5 ms), which is relatively long, and the time to be allocated to the liquid crystal reaction is increased in proportion to it, so that the liquid crystal of the liquid crystal panel is set before the light sources are turned on regardless of its position. This is because

9 shows an example in which the levels of the driving current are adjusted according to the duty ratio of the PWM signal in order to compensate for the lowering of luminance during backlight blinking driving.

Referring to FIG. 9, the level of the driving current is set to have an inverse relationship with the maximum duty ratio of the PWM signal. For example, the level of the driving current is 2 times (2A) of the reference current level A in response to the PWM signal set to the maximum duty ratio of 50%, and the reference current in response to the PWM signal set to the maximum duty ratio of 33%. 3 times (3A) of the level (A), corresponding to the PWM signal set to the maximum duty ratio of 25% 4 times (4A) of the reference current level (A) to the PWM signal set to the maximum duty ratio of 20% Correspondingly, 5 times 5A of the reference current level A can be set. Here, the reference current level A is a current level corresponding to the maximum duty ratio of 100% and is stored in advance in a specific register in the light source control circuit.

As described above, the stereoscopic image display apparatus controls the operation of the driving circuits at a frequency faster than the unit frame frequency, divides the unit frame into a plurality of subframes, and repeatedly displays the same data. Then, all of the light sources are turned on within the last sub frame period among the plurality of sub frames, and the left and right eye shutters are alternately opened and closed every unit frame period. In addition, the decrease in luminance of the display surface due to the blinking driving is compensated for by increasing the light source driving current. Accordingly, the 3D image display device according to the present invention can increase the response speed of the liquid crystal to prevent 3D crosstalk, and can further improve the display quality as a whole by improving the MPRT performance without lowering the luminance in the video. have.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

10 liquid crystal display panel 11 timing controller
12: data driving circuit 13: gate driving circuit
14 light source control circuit 15 light source driving circuit
16 backlight unit 17 shutter control circuit
18: shutter glass 20: data modulation circuit

Claims (12)

A liquid crystal display panel configured to alternately display a left eye image and a right eye image at a unit frame period;
A data driver circuit driving data lines of the liquid crystal display panel;
A gate driving circuit driving gate lines of the liquid crystal display panel;
The unit frame period is divided into N (N is a positive integer of 2 or more) subframe periods, and the same unit frame data for displaying the left eye image or the right eye image to the data driving circuit during the N sub frame periods. A timing controller for supplying repeatedly;
Light sources generating light to be irradiated onto the liquid crystal display panel;
A light source control circuit for generating a backlight control signal for controlling the timing of lighting of the light sources; And
And a light source driving circuit for lighting all of the light sources within the last sub frame period of the N sub frame periods in response to the backlight control signal. The method of claim 1,
And the backlight control signal is any one of a pulse width modulation (PWM) signal, a pulse amplitude modulation (PAM) signal, and a pulse frequency modulation (PFM) signal. The method of claim 1,
And the timing controller multiplies a unit frame frequency to control an operation timing of the driving circuits at a Nx speed subframe frequency. The method of claim 3, wherein
When the unit frame frequency is 120 Hz, the timing controller,
Dividing the unit frame period into first and second sub frame periods;
After copying the unit frame data, the same unit frame data is repeatedly supplied to the data driving circuit during the first and second sub frame periods;
And multiplying the unit frame frequency to control operations of the driving circuits at a double speed subframe frequency. The method of claim 3, wherein
When the unit frame frequency is 80 Hz, the timing controller,
Dividing the unit frame period into first to third sub frame periods;
After copying the unit frame data, the same unit frame data is repeatedly supplied to the data driving circuit during the first to third sub frame periods;
And multiplying the unit frame frequency to control the operation of the driving circuits at a triple subframe frequency. The method of claim 1,
And the light source control circuit further generates a current control signal for controlling a driving current applied to the light sources. The method according to claim 6,
And the level of the driving current is preset to be inversely proportional to the maximum duty ratio of the backlight control signal. The method according to claim 4 or 5,
The maximum duty ratio of the backlight control signal is preset in the range of 33% or less or 50% or less,
The timing of turning on the light sources is delayed as the maximum duty ratio of the backlight control signal is set smaller. The method of claim 1,
And a shutter glass including a left eye shutter opened in a unit frame period in which the left eye image is displayed, and a right eye shutter opened in a unit frame period in which the right eye image is displayed. The method of claim 9,
The unit frame data is left eye frame data or right eye frame data;
The timing controller,
Repetitively supplying the same left eye frame data to the data driving circuit during the N sub frame periods in which the left eye image is displayed;
And supplying the same right eye frame data to the data driving circuit repeatedly during the N sub frame periods in which the right eye image is displayed. The method of claim 1,
The timing of turning on the light sources is determined after the liquid crystal in the middle portion of the liquid crystal display panel is segregated. The method of claim 1,
A data modulation circuit for supplying the unit frame data to the timing controller;
And the data modulation circuit generates the unit frame data by inserting interpolation frame data into input frame data.

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