KR20110079304A - Method for manufacturing of semiconductor device - Google Patents

Method for manufacturing of semiconductor device Download PDF

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Publication number
KR20110079304A
KR20110079304A KR1020090136322A KR20090136322A KR20110079304A KR 20110079304 A KR20110079304 A KR 20110079304A KR 1020090136322 A KR1020090136322 A KR 1020090136322A KR 20090136322 A KR20090136322 A KR 20090136322A KR 20110079304 A KR20110079304 A KR 20110079304A
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KR
South Korea
Prior art keywords
well
conductivity type
substrate
forming
type
Prior art date
Application number
KR1020090136322A
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Korean (ko)
Inventor
유재현
Original Assignee
주식회사 동부하이텍
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Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020090136322A priority Critical patent/KR20110079304A/en
Publication of KR20110079304A publication Critical patent/KR20110079304A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/06—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials
    • H01L21/10—Preliminary treatment of the selenium or tellurium, its application to the foundation plate, or the subsequent treatment of the combination
    • H01L21/108—Provision of discrete insulating layers, i.e. non-genetic barrier layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biotechnology (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

A method of manufacturing a semiconductor device according to the present embodiment may include: forming a shallow well of a second conductivity type by implanting a second conductivity type impurity into a first conductivity type substrate in the high voltage area; Implanting a first conductivity type impurity into the substrate to form a deep well of a first conductivity type; Forming an isolation layer on the substrate; And forming a gate electrode on the substrate, and forming a drain region for a drain contact and a doping region for a well contact in the substrate.

Description

Method for manufacturing a semiconductor device

This embodiment discloses a semiconductor device.

Conventionally, a well contact structure as shown in FIG. 1 is used for a typical well ground.

Referring to FIG. 1, an N-type deep well 2 is formed in a P-type semiconductor substrate 1, and an element isolation film 3 for device isolation is formed.

P-type wells 5 for drain contacts and N-type wells 6 for well contacts are formed on the substrate surface.

Here, the distance from the drain contact to the well contact must be sufficiently maintained so that the well contact is not affected by the voltage that can be applied to the drain.

If the distance between the drain and the well is close, as shown in FIG. 2, the device isolation layer 3 acts as a small parasitic capacitance due to the voltage applied to the drain, which may occur in the process. A leakage current between the drain and the well may be generated by the device isolation interface trap.

Therefore, the design of the distance between the drain and the well is important.

This embodiment proposes a semiconductor device in which isolation between the drain and the well can be achieved.

The proposed semiconductor device reduces the area occupied for isolation, and furthermore, proposes a structure capable of highly integrated semiconductor devices.

A method of manufacturing a semiconductor device according to the present embodiment may include: forming a shallow well of a second conductivity type by implanting a second conductivity type impurity into a first conductivity type substrate in the high voltage area; Implanting a first conductivity type impurity into the substrate to form a deep well of a first conductivity type; Forming an isolation layer on the substrate; And forming a gate electrode on the substrate, and forming a drain region for a drain contact and a doped region for a well contact in the substrate.

The shallow well of the second conductivity type is formed at a higher doping concentration than the deep well of the first conductivity type.

The shallow wells of the second conductivity type are selectively formed around the device isolation layer.

In the forming of the shallow well of the second conductivity type, the shallow well of the second conductivity type is formed at the base end of the PNP or NPN transistor formed in the substrate.

According to the semiconductor device of the embodiment as proposed, there is an advantage that can maintain a small amount of leakage current while maintaining a short distance between the drain and the well compared to the conventional isolation structure.

In addition, there is an advantage that can suppress the latch-up (latch-up) characteristics, there is an advantage that can be implemented in the existing mask combination without the mask addition process.

Hereinafter, with reference to the accompanying drawings for the present embodiment will be described in detail. However, the scope of the idea of the present invention may be determined from the matters disclosed by the present embodiment, and the idea of the invention of the present embodiment may be performed by adding, deleting, or modifying components to the proposed embodiment. It will be said to include variations.

In the following description, the word 'comprising' does not exclude the presence of other elements or steps than those listed. In addition, in the accompanying drawings, the thickness thereof is enlarged in order to clearly express various layers and regions. In addition, the same reference numerals are used for similar parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only being another part "on top" but also having another part in the middle.

3 to 5 are views for explaining a method of manufacturing a semiconductor device according to the present embodiment.

3 through 5 illustrate a high voltage region. First, referring to FIG. 3, a second conductivity type impurity is injected into a first conductivity type substrate 10. The second conductivity type ion implantation region 11 is formed.

In the figure, since the first conductivity type impurity is exemplified by P type and the second conductivity type impurity is exemplified by N type, the following description will be given as an example of P type and N type for convenience of explanation.

That is, according to this embodiment, the N-type shallow well 11 is formed in the P-type semiconductor substrate 10. By using low voltage wells for the high voltage region, well isolation can be enhanced.

The formation depth of the N-type shallow well 11 is designed so that the P-type deep well 13 formed by a subsequent process is located between the P-type substrate 10 and the N-type shallow well 11. . The N type shallow well 11 is formed to have a higher doping concentration than the P type deep well 13 described later.

In addition, the device isolation layer 12 is formed on the substrate 10.

Next, referring to FIG. 4, a first conductivity type impurity is implanted into the substrate 10 to form a P-type deep well 13.

According to the present embodiment, when forming a high voltage (HV) PMOS, a process for forming an N-type shallow well (LV Nwell) 11 prior to forming a P-type deep well (HV Pwell) 13 isolating region. Optionally. That is, before forming the P-type deep well 13, an N-type shallow well 11 is formed around the device isolation film 12, whereby depletion occurs around the device isolation film 12. Can be reduced.

Next, referring to FIG. 5, a gate electrode 15 is formed on the substrate 10, a drain region 16, which is a first conductivity type impurity region for drain contact, and a second conductivity for well contact. A well region 17 which is a type impurity region is formed in the substrate.

By this method, the N type shallow well 11 into which the second conductivity type impurity is implanted is formed around the device isolation film 12 and the well region 17, thereby generating parasitic impedance at the interface of the device isolation film 12. Can be reduced.

That is, as described above, when a strong negative bias is conventionally applied to the drain, a strong E-field is applied to the device isolation layer because the distance between the drain region and the well region is sufficiently short, which causes depletion. . Such depletion serves as a source for generating carriers, and there is a problem in that a large number of parasitic carriers are generated at an interface of a device separator that generates many traps in the process.

However, by the N-type shallow well 11 formed at a relatively high doping concentration according to the present embodiment, even if the distance between the drain region 16 and the well region 17 is short, the dipley under the device isolation film 12 is reduced. By eliminating the option, it can play an effective role as isolation.

6 is a view for explaining the configuration and characteristics of the semiconductor device according to the second embodiment of the present invention.

Well isolation may be enhanced by a well structure proposed in the present invention, that is, a structure in which a low voltage well is applied to a region to which a high voltage is applied. As shown in Fig. 6, the base resistances of the NPN and the PNP are lowered by the low voltage P well (LVPW) 101 and the low voltage N well (LVNW) 102 formed in the high voltage region, which is a kind of rectifier. It is effective to increase the triggering and holding voltage of the SCR.

In addition, the doping between the wells to the wells is increased, so that the leakage current can be eliminated.

7 is a view for explaining the configuration and characteristics of the semiconductor device according to the third embodiment of the present invention.

That is, FIG. 7 illustrates a latch free semiconductor device, which is characterized by applying well taps 71 and 72 when the distance between NPN and PNP is sufficiently secured. It is done.

In detail, a low voltage P well (LVPW) 71 and a low voltage N well (LVNW) 72 are formed between the NPN and the PNP in the high voltage region of the semiconductor device, and the base of the NPN and PNP is similar to that in FIG. 6. The low voltage P well (LVPW) 101 and the low voltage N well (LVNW) 102 are formed to lower the resistance.

Such a structure serves to subtract the leakage current causing the latch from the regions of the low voltage wells 71 and 72 formed in the center, and even in this structure, the LV well process reduces the well resistance, thereby reducing the latch characteristics. It can be improved more.

8 is a view for explaining the configuration and characteristics of the semiconductor device according to the fourth embodiment of the present invention.

8 is a diagram illustrating a method of suppressing a latch caused by an external current source. In the figure, when the conventional technique, the hole current applied from the diode P + flows into the well of the NMOS to generate a latch is shown by arrow 8A.

That is, in the case of the bipolar transistor, since the resistance shown by Rpw is formed at the base end, the voltage in that region increases, which causes the base voltage of the bipolar transistor to increase, resulting in the NMOS transistor being operated and eventually the arrow of 8A. As in the case, a current may flow.

However, when the low voltage P well (LVPW) 81 is formed at the base end of the NMOS transistor according to the embodiment of the present invention, the resistance of the base end of the transistor is lowered, which causes the transistor to be leaked by the leakage current. The malfunction can be prevented.

Similarly, by forming the low voltage N well (LVNW) 82 in the PNP region and lowering the resistance at the base end of the transistor, it is possible to suppress the transistor from malfunctioning due to leakage current.

1 illustrates a well contact structure for a typical well ground in the prior art.

2 is a view for explaining a leakage current generated in the conventional structure.

3 to 5 are views for explaining the manufacturing method of the semiconductor device according to the present embodiment.

6 is a view for explaining the configuration and characteristics of the semiconductor device according to the second embodiment of the present invention.

7 is a view for explaining the configuration and characteristics of the semiconductor device according to the third embodiment of the present invention.

8 is a view for explaining the configuration and characteristics of the semiconductor device according to the fourth embodiment of the present invention.

Claims (5)

In a semiconductor device having a high voltage region, Implanting a second conductivity type impurity into the first conductivity type substrate in the high voltage region to form a shallow well of a second conductivity type; Implanting a first conductivity type impurity into the substrate to form a deep well of a first conductivity type; Forming an isolation layer on the substrate; And Forming a gate electrode on the substrate, and forming a drain region for a drain contact and a doped region for a well contact in the substrate. The method of claim 1, And the shallow well of the second conductivity type is formed at a higher doping concentration than the deep well of the first conductivity type. The method of claim 1, The shallow well of the second conductivity type is selectively formed around the device isolation film. The method of claim 1, The forming of the second well type shallow well may include forming the second well type shallow well at a base end of a PNP or NPN transistor formed in a substrate. The method of claim 1, The first conductive type is a P-type impurity, and the second conductive type is an N-type impurity manufacturing method.
KR1020090136322A 2009-12-31 2009-12-31 Method for manufacturing of semiconductor device KR20110079304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090136322A KR20110079304A (en) 2009-12-31 2009-12-31 Method for manufacturing of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090136322A KR20110079304A (en) 2009-12-31 2009-12-31 Method for manufacturing of semiconductor device

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KR20110079304A true KR20110079304A (en) 2011-07-07

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