KR20110079066A - Phase locked loop circuit - Google Patents

Abstract

PURPOSE: A phase locked loop circuit is provided to reduce noises due to an amount of currents by generating a locked voltage oscillation signal by applying a locked DC voltage to a voltage controlled oscillating unit. CONSTITUTION: A voltage controlled oscillating unit(130) outputs a voltage controlled oscillation signal in proportion to a first or second DC voltage. A counter unit(140) divides a voltage controlled oscillation signal into a phase and a frequency and outputs the divided signal. A phase and frequency comparing unit(100) outputs an error signal corresponding to the phase difference and frequency difference. A charge pump unit(110) charges or discharges the amount of currents by using the phase element and frequency element of the error signal. A low pass filter(120) converts the amount of currents charged or discharged in the charge pump unit into a first DC voltage and outputs the first DC voltage.

Description

Phase Locked Loop Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit, and more particularly, to a phase locked loop circuit having low noise and fast locking time.

1 is a block diagram showing a phase locked loop circuit according to the prior art.

As shown in FIG. 1, the conventional phase-locked loop circuit includes a phase and frequency comparison unit 10, a charge pump unit 11, a low pass filter unit 12, a voltage controlled oscillator unit 13, and a counter unit 14. It consists of

The output signal FOUT generated by the voltage controlled oscillator 13 is divided into a phase and a frequency by the counter 14 and input to the phase and frequency comparator 10.

The phase and frequency comparison unit 10 compares the phase and frequency of the input signal FIN with the phase and frequency input by being divided by the counter unit 14, and outputs a phase difference and a frequency difference according to the comparison result. The phase and frequency comparison unit 10 outputs the phase difference and the frequency difference as an error signal.

The charge pump unit 11 charges or discharges the amount of current using the phase component and the frequency component of the error signal output from the phase and frequency comparator 10.

The low pass filter unit 12 converts the amount of current charged or discharged in the charge pump unit 10 into a DC voltage.

The voltage controlled oscillator 13 generates a voltage controlled oscillation signal proportional to the DC voltage output from the low pass filter 12.

In the conventional phase synchronizing loop circuit configured as described above, if the phase and frequency of the input signal FIN are faster than the phase or frequency of the voltage controlled oscillation signal fed back from the voltage controlled oscillator 13, the phase and frequency comparator 10 Outputs a positive pulse at and causes the charge pump unit 11 to increase the amount of current being charged or discharged. As the amount of current increases, the low pass filter unit 12 increases the output DC voltage, and the voltage controlled oscillator 13 speeds up the phase and frequency of the output voltage controlled oscillation signal due to the increase of the DC voltage. Thereby, the phase and frequency of the voltage controlled oscillation signal are synchronized with those of the input signal FIN.

On the contrary, if the phase and frequency of the input signal FIN are slower than the phase and frequency of the voltage controlled oscillation signal fed back from the voltage controlled oscillator 13, the phase and frequency comparator 10 outputs a negative pulse. The charge pump section 11 causes the amount of current to be charged or discharged to be reduced. As the amount of current decreases, the low pass filter unit 12 decreases the output DC voltage, and the voltage controlled oscillator 13 slows the phase and frequency of the output voltage controlled oscillation signal due to the reduction of the DC voltage. Thereby, the phase and frequency of the voltage controlled oscillation signal are synchronized with those of the input signal FIN.

In such a conventional phase-locked loop circuit, the charge pump unit 11 increases or decreases the amount of current by receiving a positive or negative pulse generated from the phase and frequency comparison unit 10. In addition, the increase or decrease of the amount of current causes the low pass filter unit 12 to increase or decrease the DC voltage. However, there is a problem of increasing the noise of the phase-locked loop circuit as a whole due to the difference in the amount of current charged or discharged in the charge pump unit 11. In addition, there is a delay by the locking time in order to generate the desired frequency. Specifically, when the positive and negative pulse widths generated by the phase and frequency comparator 10 are the same, the same amount of current must be charged or discharged, but in some cases, There will be a difference. Such a difference in the amount of current causes the noise of the phase locked loop circuit to increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase locked loop circuit that solves noise and locking time delay problems by applying a fixed DC voltage to a voltage controlled oscillator to generate a fixed voltage controlled oscillation signal. To provide.

According to an aspect of the present invention, there is provided a phase locked loop circuit including: a voltage controlled oscillator for outputting a voltage controlled oscillation signal proportional to any one of different first and second DC voltages; A counter unit which divides and outputs the voltage controlled oscillation signal outputted from the voltage controlled oscillator in phase and frequency; A phase and frequency comparison unit for comparing the phase and frequency divided by the counter with the phase and frequency of the input signal, and outputting an error signal corresponding to the phase difference and the frequency difference according to the comparison result; A charge pump unit for charging or discharging the amount of current by using a phase component and a frequency component of the error signal output from the phase and frequency comparison unit; A low pass filter unit converting an amount of current charged or discharged in the charge pump unit into the first DC voltage and outputting the first DC voltage; A DC voltage supply unit for supplying the second DC voltage to the voltage controlled oscillator while interrupting an input path to the voltage controlled oscillator for the first DC voltage; Locking to compare the phase and frequency divided by the counter unit with the phase and frequency of the input signal input to the phase and frequency comparison unit, and to control the operation of the DC voltage supply unit to an active or inactive state according to the comparison result. It consists of a detector.

According to the present invention, by applying a fixed DC voltage to the voltage-controlled oscillation unit to generate a fixed voltage-controlled oscillation signal, to solve the noise problem due to the difference in the amount of current generated even though the same amount of current must be charged or discharged In addition, it is possible to generate a desired frequency by using the code values stored in the memory at the stored maximum frequency and the minimum frequency, while storing the code values at the maximum frequency and the minimum frequency in the memory. Locking time can be implemented.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a configuration and an operation of an embodiment of the present invention will be described with reference to the accompanying drawings, and the configuration and operation of the present invention shown in and described by the drawings will be described as at least one embodiment, The technical idea of the present invention and its essential structure and action are not limited.

Hereinafter, a preferred embodiment of a phase locked loop circuit according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the phase-locked loop circuit according to an embodiment includes a phase and frequency comparison unit 100, a charge pump unit 110, a low pass filter unit 120, a voltage controlled oscillator 130, and a counter. A first and second switches 150 and 151, a locking detector 160, a triangular wave generator 161, an analog-to-digital converter 162, and a digital-analog, which include a unit 140 and which is added to solve noise problems. It further includes a converter 163.

The output signal FOUT generated by the voltage controlled oscillator 130 is divided into phases and frequencies by the counter 140 and input to the phase and frequency comparator 100.

The phase and frequency comparison unit 100 compares the phase and frequency of the input signal FIN with the phase and frequency input by being divided by the counter 140 and outputs a phase difference and a frequency difference according to the comparison result. The phase and frequency comparison unit 100 outputs the phase difference and the frequency difference as an error signal.

The charge pump 110 charges or discharges the amount of current using the phase component and the frequency component of the error signal output from the phase and frequency comparator 100.

The low pass filter unit 120 converts the amount of current charged or discharged in the charge pump unit 100 into a DC voltage. The DC voltage converted by the low pass filter unit 120 is defined as "DC voltage_value".

The first and second switches 150 and 151 are turned on / off according to the switch selection signal output from the digital-analog converter 163. Here, the switch selection signal turns off the second switch 151 while turning on the first switch 150 to transmit the DC voltage_value to the voltage controlled oscillator 130. On the contrary, the switch selection signal turns on the first switch while turning on the second switch 151 to transfer the DC voltage ("DC voltage _ or") output from the digital-analog converter 163 to the voltage controlled oscillator 130. 150) is turned off.

The first switch 150 is provided between the low pass filter 120 and the voltage controlled oscillator 130. When the first switch 150 is turned on according to the switch selection signal, the DC voltage converted from the low pass filter 120 is reduced. Is input to 130. At this time, the second switch 151 is turned off to interrupt the input of the DC voltage.

Two different input paths of the voltage controlled oscillator 130 are provided. One input path is a DC voltage_additional input path and the other is a DC voltage_I input path. The second switch 151 is provided in the DC voltage_I input path and is provided between the digital-analog converter 163 and the voltage controlled oscillator 130. When the second switch 151 is turned on according to the switch selection signal, the DC voltage_naga output from the digital-analog converter 163 is input to the voltage control oscillator 130. At this time, the first switch 150 is turned off to interrupt the input of the DC voltage.

The voltage controlled oscillator 130 generates a voltage controlled oscillation signal proportional to the DC voltage_ output from the low pass filter 120 or the DC voltage_ output from the digital-analog converter 163.

The counter 140 divides the voltage-controlled oscillation signal generated by the voltage-controlled oscillator 130, that is, the output signal FOUT into phase and frequency, and inputs it to the phase and frequency comparison unit 100. In particular, the counter 140 divides the same frequency as the input signal FIN.

The locking detector 160 is connected to the output terminal of the counter unit 140 while being connected to the input terminal of the phase and frequency comparison unit 100, and the frequency of the input signal FIN input to the phase and frequency comparison unit 100. The frequency divided and output by the counter 140 is compared, and a lock signal is generated according to whether a difference between two frequencies occurs according to the comparison result. That is, when the two frequencies are the same as the comparison result, a lock signal is generated.

The lock signal generated by the locking detector 160 includes components (triangle wave generator, analog-to-digital converter, and digital-to-analog converter) for supplying the aforementioned DC current_I to the voltage control generator 130 (hereinafter, This signal controls the operation of DC voltage_ or supply block). That is, the components (triangle wave generator, analog-digital converter, and digital-analog converter) for supplying the DC current_I to the voltage control generator 130 are generated by a lock signal from the locking detector 160. In this case, it becomes an active state.

The triangular wave generator 161 generates and outputs a triangular wave when in an active state. That is, when the frequency of the input signal FIN input to the phase and frequency comparator 100 and the frequency divided by the counter 140 are the same, a triangular wave is generated and output.

The analog-to-digital converter 162 uses the triangle wave output from the triangle wave generator 161 and the DC voltage_value converted from the low pass filter 120 as inputs, and compares the two inputs. That is, the input triangular wave is compared with the DC voltage. The analog-digital converter 162 outputs a code value according to the comparison result. The sign value is preferably a pulse count value at the same level of the input triangular wave and the DC voltage_ value. See FIG. 8 for this. As shown in FIG. 8, the count value of the pulse is output as a code value to a point A at which the triangular wave and the DC voltage_value are at the same level.

The digital-analog converter 163 outputs a DC voltage_ and a switch selection signal according to a code value output from the analog-digital converter 162. That is, the first switch 150 is turned off and the second switch 151 turns on the switch selection signal for outputting the DC voltage corresponding to the code value while the DC voltage_NA is inputted to the voltage controlled oscillator 130. Output

3 is a block diagram illustrating a phase locked loop circuit according to another exemplary embodiment of the present invention, and further includes a memory unit 164 operating according to a code selection signal and storing a plurality of code values in the circuit configuration of FIG. 2. It is an example provided.

The memory unit 164 includes a maximum frequency code value that is a pulse count value at the same level of a triangular wave and a maximum DC voltage_value (DC voltage_value_maximum value), a triangle wave and a minimum DC voltage_value (DC voltage_ Stores the minimum frequency code value that is the pulse count value at the same level of (_ minimum value).

The following describes the operation of the phase locked loop circuit according to the above configuration.

4 to 5 are block diagrams for describing an operation of a phase locked loop circuit according to an exemplary embodiment of the present invention.

The first loop shown in FIG. 4 shows a general phase-locked loop, and the voltage controlled oscillator 130 outputs a voltage controlled oscillation signal proportional to the DC voltage_value that is the output of the low pass filter 120. In this case, the locking detector 160 does not generate a lock signal as the frequency of the input signal FIN input to the phase and frequency comparator 100 and the frequency divided by the counter 140 are different from each other. Do not. That is, the operation of components (a triangle wave generator, an analog-digital converter, and a digital-analog converter) for supplying the DC current_I to the voltage control generator 130 is controlled in an inactive state.

On the other hand, in the first loop, the DC voltage _ value that is the output of the low pass filter 120 at the minimum frequency and the maximum frequency can be obtained.

In the second loop illustrated in FIG. 5, the frequency of the input signal FIN input to the phase and frequency comparator 100 and the frequency divided and output from the counter 140 are the same. Accordingly, the operation of components (a triangle wave generator, an analog-to-digital converter, and a digital-analog converter) for supplying the DC current_I to the voltage control generator 130 is controlled in an active state.

The triangular wave generator 161 generates and outputs a triangular wave, and the analog-to-digital converter 162 inputs the triangular wave output from the triangular wave generator 161 and the DC voltage_value converted from the low pass filter 120 as its input. Compare two inputs. The analog-digital converter 162 outputs a code value according to the comparison result. Since the sign value has already been described above, the description is omitted. Subsequently, the digital-analog converter 163 outputs a DC voltage_ and a switch selection signal according to a code value output from the analog-digital converter 162. That is, the first switch 150 is turned off while the second switch 151 is turned on to interrupt the input path of the DC voltage value while converting and outputting a code value into a fixed DC voltage_I. Output the selection signal. Accordingly, the DC voltage output from the digital-analog converter 163 is input to the voltage controlled oscillator 130 via the second switch 151. Then, the voltage controlled oscillator 130 outputs a voltage controlled oscillation signal proportional to the input DC voltage_I.

6 to 7 are block diagrams for describing an operation of a phase locked loop circuit according to another exemplary embodiment of the present invention.

6 to 7 are different in that the third loop uses the maximum frequency code value and the minimum frequency code value stored in the memory unit 164 as compared with the second loop described above.

The third loop is a loop for storing the maximum frequency code value and the minimum frequency code value in the memory unit 164.

The third loop is a case where the frequency of the input signal FIN input to the phase and frequency comparator 100 and the frequency divided and output from the counter 140 are the same. The operation of components (triangular wave generator, analog-to-digital converter, and digital-to-analog converter) for supplying me to the voltage control generator 130 is controlled in an active state.

The triangular wave generator 161 generates and outputs a triangular wave, and the analog-to-digital converter 162 is the maximum frequency of the triangular wave output from the triangular wave generator 161 and the DC voltage_added by the low pass filter 120. DC voltage_ value at the maximum DC voltage_DC_value_DC_value at the minimum frequency, that is, DC voltage_DC value_DC_value_Minimum value Compare each other as input.

The analog-digital converter 162 outputs a minimum sign value and a maximum sign value according to the comparison result. The minimum sign value is preferably a pulse count value at the same level of the input triangle wave and DC voltage_ minimum value, and the maximum sign value is a pulse at the same level of input triangle wave and DC voltage_ maximum value. It is preferable that it is a count value. See FIG. 9 for this. As shown in FIG. 9, the pulse count value is output as the minimum sign value to the point B where the triangle wave and the DC voltage_minimum value are the same level, and the triangle wave and DC voltage_max_value are the same level. The count value of the pulse is output as the maximum sign value until (C).

The output minimum and maximum sign values are stored in the memory unit 164 as described above.

At the same time, the digital-to-analog converter 163 may output the DC voltage_ or the switch selection signal according to the minimum sign value or the maximum sign value output from the analog-to-digital converter 162. That is, the first switch 150 is turned off and the second switch 151 outputs a switch selection signal for turning the first sign 150 off while converting the minimum sign value or the maximum sign value into a fixed DC voltage_na. Accordingly, the DC voltage output from the digital-to-analog converter 163 is input to the voltage controlled oscillator 130 through the second switch 151, and the voltage controlled oscillator 130 is inputted to the input DC voltage_NA. Outputs a proportional voltage controlled oscillation signal.

The fourth loop illustrated in FIG. 7 is a loop using the maximum frequency code value and the minimum frequency code value stored in the memory unit 164 in the third loop.

At the maximum frequency, the code select signal is used to read the maximum code value from the memory unit 164, and the digital-analog converter 163 switches the DC voltage according to the maximum code value read from the memory unit 164. Output the selection signal. That is, the digital-to-analog converter 163 converts the maximum code value read from the memory unit 164 into a fixed DC voltage_na and outputs the first switch 150 to turn off the second switch 151 to turn on. Outputs a switch select signal for Accordingly, the DC voltage output from the digital-to-analog converter 163 is input to the voltage controlled oscillator 130 through the second switch 151, and the voltage controlled oscillator 130 is inputted to the input DC voltage_NA. Outputs a proportional voltage controlled oscillation signal.

Also, at the minimum frequency, the code select signal is used to read the minimum code value from the memory unit 164, and the digital-to-analog converter 163 reads the DC voltage according to the minimum code value read from the memory unit 164. Outputs the switch select signal. That is, the digital-to-analog converter 163 converts the minimum code value read from the memory unit 164 into a fixed DC voltage_na while outputting the first switch 150 and turning off the second switch 151. Outputs a switch select signal for Accordingly, the DC voltage output from the digital-to-analog converter 163 is input to the voltage controlled oscillator 130 through the second switch 151, and the voltage controlled oscillator 130 is inputted to the input DC voltage_NA. Outputs a proportional voltage controlled oscillation signal.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

Therefore, the embodiments of the present invention described herein are to be considered in descriptive sense only and not for purposes of limitation, and the scope of the present invention is shown in the appended claims rather than the foregoing description, and all differences within the scope are equivalent to Should be interpreted as being included in.

1 is a block diagram showing a phase locked loop circuit according to the prior art.

2 is a block diagram illustrating a phase locked loop circuit according to an exemplary embodiment of the present invention.

3 is a block diagram illustrating a phase locked loop circuit according to another exemplary embodiment of the present invention.

4 to 5 are block diagrams for describing an operation of a phase locked loop circuit according to an exemplary embodiment of the present invention.

6 to 7 are block diagrams for describing an operation of a phase locked loop circuit according to another exemplary embodiment of the present invention.

8 is a diagram for describing an example of generating a code value for generating a fixed DC voltage in the present invention.

FIG. 9 is a diagram for describing an example of generating a maximum code value and a minimum code value for generating a fixed DC voltage at the maximum frequency and the minimum frequency in the present invention.

Claims (7)

A voltage controlled oscillator for outputting a voltage controlled oscillation signal proportional to any one of different first and second DC voltages; A counter unit which divides and outputs the voltage controlled oscillation signal outputted from the voltage controlled oscillator in phase and frequency; A phase and frequency comparison unit for comparing the phase and frequency divided by the counter with the phase and frequency of the input signal, and outputting an error signal corresponding to the phase difference and the frequency difference according to the comparison result; A charge pump unit for charging or discharging the amount of current by using a phase component and a frequency component of the error signal output from the phase and frequency comparison unit; A low pass filter unit converting an amount of current charged or discharged in the charge pump unit into the first DC voltage and outputting the first DC voltage; A DC voltage supply unit for supplying the second DC voltage to the voltage controlled oscillator while interrupting an input path to the voltage controlled oscillator for the first DC voltage; Locking to compare the phase and frequency divided by the counter unit with the phase and frequency of the input signal input to the phase and frequency comparison unit, and to control the operation of the DC voltage supply unit to an active or inactive state according to the comparison result. A phase locked loop circuit comprising a detector. The method of claim 1, wherein the locking detector, And, in the comparison result, when the phase and frequency divided by the counter and the phase and frequency of the input signal input to the phase and frequency comparison unit are the same, controlling the DC voltage supply unit to the active state. Loop circuit. The oscillator of claim 1, wherein the voltage controlled oscillator outputs a voltage controlled oscillation signal proportional to the first DC voltage output from the low pass filter when the DC voltage supply unit is in the inactive state under the control of the locking detector. Outputting a phase-locked loop circuit. The method of claim 1, wherein the DC voltage supply unit, A triangular wave generator for generating and outputting a triangular wave in the active state; An analog-to-digital converter configured to output a sign value according to a result of comparing two inputs by using the triangle wave output from the triangle wave generator and the first DC voltage converted by the low pass filter; Outputting a switch selection signal for turning on the input path to the voltage controlled oscillator for the second DC voltage while interrupting the input path to the voltage controlled oscillator, and according to the code value output from the analog-to-digital converter And a digital-to-analog converter for outputting the second DC voltage. The method of claim 4, wherein the sign value, And a count value of a pulse to a point at which the triangle wave and the first DC voltage are at the same level. The method of claim 4, wherein the DC voltage supply unit, The count value of the pulse is stored as a maximum sign value until the maximum value of the triangle wave and the first DC voltage is the same level, and the count value of the pulse is stored up to the point where the minimum value of the triangle wave and the first DC voltage is the same level. And a memory unit for storing the minimum code value. The method of claim 6, At the maximum frequency, the digital-analog converter converts the maximum code value read from the memory unit into the second DC voltage and outputs the converted DC signal. And at the minimum frequency, the digital-analog converter converts the minimum code value read from the memory unit into the second DC voltage and outputs the second DC voltage.

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