KR20110078785A

KR20110078785A - Liquid crystal display device controllable viewing angle

Info

Publication number: KR20110078785A
Application number: KR1020090135683A
Authority: KR
Inventors: 김태한; 이경언
Original assignee: 엘지디스플레이 주식회사
Priority date: 2009-12-31
Filing date: 2009-12-31
Publication date: 2011-07-07

Abstract

PURPOSE: A liquid crystal display device with a controllable viewing angle is provided to control right and left viewing angel and up and down viewing angle by dividing each pixel through a UV alignment. CONSTITUTION: A pixel region is defined by a first and a second data lines which are adjacent to each other. A first thin film transistor(TFT-1) is formed in the intersection area of the first data line and a gate line. A second thin film transistor(TFT-2) is formed in the intersection area of the second data line and a gate line. A liquid crystal display panel comprises a second pixel electrode and a common electrode which faces the first and the second pixel electrodes. A pixel voltage supplier creates pixel voltage corresponding to the selected viewing angle mode.

Description

Liquid crystal display device controllable viewing angle

The present invention relates to a liquid crystal display device, and to a liquid crystal display device capable of controlling a viewing angle according to a user's selection.

Recently, with the development of various portable electronic devices such as mobile phones, PDAs, notebook computers, the demand for light and thin flat panel display devices that can be applied to them is gradually increasing. Liquid crystal display devices (LCDs), plasma display panels (PDPs), field emission displays (FEDs), etc. are being actively researched as such flat panel displays, but due to mass production technology, ease of driving means and high quality, Liquid crystal display (LCD) is in the spotlight.

The liquid crystal display device has various display modes according to the arrangement of liquid crystal molecules. However, TN mode liquid crystal display devices are mainly used because of the advantages of easy monochrome display, fast response speed, and low driving voltage.

The basic structure of the liquid crystal display includes an array substrate on which unit pixels are arranged, a color filter substrate facing the array substrate, and a liquid crystal formed between the array substrate and the color filter substrate. Polarizers are formed around the array substrate and the color filter substrate to allow the polarized light to reach the liquid crystal. In addition, the liquid crystal is arranged twisted spirally from the array substrate to the color filter substrate.

In such a TN mode liquid crystal display, liquid crystal molecules oriented horizontally with respect to the substrate are almost perpendicular to the substrate when a voltage is applied. Therefore, there is a problem that the viewing angle is narrowed upon application of voltage due to the refractive anisotropy of the liquid crystal molecules.

In order to solve the viewing angle problem, liquid crystal display devices of various modes having wide viewing angle characteristics have recently been proposed, but among them, the liquid crystal display device of the lateral field mode (In Plane Switching Mode) has been applied to actual mass production. The IPS mode liquid crystal display device improves the viewing angle characteristic by forming a planar transverse electric field when the voltage is applied and aligning the liquid crystal molecules in a planar manner.

The IPS mode has a problem in that the response speed is slow and the aperture ratio is reduced instead of the excellent viewing angle characteristic.

In addition, the wide viewing angle may not be advantageous to the user. According to the user's selection, a flat panel display having narrow viewing angle characteristics may be required. Therefore, development of a flat panel display device that can narrow or widen the viewing angle according to a user's selection is required.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device capable of adjusting a viewing angle capable of controlling left / right viewing angles and up / down viewing angles by dividing each pixel through UV alignment.

According to an exemplary embodiment of the present invention, a liquid crystal display device having an adjustable viewing angle may include one gate line. A pixel region defined by first and second data lines crossing the one gate line and adjacent to each other, a first thin film transistor formed at an intersection of the one gate line and the first data line, and the one A second thin film transistor formed at an intersection of a gate line and the second data line, a first pixel electrode electrically connected to the first thin film transistor, and a first pixel electrode electrically connected to the first thin film transistor And a liquid crystal display panel including a second pixel electrode parallel to the horizontal direction and a common electrode facing the first and second pixel electrodes, a mode selector for selecting a viewing angle mode of the liquid crystal display panel, and the mode selector. A pixel voltage supply unit configured to generate a pixel voltage corresponding to the viewing angle mode selected by and supply the pixel voltage to the first and second data lines. The pixel electrode of any one of the first and second pixel electrodes may be patterned in a different shape in the upper and lower portions of the pixel region, and the pixel region may have a 90 ° difference in the upper and lower portions through UV alignment. Oriented and split into two domains.

According to the present invention, the liquid crystal display device having the adjustable viewing angle divides the liquid crystal positioned in each pixel through UV to be oriented at different angles, thereby driving all pixels in the IPS mode when the user selects the wide viewing angle mode. If the viewing angle mode is selected, the IPS mode and the ECB mode can be driven separately.

Hereinafter, embodiments according to the present invention will be described with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention crosses a plurality of gate lines GL1 to GL2n and a plurality of data lines DL1 to DLm, and drives the liquid crystal cell Clc at an intersection thereof. Supplying data to the liquid crystal display panel 100 having a thin film transistor TFT formed therein, a gate driver 110 for supplying scan signals to the gate lines GL1 to GL2n, and data lines DL1 to DLm. A common voltage generator for supplying a common voltage Vcom to the data driver 120, the timing controller 130 controlling the gate driver 110, the data driver 120, and the liquid crystal display panel 100. 140.

In addition, the liquid crystal display according to the present invention generates a pixel voltage corresponding to the viewing angle mode recognized by the mode selection unit 150 and the mode selection unit 150 to recognize the viewing angle mode selected by the user to the data driver ( The pixel voltage generator 170 further supplies the pixel voltage to the pixel voltage.

In the liquid crystal display panel 100, liquid crystal is formed between two glass substrates, and a plurality of gate lines GL1 to GL2n and a plurality of data lines DL1 to DLm defining a plurality of pixel areas on the lower glass substrate. It is formed to cross each other.

In this case, first and second thin film transistors TFT-1 and TFT-2 are formed in one pixel area, and the first and second thin film transistors TFT-1 and TFT-2 are respectively different from each other. It is electrically connected.

The first and second thin film transistors TFT-1 and TFT-2 formed at the intersection of the plurality of gate lines GL1 to GL2n and the plurality of data lines DL1 to DLm respectively correspond to gate lines GL1 to GL. The data from the data lines DL1 to DLm is supplied to the liquid crystal cell Clc in response to the scan signal from GL2n).

In addition, a storage capacitor Cst is formed on the lower glass substrate of the liquid crystal display panel 100 to maintain the voltage of the liquid crystal cell Clc. The storage capacitor Cst may be formed between the liquid crystal cell Clc and the front gate line, or may be formed between the liquid crystal cell Clc and a separate common line.

On the upper glass substrate of the liquid crystal display panel 100, color filters of R, G, and B colors corresponding to the pixel areas in which the first and second thin film transistors TFT-1 and TFT-2 are formed, respectively, And a black matrix covering the gate lines GL1 to GLn, the data lines DL1 to DLm, the thin film transistor TFT, and the like, and a common electrode covering all of them.

The gate driver 110 supplies a plurality of scan signals to the plurality of gate lines GL1 to GL2n in response to the gate control signal GCS from the timing controller 130. These multiple scan signals cause the multiple gate lines GL1 to GL2n to be sequentially enabled for one horizontal synchronization signal. The gate driver 110 may include a plurality of gate driver integrated circuits.

The data driver 120 generates a plurality of pixel data voltages whenever one of the gate lines GL1 to GL2n is enabled in response to the data control signals DCS from the timing controller 130. And a plurality of data lines DL1 to DLm on the liquid crystal display panel 100. The data driver 120 may include a plurality of data driver integrated circuits.

The timing controller 130 may enable data synchronization and synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown). The gate control signal GCS for controlling the gate driver 110 and the data control signal DCCS for controlling the data driver 120 are generated using the signal DE and the clock signal CLK.

In addition, the timing controller 130 arranges the image data Data input from an external system and supplies the sorted data to the data driver 120.

The common voltage generator 140 generates a common voltage Vcom, which is a DC voltage of a predetermined level, by using a power supply voltage Vdd applied from a power supply (not shown) to form a common electrode of the liquid crystal display panel 100. The common voltage Vcom is supplied.

The mode selector 150 recognizes the viewing angle mode selected by the user and provides the recognized result to the pixel voltage generator 170.

The pixel voltage generator 170 determines the viewing angle mode selected by the user according to the signal provided from the mode selection unit 150, generates a pixel voltage corresponding to the viewing angle mode, and provides the pixel voltage to the data driver 120.

For example, when the user selects the wide viewing angle mode, the pixel voltage generator 170 generates the first and second pixel voltages which are symmetrical to each other but have different polarities, and provide the same to the data driver 120. In addition, when the user selects the narrow viewing angle mode, the pixel voltage generator 170 generates the first and second pixel voltages having the same level for each frame or the first and second pixel voltages having different polarities. The data driver 120 provides this.

FIG. 2 is a circuit diagram schematically illustrating the liquid crystal display panel of FIG. 1.

1 and 2, the liquid crystal display panel 100 vertically crosses first to fourth gate lines GL1 to GL4 and perpendicular to the first to fourth gate lines GL1 to GL4. The first to third data lines DL1 to DL3 and four pixel areas A to D defined by the two signal lines are formed.

Each of the four pixel areas A to D includes first and second thin film transistors TFT-1 and TFT-2.

The first and second thin film transistors TFT-1 and TFT-2 included in the first pixel area A among the four pixel areas A to D are electrically connected to the first gate line GL1. It is controlled by a scan signal supplied to the first gate line GL1.

In this case, the first thin film transistor TFT-1 included in the first pixel area A may be electrically connected to the first data line DL1 to receive the first pixel voltage provided from the first data line DL1. The pixel electrode 160 is supplied to the pixel electrode 160. The second thin film transistor TFT-2 included in the first pixel area A is electrically connected to a second data line DL2 to receive a second pixel voltage provided from the second data line DL2. Supply to 160.

The first and second thin film transistors TFT-1 and TFT-2 included in the second pixel area B among the four pixel areas A to D are electrically connected to the second gate line GL2. It is controlled by a scan signal supplied to the second gate line GL2.

The first thin film transistor TFT-1 included in the second pixel region B is electrically connected to a second data line DL2 to receive a second pixel voltage provided from the second data line DL2. Supply to 160. The second thin film transistor TFT-2 included in the second pixel region B is electrically connected to a third data line DL3 to receive a third pixel voltage provided from the third data line DL3. Supply to 160.

The first and second thin film transistors TFT-1 and TFT-2 included in the third pixel area C among the four pixel areas A to D are electrically connected to the third gate line GL3. It is controlled by the scan signal supplied to the third gate line GL3.

The first thin film transistor TFT-1 included in the third pixel region C supplies the first pixel voltage provided from the first data line DL1 to the pixel electrode 160. The second thin film transistor TFT-2 included in the third pixel region C supplies the second pixel voltage provided from the second data line DL2 to the pixel electrode 160.

The first and second thin film transistors TFT-1 and TFT-2 included in the fourth pixel area D among the four pixel areas A to D are electrically connected to the fourth gate line GL4. It is controlled by the scan signal supplied to the fourth gate line GL4.

The first thin film transistor TFT-1 included in the fourth pixel region D supplies the second pixel voltage provided from the second data line DL2 to the pixel electrode 160. The second thin film transistor TFT-2 included in the fourth pixel region D supplies the third pixel voltage provided from the third data line DL3 to the pixel electrode 160.

As a result, the first and second thin film transistors TFT-1 and TFT-2 are formed in a zigzag shape on the liquid crystal display panel 100.

3 is a plan view illustrating the second pixel area of FIG. 2 in detail.

For convenience, the second pixel area will be described as a representative.

As shown in FIGS. 1 and 3, the second pixel area B includes the second gate line GL2 and the second and third data lines DL2 crossing the second gate line GL2 in a vertical direction. , DL3). A first thin film transistor TFT-1 is formed at an intersection of the second gate line GL2 and the second data line DL2, and the second gate line GL2 and the third data line DL3 are formed. ), A second thin film transistor TFT-2 is formed.

The first thin film transistor TFT-1 includes a first gate electrode 171 extending from the second gate line GL2 and a first semiconductor layer 172 formed on the first gate electrode 171. The first source and first drain electrodes 173 and 174 may be spaced apart from each other on the first semiconductor layer 172. The first drain electrode 174 is electrically connected to the second pixel electrode 160b through the first contact hole H1.

The second thin film transistor TFT-2 includes a second gate electrode 175 extending from the second gate line GL2, and a second semiconductor layer 176 formed on the second gate electrode 175. The second source and second drain electrodes 177 and 178 are spaced apart from each other on the second semiconductor layer 176. The second drain electrode 178 is electrically connected to the first pixel electrode 160a through the second contact hole H2.

The first and second pixel electrodes 160a and 160b constitute the pixel electrode 160 and are formed on different arrays.

The first pixel electrode 160a is formed of a metal having a transparent material and is formed over the second pixel region (B). The second pixel electrode 160b may also be formed of a metal having a transparent material. The second pixel electrode 160b may be divided into upper and lower ends in the second pixel region B and may be patterned differently. For example, the second pixel electrode 160b is patterned in a grid shape twisted from top to bottom at the upper end of the second pixel region B, and is twisted from left to right at the lower end of the second pixel region B. FIG. Patterned in true grid form.

In addition, a liquid crystal layer (not shown) formed in the second pixel region B may be aligned at 90 ° from an upper end of the second pixel region B so as to correspond to the second pixel electrode 160b. It is oriented at 0 degrees at the lower end of the two pixel region (B). UV segmentation is performed such that upper and lower portions of the liquid crystal layer formed in the second pixel region B have a 90 ° alignment difference.

As the upper and lower portions of the second pixel region B are aligned at different angles, the liquid crystal layer positioned at the upper end of the second pixel region B has a retardation only in the left and right directions, and the second pixel The liquid crystal layer positioned at the lower end of the region B has retardation only in the vertical direction.

4 is a cross-sectional view taken along the line II ′ of FIG. 3.

As shown in FIGS. 3 and 4, the liquid crystal display panel 100 includes first and second glass substrates 101 and 109. First and second gate electrodes 171 and 175 of the first and second thin film transistors TFT1 and TFT-2 are formed on the first glass substrate 101, and the first and second gate electrodes ( The gate insulating layer 102 is formed on the 171 and 175.

First and second semiconductor layers 172 and 176 are formed on the first glass substrate 101 on which the gate insulating layer 102 is formed to correspond to the first and second gate electrodes 171 and 175, respectively.

The first source electrode 173 extending from the second data line DL2 of FIG. 3 and the first drain electrode 174 spaced apart from the first source electrode 173 are disposed on the first semiconductor layer 172. Is formed. On the second semiconductor layer 176, a second source electrode 177 extending from a third data line (DL3 of FIG. 3) and a second drain electrode 178 spaced apart from the second source electrode 177 are formed. Is formed.

First and second passivation layers 103 and 104 are sequentially formed on the first source and drain electrodes 173 and 174 and the second source and drain electrodes 177 and 178. In this case, the first and second passivation layers 103 and 104 include a second contact hole (H2 of FIG. 3) exposing a portion of the second drain electrode 178.

First pixel electrodes 160a are formed on the first and second passivation layers 103 and 104 to be electrically connected to a portion of the second drain electrode 178 through the second contact hole H2. An insulating layer 105 is formed on the first glass substrate 101 on which the first pixel electrode 160a is formed. In this case, the insulating layer 105 includes a first contact hole (H1 of FIG. 3) that exposes a portion of the first drain electrode 174.

A second pixel electrode 160b is formed on the insulating layer 105 to be electrically connected to a portion of the first drain electrode 174 through the first contact hole H1.

The second glass substrate 109 is formed on a portion corresponding to the first and second thin film transistors TFT-1 and TFT-2, and a black matrix 108 formed at a portion other than the black matrix 108. The color filter 107 is included. In addition, the second glass substrate 109 includes a common electrode 106 formed on the entire surface. The common electrode 106 is supplied with the common voltage Vcom generated by the common voltage generator 140 of FIG. 1.

The first and second pixel electrodes 160a and 160b of the second pixel region B may be supplied with pixel voltages having different polarities or pixel voltages having the same polarity, depending on the viewing angle mode selected by the user. Supplied.

For example, when the user selects the wide viewing angle mode, the pixel voltage generation unit 170 of FIG. 1 may perform the second data line DL2 during the first frame, as illustrated in FIG. 5A. The first pixel voltage V_data1 of the positive polarity is supplied to the second pixel voltage, and the second pixel voltage V_data2 of the negative polarity is supplied to the third data line DL3.

Accordingly, the first pixel voltage V_data1 having a positive polarity is supplied from the second data line DL2 to the first pixel electrode 160a, and the third data line DL3 is supplied to the second pixel electrode 160b. The second pixel voltage V_data2 of negative polarity is supplied from. The first and second pixel voltages V_data1 and V_dat2 have the same level and their polarities are inverted for each frame.

At this time, the common electrode 106 is supplied with a common voltage Vcom having a constant level of 0V.

When the first and second pixel voltages V_data1 and V_data2 having different polarities are supplied to the first and second pixel electrodes 160a and 160b, between the common electrode 106 and the first pixel electrode 160a. The generated upper and lower electric fields and the upper and lower electric fields generated between the common electrode 106 and the second pixel electrode 160b cancel each other. As a result, the second pixel region B is driven like an IPS mode by a horizontal electric field generated between the first and second pixel electrodes 160a and 160b to implement a wide viewing angle mode.

For example, when the user selects the narrow viewing angle mode, the pixel voltage generation unit 170 of FIG. 1 is connected to the second and third data lines DL2 and DL3 for each frame. As shown in (b), the first and second pixel voltages V_data1 and V_data2 are supplied.

In detail, the pixel voltage generation unit 170 of FIG. 1 may include first and second polarities having different polarities as shown in FIG. 5A to the second and third data lines DL2 and DL3 during a first frame. The second pixel voltages V_data1 and V_data2 are supplied. Subsequently, during the second frame, the pixel voltage generation unit 170 of FIG. 1 is the first and second data lines DL2 and DL3 having the same polarity and level as shown in FIG. 5B. And second pixel voltages V_data1 and V_data2.

During the first frame, the first pixel voltage V_data1 having a positive polarity is supplied to the first pixel electrode 160a from the second data line DL2 as shown in FIG. 5A and the second pixel. The second pixel voltage V_data2 of negative polarity is supplied to the electrode 160b from the third data line DL3.

During the second frame, as shown in FIG. 5B, a first pixel voltage V_data1 of negative polarity is supplied to the first pixel electrode 160a from the second data line DL2. The negative pixel voltage V_data2 is supplied to the pixel electrode 160b from the third data line DL3.

When the same first and second pixel voltages V_data1 and V_data2 are supplied to the first and second pixel electrodes 160a and 160b, a horizontal electric field is formed between the first and second pixel electrodes 160a and 160b. Without forming the upper and lower electric fields between the common electrode 106 and the first pixel electrode 160a and between the common electrode 106 and the second pixel electrode 160b, the liquid crystal display panel of FIG. 100 of 1 is driven together with ECB mode.

When an upper / lower electric field is formed in the second pixel area B, an area oriented at 0 ° in the second pixel area B transmits light only in an upper / lower viewing angle direction and is oriented at 90 °. Area is transmitted only in the left / right viewing angle direction. When only the upper and lower electric fields are formed in the second pixel area B, the regions oriented at different angles may form narrow viewing angles in the up / down and left / right directions.

As described above, when the user selects the narrow viewing angle mode, the horizontal electric field and the up / down electric field are alternately formed for each frame in the second pixel area B. When the wide viewing angle mode is selected, the horizontal electric field is formed over the entire frame. .

As described above, the upper end and the lower end of the second pixel region B are oriented at different angles. Therefore, the upper end portion of the second pixel region B has a characteristic of transmitting light in the left / right viewing angle direction and not transmitting the light in the up / down viewing angle direction, as shown in FIG. . In addition, as shown in (b) of FIG. 6, the lower end portion of the second pixel region B transmits light in an up / down viewing angle direction and does not transmit light in a left / right viewing angle direction. .

Accordingly, the second pixel area B may form two domains by aligning the upper end and the lower end at different angles to implement narrow viewing angles in the up / down and left / right directions.

As described above, according to the present invention, the LCD according to the present invention can adjust the viewing angle by dividing each pixel area into an upper end and a lower end to align the liquid crystal layers formed on the divided upper and lower ends at different angles. The narrow viewing angle can be implemented in the / right direction.

Although the present invention has been described with reference to the embodiments illustrated in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

FIG. 2 is a circuit diagram schematically illustrating the liquid crystal display panel of FIG. 1. FIG.

3 is a plan view illustrating the second pixel area of FIG. 2 in detail;

4 is a cross-sectional view taken along the line II ′ of FIG. 3.

5A is a waveform diagram illustrating pixel voltages supplied to first and second pixel electrodes in a wide viewing angle mode;

5B is a waveform diagram illustrating pixel voltages supplied to first and second pixel electrodes in a narrow viewing angle mode;

FIG. 6A is a view illustrating a characteristic in which light is transmitted in a left / right viewing angle direction at an upper end of a second pixel area of FIG. 3.

FIG. 6B is a view illustrating a characteristic in which light is transmitted in an up / down viewing angle direction at a lower end of the second pixel area of FIG. 3.

Claims

With one gate line. A pixel region defined by first and second data lines crossing the one gate line and adjacent to each other, a first thin film transistor formed at an intersection of the one gate line and the first data line, and the one A second thin film transistor formed at an intersection of a gate line and the second data line, a first pixel electrode electrically connected to the first thin film transistor, and a first pixel electrode electrically connected to the first thin film transistor A liquid crystal display panel including a second pixel electrode parallel to the horizontal direction and a common electrode facing the first and second pixel electrodes;

A mode selector for selecting a viewing angle mode of the liquid crystal display panel; And

And a pixel voltage supply unit configured to generate a pixel voltage corresponding to the viewing angle mode selected by the mode selector and supply the pixel voltage to the first and second data lines.

One of the pixel electrodes of the first and second pixel electrodes is patterned in a different shape in each of the upper and lower portions of the pixel region, and the pixel region is oriented such that the upper and lower portions are 90 ° apart through UV alignment. A viewing angle adjustable liquid crystal display device, characterized in that divided into two domains.

The method according to claim 1,

And an upper end portion of the pixel region is oriented at 90 degrees through UV alignment, and a lower end portion of the pixel region is oriented at 0 degrees.

The method according to claim 1,

Any one of the first and second pixel electrodes is patterned in a grid shape twisted from top to bottom at the upper end of the pixel area, and patterned in a grid shape twisted from left to right at the lower end of the pixel area. LCD display device capable of adjusting the viewing angle.

The method according to claim 1,

When the wide viewing angle mode is selected by the mode selection unit, the pixel voltage supply unit generates first and second pixel voltages having only the same polarity and the same level, and supplies them to the first and second pixel electrodes. LCD with adjustable viewing angle.

5. The method of claim 4,

And a horizontal electric field is formed in the pixel area when the liquid crystal display panel is driven in a wide viewing angle mode.

The method according to claim 1,

When the narrow viewing angle mode is selected by the mode selection unit, the pixel voltage supply unit supplies the first and second pixel voltages having the same level and the same polarity to the first and second pixel electrodes, respectively, for one frame, And a first and second pixel voltages having the same polarity and level during the next frame, and supplying the first and second pixel voltages to the first and second pixel electrodes, respectively.

The method according to claim 6,

And the horizontal electric field and the upper and lower electric fields are alternately formed every frame when the liquid crystal display panel is driven in the narrow viewing angle mode.

The method according to claim 1,

And the common voltage is supplied to the common electrode at a constant level regardless of the viewing angle mode.