KR20100060578A - Liquid crystal panel and liquid crystal display device having the same - Google Patents

Abstract

PURPOSE: A liquid crystal panel for improving image pixel quality is provided to prevent the distortion of the data signal for a data line by controlling the width of a third data line of second and third sub pixels. CONSTITUTION: A first data line and a second data line define a first sub pixel. The second data line and the third data line define a second sub pixel which is contiguous to the first sub pixel. The third data line and fourth data line define the third sub pixel which is adjacent to the second sub pixel. The first and the second thin film transistor are respectively formed within the sub pixels between the gate line and 1-4 data lines. The width of the third data line and the second data line is different from the width of the fourth data line and the first data line.

Description

Liquid crystal panel and liquid crystal display device having the same {Liquid crystal panel and liquid crystal display device having the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal panel and a liquid crystal display device having the same to improve image quality by compensating load generated for each data line by varying line widths of data lines in one pixel area. .

In general, an apparatus for displaying an image by driving pixels arranged in an active matrix form, such as a liquid crystal display or an organic light emitting display, has been actively studied.

In particular, the liquid crystal display device is a display device in which a data signal according to image information is individually supplied to pixels arranged in an active matrix form to adjust a light transmittance of the liquid crystal layer, thereby displaying a desired image. The liquid crystal display includes a liquid crystal panel in which pixels are arranged in a matrix and a driving circuit for driving the liquid crystal panel.

A plurality of gate lines and a plurality of data lines are arranged in the liquid crystal panel, and a pixel region is positioned in an area defined by the gate lines and the data lines crossing vertically. Pixel electrodes and a common electrode for applying an electric field to each of the pixel regions are formed in the liquid crystal panel.

In this case, each of the pixel areas may be defined as four data lines DL vertically intersecting one gate line GL and the one gate line GL, and may include three subpixels.

A first subpixel among the three subpixels is defined as one gate line GL and first and second data lines DL1 and DL2 perpendicularly intersecting the one gate line GL, and a second The subpixel is defined as the second and third data lines DL2 and DL3 vertically intersecting the gate line GL and the gate line GL, and the third subpixel is defined as the gate line GL and the gate line GL. The third and fourth data lines DL3 and DL4 vertically intersect the gate line GL.

The one subpixel is defined as two data lines DL arranged adjacent to each other by vertically crossing one gate line GL and the one gate line GL. Two thin film transistors TFT and two thin film transistors TFT and the common electrode Vcom formed at the intersection between the corresponding gate line GL and the corresponding two data lines DL are included in the one subpixel. The liquid crystal cell Clc connected in between is provided.

Two thin film transistors TFTs included in each of the three subpixels are formed at intersections of the gate line GL and the data line DL, respectively, and two thin film transistors TFTs included in the first subpixel are included. Is formed at the intersection where the gate line GL and the first and second data lines DL1 and DL2 cross each other.

In addition, two thin film transistors TFTs included in the second sub-pixel are formed at an intersection where the gate line GL and the second and third data lines DL2 and DL3 cross each other. Two thin film transistors TFT included in the subpixel are formed at an intersection where the gate line GL and the third and fourth data lines DL3 and DL4 cross each other.

In the case of the second data line DL, one of the two thin film transistors TFTs included in the first and second sub-pixels, respectively, is connected. In the case of the third data line DL3, one thin film transistor TFT among two thin film transistors TFTs respectively included in the second and third sub-pixels is connected. As a result, the load generated from the second and third data lines DL2 and DL3 and the load generated from the first and fourth data lines DL1 and DL4 are different.

A load difference occurs for each data line DL in one pixel area, resulting in a delay of the data signal. As a result, the charging characteristics are different for each sub-pixel, resulting in deterioration in image quality.

The present invention provides a liquid crystal panel capable of preventing the distortion of the data signal supplied to the data line by adjusting the width of the data lines arranged in three subpixels constituting one pixel area to equalize the load generated for each data line. It is an object of the present invention to provide a liquid crystal display device having the same.

Another object of the present invention is to provide a liquid crystal panel capable of improving image quality and a liquid crystal display device having the same.

According to an exemplary embodiment of the present invention, a liquid crystal panel includes a gate line, first and second data lines perpendicular to the gate line and defining a first subpixel, and vertically intersecting the gate line. Second and third data lines defining a second sub pixel adjacent to one sub pixel, and third and fourth defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel. And first and second thin film transistors formed at intersections of the data lines and the gate lines and the first to fourth data lines in the first to third sub-pixels, respectively. The widths of the second data line positioned at the boundary of the second sub-pixel and the third data line positioned at the boundary of the second and third sub-pixels are respectively positioned at one side of the first and third sub-pixels. 4th Day It is different from the width of the turbine.

The liquid crystal panel according to the second embodiment of the present invention includes a gate line, first and second data lines perpendicular to the gate line and defining a first subpixel, and vertically intersecting the gate line. Second and third data lines defining a second sub pixel adjacent to one sub pixel, and third and fourth defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel. A data line and first and second thin film transistors respectively formed at intersections of the gate line and the first to fourth data lines in the first to third subpixels, the first subpixels The capacitance of the second thin film transistor of the first thin film transistor of the second subpixel, the first thin film transistor of the second subpixel, and the first thin film transistor of the third subpixel is equal to the first thin film transistor of the first subpixel. 3 is different from the second capacitance of the thin-film transistors of the subpixels.

The liquid crystal display according to the first exemplary embodiment of the present invention includes a gate line, first and second data lines perpendicular to the gate line and defining a first sub-pixel, and vertically intersecting the gate line. Second and third data lines defining a second sub pixel adjacent to a first sub pixel, and third and third defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel. Four data lines and first and second thin film transistors formed at intersections of the gate lines and the first to fourth data lines in the first to third sub-pixels, respectively; The widths of the second data line positioned at the boundary of the second subpixel and the third data line positioned at the boundary of the second and third subpixel are respectively located at one side of the first and third subpixels. And fourth A liquid crystal panel having a width different from that of a data line, a gate driver for supplying a scan signal to the gate line to drive the first and second thin film transistors, and a data driver for supplying a data signal to the first to fourth data lines It includes.

The liquid crystal display according to the second exemplary embodiment of the present invention includes a gate line, first and second data lines perpendicular to the gate line and defining a first subpixel, and vertically intersecting the gate line. Second and third data lines defining a second sub pixel adjacent to a first sub pixel, and third and third defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel. Four data lines and first and second thin film transistors formed at intersections of the gate lines and the first to fourth data lines in the first to third sub-pixels, respectively; The capacitances of the second thin film transistor of the pixel, the first and second thin film transistors of the second sub pixel, and the first thin film transistor of the third sub pixel are different from those of the first thin film transistor of the first sub pixel. A liquid crystal panel different from the capacitance of the second thin film transistor of the third subpixel, a gate driver supplying a scan signal to the gate line to drive the first and second thin film transistors, and the first to fourth data lines. It includes a data driver for supplying a data signal.

According to an exemplary embodiment of the present invention, a width of a second data line positioned at a boundary of first and second subpixels and a third data line positioned at a boundary of second and third subpixels among three subpixels constituting one pixel area is determined. By adjusting, the load generated for each data line arranged in the three subpixels can be made uniform, thereby preventing distortion of the data signal supplied to the data line. In addition, the present invention can improve image quality.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 102 in which liquid crystal cells Clc are arranged in a matrix form, and gate lines GL1 to liquid crystal panel 102 of the liquid crystal panel 102. A gate driver 104 for driving GLn, a data driver 106 for driving the data lines DL1 to DLm of the liquid crystal panel 102, and a gate driver 104 and a data driver 106. A timing controller 108 for controlling the drive timing is provided.

In the liquid crystal panel 102, a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm that cross the gate lines GL1 to GLn to define the pixel region P are arranged. Each of the pixel areas P includes first and third subpixels defined by one gate line GL and first to fourth data lines DL1 to DLm perpendicularly intersecting the gate line GL. SP1 to SP3). First and second thin film transistors TFT1 and TFT2 are formed at the intersections of the gate line GL and the first to fourth data lines DL1 to DL4.

The first and second thin film transistors TFT1 and TFT2 formed in the first to third sub-pixels SP1 to SP3 respectively correspond to the corresponding data lines DL in response to scan signals from the corresponding gate lines GL. The pixel data voltage to be supplied to the corresponding liquid crystal cell Clc is switched.

Details of the first to third sub-pixels SP1 to SP3 will be described later with reference to FIG. 2.

The gate driver 104 supplies a plurality of gate voltages correspondingly to the plurality of gate lines GL1 to GLn in response to the gate control signal GCS from the timing controller 108. The plurality of gate voltages enable the plurality of gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal.

The data driver 106 generates a plurality of pixel data voltages each time one of the gate lines GL1 to GLn is enabled in response to the data control signal DCS from the timing controller 108. A plurality of pixel data voltages are respectively supplied to the plurality of data lines DL1 to DLm on the liquid crystal panel 102. To this end, the data driver 106 inputs pixel data by one line from the timing controller 108 and converts the pixel data of one line into an analog pixel data voltage using a gamma voltage set. .

The timing controller 108 includes synchronization signals Vsync and Hsync supplied from an external system (for example, a graphic module of a computer system or an image demodulation module of a television reception system, not shown), and a data enable ( The gate control signal GCS controlling the gate driver 104 and the data control signal DCCS controlling the data driver 106 are generated using the DE signal and the clock signal CLK. The timing controller 108 sorts the data supplied from an external system and supplies the sorted data to the data driver 106.

FIG. 2 is a diagram illustrating in detail a pixel area P of the liquid crystal panel of FIG. 1.

As shown in FIGS. 1 and 2, each pixel area P of the liquid crystal panel 102 includes first to third sub pixels SP1 to SP3.

One pixel area P includes three subpixels SP1 to SP3, and the first subpixel SP1 includes a first gate line GL1 and first and second data lines DL1 and DL2. Is defined. The second sub pixel SP2 is defined by the first gate line GL1 and the second and third data lines DL2 and DL3, and the third sub pixel SP3 is defined by the first gate line GL1. ) And third and fourth data lines DL3 and DL4.

The first sub-pixel SP1 is formed of the first thin film transistor TFT1 and the first gate line GL1 formed at the intersection of the first gate line GL1 and the first data line DL1. A second thin film transistor TFT2 is formed at an intersection where the second data line DL2 intersects.

The second sub-pixel SP2 is formed with the first thin film transistor TFT1 and the first gate line GL1 formed at the intersection where the first gate line GL1 and the second data line DL2 cross each other. A second thin film transistor TFT2 is formed at an intersection where the third data line DL3 intersects.

The third subpixel SP3 includes a first thin film transistor TFT1 and the first gate line GL1 formed at an intersection where the first gate line GL1 and the third data line DL3 cross each other. And a second thin film transistor TFT2 formed at an intersection where the fourth data line DL4 crosses.

The first data line DL1 is electrically connected to the first thin film transistor TFT1 of the first sub pixel SP1.

The second data line DL2 is positioned at the boundary between the first and second subpixels SP1 and SP2, and the second thin film transistor TFT2 and the second subpixel of the first subpixel SP1 are disposed. The first thin film transistor TFT1 of SP2 is electrically connected to the second data line DL2.

The third data line DL3 is positioned at the boundary between the second and third subpixels SP2 and SP3, and the second thin film transistor TFT2 and the third subpixel of the second subpixel SP2 are disposed. The first thin film transistor TFT1 of SP3 is electrically connected to the third data line DL3.

The fourth data line DL4 is electrically connected to the second thin film transistor TFT2 of the third sub pixel SP3.

Widths d1 of the first and fourth data lines DL1 and DL4 and widths d2 of the second and third data lines DL2 and DL3 are different from each other. In detail, the data line DL is formed such that the width d2 of the second and third data lines DL2 and DL3 is greater than the width d1 of the first and fourth data lines DL1 and DL4. do.

As described above, the width d2 of the second and third data lines DL2 and DL3 is larger than the width d1 of the first and fourth data lines DL1 and DL4. This is because two thin film transistors TFT are connected to the three data lines DL2 and DL3, and one thin film transistor TFT is connected to the first and fourth data lines DL1 and DL4.

Since the second and third data lines DL2 and DL3 are connected to two thin film transistors TFT, a load is higher than that of the first and fourth data lines DL1 and DL4 connected to one thin film transistor TFT. It becomes bigger.

Exactly, the parasitic capacitance generated in the second and third data lines DL2 and DL3 connected to the two thin film transistors TFT may be connected to the first and fourth data lines connected to the one thin film transistor TFT. The load difference between the second and third data lines DL2 and DL3 and the first and fourth data lines DL1 and DL4 is greater than the parasitic capacitance generated in the DL1 and DL4.

The width d2 of the second and third data lines DL2 and DL3 is greater than the width d1 of the first and fourth data lines DL1 and DL4 so that the second and third data lines The load difference between the DL2 and DL3 and the first and fourth data lines DL1 and DL4 may be reduced. That is, in the liquid crystal display according to the present invention, the width of the first and fourth data lines DL1 and DL4 and the width of the second and third data lines DL2 and DL3 are formed to be asymmetric. The load difference occurring between the data lines DL arranged in P) can be reduced.

Instead of the above method of varying the width of the data line DL in order to reduce the load difference occurring between the data lines DL, the thin film transistor TFT connected to the second and third data lines DL2 and DL3. ) Is different from the capacitance of the thin film transistor connected to the first and fourth data lines DL1 and DL4.

Specifically, the method includes the capacitance of two thin film transistors TFT connected to the second and third data lines DL2 and DL3 to one of the first and fourth data lines DL1 and DL4. It is equivalent to the capacity of a thin film transistor (TFT). As a result, a load difference occurring between the second and third data lines DL2 and DL3 and the first and fourth data lines DL1 and DL4 may be reduced.

As the width d2 of the second and third data lines DL2 and DL3 increases, the width of the black matrix BM surrounding the first to fourth data lines DL1 to DL4 is also shown in FIG. 3. As will be increased. The liquid crystal display according to the present invention increases the width of the black matrix BM compared to the conventional liquid crystal display device so as to sufficiently cover the second and third data lines DL2 and DL3 which have been increased in width.

4 is a graph illustrating a response speed of first to fourth data lines arranged in one pixel area.

As shown in FIG. 4, the second and third data lines DL2 and DL3 having increased widths have faster response speeds than the first and fourth data lines DL1 and DL4. Due to the rapid response speed of the second and third data lines DL2 and DL3, the first and fourth data lines DL1 and DL4 may be generated between the second and third data lines DL2 and DL3. The load difference can be compensated for. Therefore, the load difference between the first to fourth data lines DL1 to DL4 arranged in one pixel area P may be reduced to reduce distortion of the data signal supplied to the first to fourth data lines DL1 to DL4. Can be.

As a result, the liquid crystal display according to the present invention may improve image quality by reducing distortion of the data signal supplied to the data line DL.

1 is a schematic view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating in detail a pixel area P of the liquid crystal panel of FIG. 1.

3 is a diagram illustrating a black matrix formed on the liquid crystal panel of FIG. 2;

Claims (9)

Gate line; First and second data lines perpendicular to the gate line and defining a first sub pixel; Second and third data lines that cross the gate line and define a second sub pixel adjacent to the first sub pixel; Third and fourth data lines that cross the gate line and define a third sub pixel adjacent to the second sub pixel; And first and second thin film transistors respectively formed at intersections of the gate lines and the first to fourth data lines in the first to third sub-pixels. Widths of the second data line positioned at the boundary of the first and second subpixels and the third data line positioned at the boundary of the second and third subpixels are on one side of the first and third subpixels, respectively. And a width different from the width of the first and fourth data lines positioned. According to claim 1, And the first to third sub pixels define one pixel. According to claim 1, The width of the second and third data lines is greater than the width of the first and fourth data lines. According to claim 1, The second data line is electrically connected to a second thin film transistor provided in the first sub pixel and a first thin film transistor provided in the second sub pixel, and the third data line is connected to the second thin film transistor of the second sub pixel. And a first thin film transistor of the second thin film transistor and the third subpixel. Gate line; First and second data lines perpendicular to the gate line and defining a first sub pixel; Second and third data lines that cross the gate line and define a second sub pixel adjacent to the first sub pixel; Third and fourth data lines that cross the gate line and define a third sub pixel adjacent to the second sub pixel; And first and second thin film transistors respectively formed at intersections of the gate lines and the first to fourth data lines in the first to third sub-pixels. The capacitances of the second thin film transistor of the first sub pixel, the first and second thin film transistors of the second sub pixel, and the first thin film transistor of the third sub pixel are equal to the first thin film transistor of the first sub pixel and the first thin film transistor of the first sub pixel. And a capacitance different from that of the second thin film transistor of the third subpixel. According to claim 1, And the first to third sub pixels define one pixel. According to claim 1, The second thin film transistor of the first sub pixel and the first thin film transistor of the second sub pixel are electrically connected to the second data line, and the second thin film transistor of the second sub pixel and the third sub pixel. And the first thin film transistor is electrically connected to the third data line. Define a gate line, first and second data lines that intersect the gate line and define a first subpixel, and a second subpixel that intersect the gate line and adjoin the first sub pixel. Second and third data lines, third and fourth data lines defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel, and the first to third sub lines. Second data including first and second thin film transistors respectively formed at intersections of the gate lines and the first to fourth data lines in a pixel, and located at a boundary between the first and second subpixels; A liquid crystal panel having a width different from a width of the first and fourth data lines positioned at one side of the first and third sub pixels, respectively, the width of the third data line positioned at a boundary between the line and the second and third sub pixels; A gate driver supplying a scan signal to the gate line to drive the first and second thin film transistors; And And a data driver for supplying a data signal to the first to fourth data lines. Define a gate line, first and second data lines that intersect the gate line and define a first subpixel, and a second subpixel that intersect the gate line and adjoin the first sub pixel. Second and third data lines, third and fourth data lines defining a third sub pixel vertically crossing the gate line and adjacent to the second sub pixel, and the first to third sub pixels. First and second thin film transistors formed at intersections of the gate lines and the first to fourth data lines, respectively, wherein the second thin film transistors of the first sub pixel and the second sub pixel Capacities of the first and second thin film transistors and the first thin film transistors of the third subpixel are used for the first thin film transistors of the first subpixel and the second thin film transistors of the third subpixel. It is different from the liquid crystal panel; A gate driver supplying a scan signal to the gate line to drive the first and second thin film transistors; And And a data driver for supplying a data signal to the first to fourth data lines.

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