KR20080001052A - Liquid crystal display device and method driving for the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a driving method thereof are provided to enhance image quality by driving a liquid crystal panel using a vertical 3-dot inversion scheme. An LCD(Liquid Crystal Display) device includes a liquid crystal panel(102) and gate and data drivers(104,106). The liquid crystal panel includes pixel areas having sub-pixels in a vertical direction. The gate driver drives sequentially the gate lines of the liquid crystal panel. The data driver inverts the polarity of data voltage, which is supplied to the data lines of the liquid crystal panel, per three gate lines. The liquid crystal panel is driven by a vertical 3-dot inversion scheme.

Description

Liquid crystal display device and method driving for the same

1A and 1B show a conventional vertical two dot inversion scheme.

2 is a view showing a liquid crystal panel of a conventional liquid crystal display device.

3 is a view showing a liquid crystal display device according to the present invention.

4A and 4B illustrate a vertical three dot inversion scheme according to the present invention.

FIG. 5 is a diagram illustrating driving voltages supplied to a first pixel area of the liquid crystal panel of FIG. 3 for each frame; FIG.

FIG. 6 is a diagram illustrating driving voltages supplied to a second pixel area of the liquid crystal panel of FIG. 3 for each frame; FIG.

FIG. 7 is a diagram illustrating driving voltages supplied to a third pixel area of the liquid crystal panel of FIG. 3 for each frame; FIG.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

106: data driver 108: timing controller

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving image quality.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

The liquid crystal display device includes a liquid crystal panel for displaying a predetermined image and a driver for driving the liquid crystal panel.

The liquid crystal panel is composed of two glass substrates and a liquid crystal layer formed between the two glass substrates. The liquid crystal layer formed between the two glass substrates causes deterioration of characteristics when the DC voltage is applied for a long time. In order to prevent this, the liquid crystal layer is periodically driven to change the polarity of the applied voltage, which is called an inversion driving method.

The inversion driving methods include frame inversion, line inversion, and dot inversion driving methods. The dot inversion driving method includes a one dot inversion driving method and a vertical two dot inversion driving method.

In particular, the vertical two-dot inversion driving method of the dot inversion driving method is as shown in FIGS. 1A and 1B, and the polarity of the pixel signal in the odd and even frames is the same as the conventional dot inversion method. While changing in dots, it is driven to change polarity in units of two dots in the vertical direction.

2 is a view showing a liquid crystal panel of a conventional liquid crystal display device.

As shown in FIG. 2, in the conventional liquid crystal panel 2, a plurality of gate lines GL1 to GL4 and data lines DL1 to DL4 defining a plurality of pixel areas are arranged.

In the liquid crystal panel 2, the first pixel area P1 is defined as a first data line DL1 and second to fourth gate lines GL2 to GL4 intersected with the first data line DL1. . That is, the first subpixel of the first pixel region P1 is defined by the first data line DL1 and the second gate line GL2, and the second subpixel is defined by the first data line DL1. It is defined as a third gate line GL3, and the third subpixel is defined as the first data line GL1 and the fourth gate line GL4.

Thin film transistors (TFTs) and first to third pixel electrodes 12a to 12c are formed in the first to third subpixels, respectively.

The second pixel area P2 of the liquid crystal panel 2 is defined by second to fourth gate lines GL2 to GL4 arranged to intersect the second data line DL2 and the second data line DL2. . The third pixel area P3 of the liquid crystal panel 2 is defined as a third data line DL3 and second to fourth gate lines GL2 to GL4 intersecting with the third data line DL3. .

Since the liquid crystal panel 2 is driven in a vertical two-dot inversion scheme, positive data voltages are supplied to the first and second subpixels of the first pixel region P1, and the third subpixel is provided. The pixel is supplied with a negative data voltage. The data voltage of negative polarity (−) is supplied to the first and second subpixels of the second pixel region P2, and the data voltage of positive polarity (+) is supplied to the third subpixel. The third pixel region P3 is the same as the first pixel region P1.

The liquid crystal panel 2 has a storage on gate method, and the pixel electrode forms a front gate line and a storage capacitor Cst.

The first pixel electrodes 12a, 12d, and 12g of the first to third pixel areas P1 to P3 form a first gate line GL1 and a storage capacitor Cst, and form the first to third pixel areas. Second pixel electrodes 12b, 12e, and 12h of P1 to P3 form a second gate line GL2 and a storage capacitor Cst. The third pixel electrodes 12c, 12f, and 12i of the first to third pixel regions P1 to P3 form a third gate line GL3 and a storage capacitor Cst.

The positive data voltages supplied to the first and second pixel electrodes 12a and 12b of the first pixel region P1 are stored in the respective storage capacitors Cst.

In the next frame, a negative data voltage is supplied to the first and second pixel electrodes 12a and 12b of the first pixel region P1, and the positive polarity stored in the storage capacitor Cst is stored in the previous frame. The positive data voltage is changed to the negative data voltage.

The first pixel electrode 12a forms a first gate line GL1 and a storage capacitor Cst, and the positive data voltage charged in the storage capacitor Cst is negative in the next frame. During the change to the data voltage of-), the gate low voltage VGL supplied to the first gate line GL1 is affected.

The second pixel electrode 12b forms the second gate line GL2 and the storage capacitor Cst, and the positive data voltage charged in the storage capacitor Cst is in the next frame. During the change to the negative data voltage, the gate low voltage VGL supplied to the second gate line GL2 is affected.

The third pixel electrode 12c forms the third gate line GL3 and the storage capacitor Cst, and the negative data voltage charged in the storage capacitor Cst is positive in the next frame. During the change to the positive data voltage, the gate low voltage VGL supplied to the third gate line GL3 is affected.

The gate low voltage VGL supplied to the first and second gate lines GL1 and GL2 is followed by a positive data voltage to the first and second pixel electrodes 12a and 12b during the previous frame. Affected during the transition to a negative data voltage in the frame.

On the contrary, the gate low voltage VGL supplied to the third gate line GL3 has the negative data voltage of the negative pixel to the third pixel electrode 12c during the previous frame. Affected by the change of data voltage.

The degree to which the gate low voltage VGL supplied to the first and second gate lines GL1 and GL2 are affected and the degree to which the gate low voltage VGL supplied to the third gate line GL3 are affected. Are different from each other. The data voltage charged in the storage capacitors Cst of the first to third subpixels constituting the first pixel region P1 may be affected.

As a result, the data voltage charged in the pixel region of the liquid crystal panel 2 including the first pixel region P1 is affected, resulting in problems such as deterioration of image quality.

An object of the present invention is to provide a liquid crystal display device and a driving method thereof capable of improving image quality.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel including a pixel region in which three subpixels are formed in a vertical direction, a gate driver sequentially driving a gate line of the liquid crystal panel, And a data driver for supplying the polarity of the data voltage supplied to the data line to be inverted every three gate lines.

A driving method of a liquid crystal display device according to the present invention for achieving the above object is a method of driving a liquid crystal display device comprising a liquid crystal panel including a pixel region of the sub-pixels in the vertical direction, the gate line of the liquid crystal panel; And supplying a scan signal and supplying a data voltage whose polarity is inverted every three gate lines to the data lines of the liquid crystal panel.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

3 is a view showing a liquid crystal display according to the present invention.

As shown in FIG. 3, the liquid crystal display according to the present invention includes a liquid crystal panel 102 including two glass substrates and a liquid crystal layer formed between the two glass substrates to display a predetermined image, and the liquid crystal panel ( A gate driver 104 and a data driver 106 for driving 102 and a timing controller 108 for controlling the gate driver 104 and the data driver 106 are included.

The liquid crystal panel 102 includes a plurality of gate lines GL0 to GLn and data lines DL1 to DLm defining a plurality of pixel regions, and a thin film transistor TFT and a thin film transistor TFT at the intersection thereof. And a pixel electrode (not shown) electrically connected through the contact hole.

As mentioned above, the liquid crystal panel 102 is composed of two glass substrates and a liquid crystal layer formed between the two glass substrates. For example, the liquid crystal molecules of the liquid crystal layer are displaced by a potential difference between a data voltage applied to a first substrate and a common voltage applied to a second substrate of the two glass substrates.

The liquid crystal panel 102 has a storage on gate method, and the pixel electrode forms a storage capacitor Cst together with the front gate line. The liquid crystal panel 102 has a structure as shown in FIG. 2.

In this case, as shown in FIGS. 4A and 4B, the polarity of the pixel signal in the odd and even frames is changed in the unit of dots in the horizontal direction in the vertical direction, as in the conventional dot inversion method. It is driven to change the polarity in units of 3 dots.

The gate driver 104 scans a plurality of gate lines GL1 to GLn, that is, a gate high voltage VGH and a gate low voltage VGL according to a gate control signal supplied from the timing controller 108. Supply sequentially. The gate lines GL1 to GLn are electrically connected to the thin film transistor TFT.

Therefore, a gate high voltage VGH and a gate low voltage VGL are supplied to the thin film transistor TFT through the plurality of gate lines GL1 to GLn.

The thin film transistor TFT is turned on when a gate high voltage VGH is supplied from the gate lines GL1 to GLn, and a gate low voltage from the gate lines GL1 to GLn. VGL) is turned off when supplied.

The data driver 106 converts the R, G, and B data signals supplied from the timing controller 108 into analog voltages according to the data control signals supplied from the timing controller 108 to convert the plurality of data lines DL1. ~ DLm).

The timing controller 108 uses the gate driver 104 and the data driver (Vsync / Hsync) and a predetermined clock signal and data enable (DE) signal supplied from a system (not shown). A gate control signal and a data control signal for controlling 106 are generated.

In addition, the timing controller 108 arranges the R, G, and B data signals supplied from the system by R, G, and B, and the aligned R, G, and B data signals are supplied to the data driver 106. .

The timing controller 108 generates a polarity signal and supplies it to the data driver 106.

The timing controller 108 generates a polar signal according to the inversion method of the liquid crystal panel 102 and supplies it to the data driver 106. The data driver 106 receives the polarity signal and supplies a data voltage having polarity to the plurality of data lines DL1 to DLm.

Since the liquid crystal panel 102 is driven in a vertical three dot inversion scheme, the timing controller 108 generates a polarity signal to conform to the vertical three dot inversion scheme in the liquid crystal panel 102 so that the data driver 106 is used. ).

5 is a diagram illustrating a driving voltage supplied to a first pixel area of the liquid crystal panel of FIG. 3 for each frame.

During the first frame, a positive data voltage is supplied to the first pixel area (P1 of FIG. 2) of the liquid crystal panel 102. As described above, the first pixel area P1 includes first to third subpixels, and the first subpixels intersect the first data line DL1 and the first data line DL1. Defined as the second gate line GL2.

The second subpixel is defined as a third gate line GL3 intersecting the first data line DL1 and the first data line DL1, and the third subpixel is a first data line DL1. ) And a fourth gate line GL4 intersected with the first data line DL1.

A first pixel electrode 12a of FIG. 1 is formed in the first subpixel, a second pixel electrode 12b is formed in the second subpixel, and a third pixel electrode 12c is formed in the third subpixel. It is.

When the gate high voltage VGH-2 is supplied to the second gate line GL2 during the first frame, the data voltage Vd1 of positive polarity (+) is supplied to the first pixel electrode 12a. As a result, the first storage capacitor formed by the first pixel electrode 12a and the first gate line GL1 is lower than the positive data voltage Vd1 of the first pixel capacitor Vp1. Is charged.

After the gate high voltage VGH-2 is supplied to the second gate line GL2, the gate high voltage VGH-3 is supplied to the third gate line GL3, and the second pixel electrode 12b is provided. The positive data voltage Vd2 is supplied to the. At the same time, the gate low voltage VGL-2 is supplied to the second gate line GL2.

As a result, the second storage capacitor formed by the second pixel electrode 12b and the second gate line GL2 has a second pixel voltage Vp2 lower than the positive data voltage Vd2. Is charged.

After the gate high voltage VGH-3 is supplied to the third gate line GL3, the gate high voltage VGH-4 is supplied to the fourth gate line GL4, and the third pixel electrode 12c is provided. Is supplied with a positive data voltage Vd3. At the same time, a gate low voltage VGL-3 is supplied to the third gate line GL3.

As a result, the third storage capacitor formed by the third pixel electrode 12c and the third gate line GL3 has a third pixel voltage Vp3 lower than the positive data voltage Vd3. Is charged.

As a result, the data voltages Vd1 to Vd3 of positive polarity (+) are supplied to the first to third pixel electrodes 12a to 12c of the first pixel region P1 during the first frame.

Subsequently, when the gate high voltage VGH is supplied to the second gate line GL2 to the second frame, which is the next frame, a negative data voltage Vd1 is supplied to the first pixel electrode 12a. . As a result, the first storage capacitor is supplied with a first pixel voltage Vp1 that is lower than the negative data voltage Vd1.

During the first frame, the data voltage Vd1 of positive polarity is supplied to the first storage capacitor, and the data voltage Vd1 of negative polarity is supplied to the first storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the first storage capacitor charged with the positive data voltage Vd1 stores the data voltage Vd1 of the positive polarity (+) charged with the negative polarity (−) in the second frame. The data voltage Vd1 changes to charge.

In this process, the gate low voltage VGL-1 supplied to the first gate line GL1 is affected.

After the gate high voltage VGH is supplied to the second gate line GL2, the gate high voltage VGH-3 is supplied to the third gate line GL3, and the second pixel electrode 12b is negatively provided. The data voltage Vd2 of polarity (−) is supplied. At the same time, the gate low voltage VGL-2 is supplied to the second gate line GL2.

As a result, the second storage capacitor is supplied with a second pixel voltage Vp2 that is lower than the negative data voltage Vd2.

During the first frame, the data voltage Vd2 of positive polarity is supplied to the second storage capacitor, and the data voltage Vd2 of negative polarity is supplied to the second storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the second storage capacitor charged with the positive data voltage (Vd2) may store the charged data voltage (Vd2) of the negative polarity (−) in the second frame. The data voltage Vd2 is changed to charge.

In this process, the gate low voltage VGL-2 supplied to the second gate line GL2 is affected.

After the gate high voltage VGH is supplied to the third gate line GL3, the gate high voltage VGH-4 is supplied to the fourth gate line GL4, and the gate high voltage VGH-4 is supplied to the third pixel electrode 12c. The data voltage Vd3 of polarity (−) is supplied. At the same time, a gate low voltage VGL-3 is supplied to the third gate line GL3.

As a result, the third storage capacitor is supplied with a third pixel voltage Vp3 that is lower than the negative data voltage Vd3.

During the first frame, the data voltage Vd3 of positive polarity is supplied to the third storage capacitor, and the data voltage Vd3 of negative polarity is supplied to the third storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the third storage capacitor charged with the positive data voltage Vd3 stores the data voltage Vd3 of the positive polarity (+) charged in the second frame with the negative polarity (−). The data voltage Vd3 changes to charge.

In this process, the gate low voltage VGL-3 supplied to the third gate line GL3 is affected.

As a result, the gate low voltages VGL-1 to VGL-3 supplied to the first to third gate lines GL1 to GL3 forming the first to third storage capacitors of the first pixel region P1 are the same. Will be affected.

By supplying data voltages having the same polarity to the first to third pixel electrodes 12a to 12c of the first pixel region P1, the first to third pixel electrodes 12a to 12c are independent of the frame. The gate low voltages VGL-1 to VGL-3 supplied to the first to third gate lines GL1 to GL3 together to form the storage capacitor are affected in the same manner.

6 is a diagram illustrating a driving voltage supplied to a second pixel area of the liquid crystal panel of FIG. 3 for each frame.

As shown in FIG. 6, a negative data voltage is supplied to the second pixel region (P2 of FIG. 2) of the liquid crystal panel 102 during the first frame. As described above, the second pixel area P2 includes first to third subpixels, and the first subpixels intersect the second data line DL2 and the second data line DL2. Defined as the second gate line GL2.

The second subpixel is defined as a second data line DL2 and a third gate line GL3 intersected with the second data line DL2, and the third subpixel is a second data line DL2. And a fourth gate line GL4 arranged to intersect with the second data line DL2.

A first pixel electrode (12d of FIG. 1) is formed in the first subpixel, a second pixel electrode 12e is formed in the second subpixel, and a third pixel electrode 12f is formed in the third subpixel. It is.

When the gate high voltage VGH-2 is supplied to the second gate line GL2 during the first frame, the data voltage Vd4 of negative polarity (−) is supplied to the first pixel electrode 12d. As a result, a fourth pixel voltage Vp4 that is lower than the negative data voltage Vd4 is formed in the first storage capacitor formed by the first pixel electrode 12d and the first gate line GL1. Is charged.

After the gate high voltage VGH-2 is supplied to the second gate line GL2, the gate high voltage VGH-3 is supplied to the third gate line GL3, and the second pixel electrode 12e is provided. The negative data voltage Vd5 is supplied to the. At the same time, the gate low voltage VGL-2 is supplied to the second gate line GL2.

As a result, the second storage capacitor formed by the second pixel electrode 12e and the second gate line GL2 has a fifth pixel voltage Vp5 that is lower than the negative data voltage Vd5. Is charged.

After the gate high voltage VGH-3 is supplied to the third gate line GL3, the gate high voltage VGH-4 is supplied to the fourth gate line GL4, and the third pixel electrode 12f is provided. The negative data voltage Vd6 is supplied to the. At the same time, a gate low voltage VGL-3 is supplied to the third gate line GL3.

As a result, the third storage capacitor formed by the third pixel electrode 12f and the third gate line GL3 has a sixth pixel voltage Vp6 lower than the data voltage Vd6 of the negative polarity (-). ) Is charged.

As a result, the data voltages Vd4 to Vd6 of negative polarity (−) are supplied to the first to third pixel electrodes 12d to 12f of the second pixel region P2 during the first frame.

Subsequently, when the gate high voltage VGH is supplied to the second gate line GL2 to the second frame, which is the next frame, the positive data voltage Vd4 is supplied to the first pixel electrode 12d. . Thus, the first storage capacitor is supplied with a fourth pixel voltage Vp4 that is lower than the positive data voltage Vd4.

During the first frame, a negative data voltage Vd4 is supplied to the first storage capacitor, and a positive data voltage Vd4 is supplied to the first storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the first storage capacitor charged with the negative data voltage Vd4 stores the charged data voltage Vd4 of the negative polarity in the second frame. The data voltage Vd4 is changed to charge.

In this process, the gate low voltage VGL-1 supplied to the first gate line GL1 is affected.

After the gate high voltage VGH is supplied to the second gate line GL2, the gate high voltage VGH-3 is supplied to the third gate line GL3, and a positive voltage is applied to the second pixel electrode 12e. The data voltage Vd5 of polarity (+) is supplied. At the same time, the gate low voltage VGL-2 is supplied to the second gate line GL2.

As a result, the second storage capacitor is supplied with a fifth pixel voltage Vp5 that is lower than the positive data voltage Vd5.

During the first frame, the data voltage Vd5 of negative polarity is supplied to the second storage capacitor, and the data voltage Vd5 of positive polarity is supplied to the second storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the second storage capacitor charged with the negative data voltage Vd5 stores the charged data voltage Vd5 of the negative polarity in the second frame. The data voltage Vd5 is changed to charge.

In this process, the gate low voltage VGL-2 supplied to the second gate line GL2 is affected.

After the gate high voltage VGH is supplied to the third gate line GL3, the gate high voltage VGH-4 is supplied to the fourth gate line GL4, and positive is applied to the third pixel electrode 12f. The data voltage Vd6 of polarity (+) is supplied. At the same time, a gate low voltage VGL-3 is supplied to the third gate line GL3.

As a result, the third storage capacitor is supplied with a sixth pixel voltage Vp6 that is lower than the positive data voltage Vd6.

During the first frame, a negative data voltage Vd6 is supplied to the third storage capacitor, and a positive data voltage Vd6 is supplied to the third storage capacitor in a second frame, which is the next frame. Supplied.

In the first frame, the third storage capacitor charged with the negative data voltage Vd6 stores the charged data voltage Vd6 of the negative polarity in the second frame with the positive polarity (+). The data voltage Vd6 is changed to to be charged.

In this process, the gate low voltage VGL-3 supplied to the third gate line GL3 is affected.

As a result, the gate low voltages VGL-1 to VGL-3 that are supplied to the first to third gate lines GL1 to GL3 that form the first to third storage capacitors of the second pixel region P2 are the same. Will be affected.

By supplying a data voltage having the same polarity to the first to third pixel electrodes 12d to 12f of the second pixel region P2, the first to third pixel electrodes 12d to 12f are independent of the frame. The gate low voltages VGL-1 to VGL-3 supplied to the first to third gate lines GL1 to GL3 together to form the storage capacitor are affected in the same manner.

FIG. 7 is a diagram illustrating driving voltages supplied to a third pixel area of the liquid crystal panel of FIG. 3 for each frame.

As illustrated in FIG. 7, a positive data voltage is supplied to the third pixel region (P3 of FIG. 2) of the liquid crystal panel 102 during the first frame. As described above, the third pixel area P3 includes first to third subpixels, and the first subpixels are arranged to intersect with the third data line DL3 and the third data line DL3. Defined as the second gate line GL2.

The second subpixel is defined as the third data line DL3 and the third gate line GL3 intersected with the third data line DL3, and the third subpixel is the third data line DL3. And a fourth gate line GL4 arranged to intersect with the third data line DL3.

The third pixel region P3 is the same as the first pixel region P1 described above.

As a result, the gate low voltages VGL-1 to VGL-3 supplied to the first to third gate lines GL1 to GL3 forming the first to third storage capacitors of the third pixel region P3 are the same. Will be affected.

By supplying a data voltage having the same polarity to the first to third pixel electrodes 12g to 12i of the third pixel region P3, the first to third pixel electrodes 12g to 12i are independent of the frame. The gate low voltages VGL-1 to VGL-3 supplied to the first to third gate lines GL1 to GL3 together to form the storage capacitor are affected in the same manner.

As mentioned above, the liquid crystal display according to the present invention can improve the image quality by reducing the influence on the gate low voltage supplied to the gate line of the liquid crystal panel by driving the liquid crystal panel in a vertical 3-dot inversion method have.

As described above, the liquid crystal display according to the present invention drives the liquid crystal panel forming the front gate line and the storage capacitor in a vertical three dot inversion manner, thereby affecting the gate low voltage supplied to the front gate line. Can be reduced.

In addition, the liquid crystal display according to the present invention can improve the image quality by minimizing the influence on the gate low voltage supplied to the front gate line.

Although the present invention has been described with reference to the embodiments, those skilled in the art may variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. You will understand.

Claims (8)

A liquid crystal panel including a pixel region in which subpixels are formed in a vertical direction; A gate driver for sequentially driving gate lines of the liquid crystal panel; And a data driver for supplying the polarity of the data voltage supplied to the data line of the liquid crystal panel to be inverted every three gate lines. The method of claim 1, And the polarity of the data voltage is inverted from frame to frame. The method of claim 1, And the liquid crystal panel is driven in a vertical 3-dot inversion method. The method of claim 1, And the polarity of the data voltage is one dot inverted in the horizontal direction of the pixel region. In the driving method of a liquid crystal display device comprising a liquid crystal panel comprising a pixel area of the sub pixels in the vertical direction, Supplying a scan signal to a gate line of the liquid crystal panel; And supplying a data voltage whose polarity is inverted every three gate lines to the data lines of the liquid crystal panel. The method of claim 5, The polarity of the data voltage is inverted for each frame, the driving method of the liquid crystal display device. The method of claim 5, And the liquid crystal panel is driven in a vertical 3-dot inversion method. The method of claim 5, And the polarity of the data voltage is inverted by one dot in the horizontal direction of the pixel region.

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