KR20110075922A - Method manufacturing of semiconductor device - Google Patents

Method manufacturing of semiconductor device Download PDF

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Publication number
KR20110075922A
KR20110075922A KR1020090132495A KR20090132495A KR20110075922A KR 20110075922 A KR20110075922 A KR 20110075922A KR 1020090132495 A KR1020090132495 A KR 1020090132495A KR 20090132495 A KR20090132495 A KR 20090132495A KR 20110075922 A KR20110075922 A KR 20110075922A
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South Korea
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film
semiconductor device
trench
capping layer
capping
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KR1020090132495A
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Korean (ko)
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이민형
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주식회사 동부하이텍
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Priority to KR1020090132495A priority Critical patent/KR20110075922A/en
Publication of KR20110075922A publication Critical patent/KR20110075922A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent diffusion of a barrier film and a copper line during a following process, by forming a second capping layer on both walls of a trench. CONSTITUTION: A first capping layer(14) and a second interlayer insulation film are formed on a first interlayer insulation film. The first interlayer insulation film has a bottom metal line. A trench is formed on the second interlayer insulation film. The trench exposes a part of the first capping layer. The exposed first capping layer is removed through a re-sputtering process. A barrier metal film(24) is formed on the whole surface including the first capping layer. A copper line(30) is formed by burying the trench.

Description

반도체 소자의 제조방법{Method Manufacturing of Semiconductor Device} Manufacturing method of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 금속배선과 절연막 간의 접착력을 증가시킬 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can increase the adhesion between the metal wiring and the insulating film.

일반적으로, 반도체 소자의 금속배선으로 널리 사용하는 금속으로 알루미늄(Al), 알루미늄 합금 및 텅스텐(W) 등이 있다. Generally, metals widely used as metal wirings of semiconductor devices include aluminum (Al), aluminum alloys, and tungsten (W).

그러나, 이러한 금속들은 반도체 소자가 고집적화됨에 따라 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. However, these metals are no longer applicable to ultra-high density semiconductor devices due to the low melting point and high resistivity as semiconductor devices are highly integrated.

따라서, 금속배선의 대체 재료에 대한 개발 필요성이 대두되고 있는 실정이다. 대체 재료로 전도성이 우수한 물질인 구리(Cu), 금(Au), 은(Ag), 코발트(Co), 크롬(Cr), 니켈(Ni) 등이 있으며, 이러한 물질들 중 비저항이 작고, 일렉트로 마이그레이션(electro migration ; EM)과 스트레스 마이그레이션(stress migration; SM) 등의 신뢰성이 우수하며, 생산원가가 저렴한 구리 및 구리 합금이 널리 적용되고 있는 추세이다.Therefore, there is a need for development of alternative materials for metal wiring. Alternative materials include copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr) and nickel (Ni), which are highly conductive materials. Copper and copper alloys with high reliability and low production cost, such as electro migration (EM) and stress migration (SM), are widely applied.

이러한 구리배선은 알루미늄 배선과 달리 다마신(damascene) 공정을 이용하여 층간절연막 패턴을 형성하고 전기도금(ECP) 등의 공정을 거쳐 형성한다. Unlike the aluminum wiring, the copper wiring is formed through a process such as electroplating (ECP) by forming an interlayer insulating film pattern using a damascene process.

이와 같은 구리 배선을 이용한 다마신 배선에서 신뢰성을 확보하기 위해서 금속배선과 산화막으로 형성되는 층간절연막 간의 접착력을 증가시키는 연구가 요구되고 있다. In order to secure reliability in such damascene wiring using copper wiring, research is required to increase the adhesion between the metal wiring and the interlayer insulating film formed of the oxide film.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 금속배선과 절연막 간의 접착력을 증가시킬 수 있는 반도체 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can increase the adhesion between the metal wiring and the insulating film.

본 발명에 따른 반도체 소자의 제조방법은 반도체 기판 상에 형성되며, 하부 금속배선을 갖는 제 1 층간 절연막상에 제 1 캡핑막과 제 2 층간 절연막을 차례로 형성하는 단계; 상기 제 2 층간 절연막에 상기 제 1 캡핑막의 일부분을 노출시키는 트렌치를 형성하는 단계; 상기 노출된 제 1 캡핑막을 리스퍼터링(Re-Sputtering) 공정을 통해 선택적으로 제거하는 단계; 상기 제 1 캡핑막을 포함한 전표면상에 배리어 금속막을 형성하는 단계; 상기 트렌치를 매립하여 구리배선을 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a semiconductor device according to the present invention includes forming a first capping film and a second interlayer insulating film on a first interlayer insulating film formed on a semiconductor substrate and having a lower metal wiring; Forming a trench in the second interlayer dielectric to expose a portion of the first capping layer; Selectively removing the exposed first capping layer through a re-sputtering process; Forming a barrier metal film on the entire surface including the first capping film; Embedding the trench to form a copper wiring.

이상에서 설명한 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 트렌치의 양벽면에 제 2 캡핑막을 형성함으로써 후속공정에서 형성될 배리어 금속막과 함께 구리 배선의 확산을 이중으로 방지할 수 있다. 또한, 배리어 금속막이 증착되기 어려운 트렌치의 측면에서 구리 배선과 배리어 금속막 간의 접착력을 증가시킬 수 있다. 또한, 일반적인 반도체 소자의 제조방법에서 하부 금속 배선 상에 제 1 캡핑막을 제거할 시 발생하는 부산물을 원천적으로 방지할 수 있어, 구리 배선과 제 2 층간 절연막 간의 접착력을 증가시킬 수 있다. As described above, in the method of manufacturing the semiconductor device according to the present invention, by forming the second capping film on both sidewalls of the trench, the diffusion of the copper wiring together with the barrier metal film to be formed in the subsequent step can be prevented. In addition, it is possible to increase the adhesion between the copper wiring and the barrier metal film on the side of the trench where the barrier metal film is hard to be deposited. In addition, by-products generated when the first capping layer is removed on the lower metal wires may be prevented in a general method of manufacturing a semiconductor device, thereby increasing adhesion between the copper wires and the second interlayer insulating film.

이하 상기의 목적을 구체적으로 실현할 수 있는 본 발명의 바람직한 실시 예를 첨부한 도면을 참조하여 설명한다. 이때 도면에 도시되고 또 이것에 의해서 설명되는 본 발명의 구성과 작용은 적어도 하나의 실시 예로서 설명되는 것이며, 이것에 의해서 상기한 본 발명의 기술적 사상과 그 핵심 구성 및 작용이 제한되지는않는다.Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

그리고 본 발명에서 사용되는 용어는 가능한 한 현재 널리 사용되는 일반적인 용어를 선택하였으나, 특정한 경우는 출원인이 임의로 선정한 용어도 있으며, 이 경우 해당되는 발명의 설명 부분에서 상세히 그 의미를 기재하였으므로, 단순한 용어의 명칭이 아닌 그 용어가 가지는 의미로서 본 발명을 파악하여야 함을 밝혀두고자 한다.In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is to be understood that the present invention is to be understood as the meaning of the term rather than the name.

도 1 내지 도 3은 본 발명에 따른 반도체 소자의 제조 공정을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the present invention.

여기서, 도 1 내지 3에서는 전체 반도체 소자 중 본 발명과 관련된 영역만을 도시하였다. 이외의 영역은 일반적인 반도체 소자와 동일한 구성을 가지므로 도시를 생략하기로 한다.1 to 3 show only regions related to the present invention among all semiconductor devices. Since the other regions have the same configuration as that of a general semiconductor device, illustration thereof will be omitted.

먼저, 도 1에 도시된 바와 같이, 본 발명에 따른 반도체 소자의 제조 방법은 하부 금속 배선(10)이 형성된 제 1 층간 절연막(12) 상에 제 1 캡핑막(14)과 소정 두께를 갖는 제 2 층간 절연막(16)을 차례로 형성한다. First, as shown in FIG. 1, a method of manufacturing a semiconductor device according to the present invention includes a first capping layer 14 and a predetermined thickness on a first interlayer insulating layer 12 on which a lower metal wiring 10 is formed. The two interlayer insulating film 16 is formed in order.

여기서, 하부 금속 배선(10)은 구리(Cu)제 1 캡핑막(14)은 실리콘 나이트라이드(SiN)으로 형성되며, 하부 금속 배선(10)이 상부층으로 확산하는 것을 막는 역할 및 식각정지막으로써의 역할도 하게 된다. Here, the lower metal interconnection 10 is a copper (Cu) first capping layer 14 is formed of silicon nitride (SiN), and serves to prevent the lower metal interconnection 10 from diffusing to the upper layer and as an etch stop layer. Will also play a role.

이어, 소정의 패터닝 공정으로 제 2 층간 절연막(24)을 선택적으로 제거하여 하부 금속 배선(10)에 대응하는 제 1 캡핑막(14)의 일영역을 노출시키는 트렌치(20)를 형성한다. Subsequently, the second interlayer insulating layer 24 is selectively removed by a predetermined patterning process to form the trench 20 exposing one region of the first capping layer 14 corresponding to the lower metal line 10.

한편, 본원발명에서는 트렌치(20)만을 형성하는 것으로 설명하였지만 비아 및 트렌치로 이루어진 듀얼 다마신 구조의 콘택홀을 형성하는 것도 가능하다. On the other hand, in the present invention has been described as forming only the trench 20, it is also possible to form a contact hole having a dual damascene structure consisting of vias and trenches.

다음으로, 도 2에 도시된 바와 같이, Ar 또는 불활성기체를 이용한 리-스퍼터링(Re-sputtering) 공정을 통해 노출된 제 1 캡핑막(14) 부분을 제거한다. 이때, Ar 또는 불활성 기체를 이용함으로써 노출된 제 1 캡핑막(14)의 부분이 화학적 변화없이 순수하게 트렌치(20)의 벽면에 재증착하게 되어 제 2 캡핑막(14a)을 형성한다. 또한, 리-스퍼터링 공정은 100~500W의 AC 바이어스의 공정조건을 통해 수행하는 것이 바람직하다. Next, as shown in FIG. 2, the portion of the first capping layer 14 exposed through the re-sputtering process using Ar or an inert gas is removed. At this time, the portion of the first capping film 14 exposed by using Ar or an inert gas is redeposited on the wall surface of the trench 20 without chemical change to form the second capping film 14a. In addition, the re-sputtering process is preferably performed through the process conditions of the AC bias of 100 ~ 500W.

이와 같이 트렌치(20)의 양벽면에 형성된 제 2 캡핑막(14a)은 후속공정에서 형성될 배리어 금속막(24)과 함께 구리 배선의 확산을 이중으로 방지하게 되고, 배리어 금속막(24)이 증착되기 어려운 트렌치(20)의 측면에서 구리 배선과 배리어 금속막(24) 간의 접착력을 증가시킬 수 있다. 또한, 일반적인 반도체 소자의 제조방법에서 하부 금속 배선(10) 상에 제 1 캡핑막(14)을 제거할 시 발생하는 부산물을 원천적으로 방지할 수 있어, 구리 배선과 제 2 층간 절연막(16) 간의 접착력을 증 가시킬 수 있다. As described above, the second capping film 14a formed on both wall surfaces of the trench 20 prevents diffusion of copper wiring together with the barrier metal film 24 to be formed in a subsequent process, and the barrier metal film 24 The adhesion between the copper wiring and the barrier metal film 24 may be increased at the side of the trench 20 that is difficult to deposit. In addition, by-products generated when the first capping layer 14 is removed on the lower metal interconnection 10 may be fundamentally prevented in a method of manufacturing a semiconductor device, and thus, between the copper interconnection and the second interlayer insulating layer 16. It can increase the adhesion.

그리고나서, 도 3에 도시된 바와 같이, 제 2 캡핑막(14a) 및 트렌치(20)를 포함한 상기 결과물 전면에 이온화된 금속 플라즈마 스퍼터링(Ionized PVD) 방법으로 배리어 금속막(24)를 형성한다. Then, as shown in FIG. 3, the barrier metal film 24 is formed by ionized metal plasma sputtering (Ionized PVD) on the entire surface of the resultant product including the second capping film 14a and the trench 20.

이때, 배리어 금속막(24)은 Ta, TaN 계열의 물질로 형성하는 것이 바람직하다. In this case, the barrier metal film 24 is preferably formed of a Ta, TaN-based material.

이어서, 일반적인 반도체 소자의 제조방법과 같이, 전해도금법 및 CMP 공정 등을 이용하여 트렌치(20)를 매립함으로써 구리배선(30)을 형성하여 본 발명의 배선형성 방법에 따른 반도체 소자를 완성한다. Subsequently, the copper wiring 30 is formed by embedding the trenches 20 using an electroplating method, a CMP process, or the like, as in a general method of manufacturing a semiconductor device, thereby completing the semiconductor device according to the wiring forming method of the present invention.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1 내지 도 3은 본 발명에 따른 반도체 소자의 제조 공정을 도시한 단면도1 to 3 are cross-sectional views showing the manufacturing process of the semiconductor device according to the present invention.

Claims (6)

반도체 기판 상에 형성되며, 하부 금속배선을 갖는 제 1 층간 절연막상에 제 1 캡핑막과 제 2 층간 절연막을 차례로 형성하는 단계;Forming a first capping film and a second interlayer insulating film on a first interlayer insulating film formed on a semiconductor substrate and having lower metal wirings; 상기 제 2 층간 절연막에 상기 제 1 캡핑막의 일부분을 노출시키는 트렌치를 형성하는 단계;Forming a trench in the second interlayer dielectric to expose a portion of the first capping layer; 상기 노출된 제 1 캡핑막을 리스퍼터링(Re-Sputtering) 공정을 통해 선택적으로 제거하는 단계;Selectively removing the exposed first capping layer through a re-sputtering process; 상기 제 1 캡핑막을 포함한 전표면상에 배리어 금속막을 형성하는 단계;Forming a barrier metal film on the entire surface including the first capping film; 상기 트렌치를 매립하여 구리배선을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.And embedding the trench to form copper wiring. 제 1항에 있어서, The method of claim 1, 상기 노출된 제 1 캡핑막을 리스퍼터링(Re-Sputtering) 공정을 통해 선택적으로 제거할 때, 상기 트렌치의 양벽면에 제 2 캡핑막이 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.And selectively removing the exposed first capping layer through a re-sputtering process, wherein a second capping layer is formed on both sidewalls of the trench. 제 1항에 있어서, The method of claim 1, 상기 제 1 캡핑막 및 제 2 캡핑막은 SiN으로 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The first capping film and the second capping film is a semiconductor device manufacturing method, characterized in that formed of SiN. 제 1항에 있어서, The method of claim 1, 상기 리스퍼터링 공정은 Ar 또는 불활성 기체를 이용하여 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of manufacturing the semiconductor device, characterized in that for performing the resputtering process using Ar or an inert gas. 제 1항에 있어서, The method of claim 1, 상기 리스퍼터링 공정은 100~500W의 AC 바이어스의 공정조건에서 수행하는 것을 특징으로 하는 반도체 소자의 제조방법.The resputtering process is a semiconductor device manufacturing method, characterized in that performed under the process conditions of the AC bias of 100 ~ 500W. 제 2항에 있어서, 3. The method of claim 2, 상기 배리어 금속막은 상기 제 2 캡핑막을 포함한 전표면 상에 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.The barrier metal film is formed on the entire surface including the second capping film manufacturing method of a semiconductor device.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11990430B2 (en) 2021-01-28 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structures of integrated circuit devices and method forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11990430B2 (en) 2021-01-28 2024-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structures of integrated circuit devices and method forming the same

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