KR20110075358A - Test circuit of a semiconductor memory apparatus - Google Patents

Abstract

PURPOSE: A test circuit for a semiconductor memory device is provided to reduce a test period for a semiconductor memory device by monitoring a change in a property of a transistor according to a change of P.V.T(Process Voltage Temperature). CONSTITUTION: A test input signal generation unit generates a first test input signal and a second test input signal in response to an oscillator test signal, a pull-up test signal, a full-down test signal, and a clock. A test control signal generation unit(100) outputs a test voltage as a voltage of a PMOS control signal in response to a first test selection signal. A test control signal generation unit(200) outputs the PMOS control signal by inverting the first test input signal and outputs the test voltage as the test voltage of an NMOS control signal in response to a second test selection signal. A test control signal generation unit inverts the second test input signal and the NMOS control signal. A test driver(300) pulls up a voltage of an output node connected to a pad and pulls down the voltage of the output node.

Description

Test circuit of a semiconductor memory device {Test Circuit of a Semiconductor Memory Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly to test circuits for semiconductor memory devices.

In general, a semiconductor memory device is implemented using a transistor.

The transistor has a characteristic in which a characteristic changes with a P.V.T (process, voltage, temperature) change, and a semiconductor memory device implemented with such a transistor also changes in accordance with the P.V.T change.

In order to ensure stable operation of the semiconductor memory device, the semiconductor memory device is subjected to numerous tests.

Of the many tests that a semiconductor memory device must undergo, a test that first monitors the characteristics of transistors according to PVT changes in a wafer state is performed first to determine whether there is a defect in the semiconductor memory device and to perform the next test. Reduce test time.

There is an increasing demand for test circuits that can monitor transistor characteristic changes with P.V.T changes in wafer conditions.

The present invention has been made to solve the above-described problem, and provides a test circuit of a semiconductor memory device capable of monitoring a characteristic change of a transistor according to a change in P.V.T (process, voltage, temperature).

The test circuit of the semiconductor memory device according to an exemplary embodiment of the present invention may include a test input signal generator configured to generate a first test input signal and a second test input signal in response to an oscillator test signal, a pull-up test signal, a pull-down test signal, and a clock. Outputting a test voltage as a voltage of a PMOS control signal in response to a first test selection signal or inverting the first test input signal to output as a PMOS control signal, and in response to a second test selection signal, the test voltage Outputs the voltage as the NMOS control signal or inverts the second test input signal to output the NMOS control signal, and a voltage of an output node connected to the pad in response to the PMOS control signal. The output node in response to the NMOS control signal And a test driver configured to pull-down the voltage.

The test circuit of the semiconductor memory device according to the present invention can monitor the characteristic change of the transistor according to the change of P.V.T, thereby reducing the test period of the semiconductor memory device.

As illustrated in FIG. 1, a test circuit of a semiconductor memory device according to an embodiment of the present invention includes a test input signal generator 100, a test control signal generator 200, and a test driver 300.

The test input signal generator 100 may generate a clock CLK in response to an oscillator test signal T_ROD, a pull-up test signal T_PUON, and a pull-down test signal T_PDON, and then may include a first test input signal T_in1 and a second test signal. It outputs as a test input signal T_in2. The test input signal generator 100 may generate the first test input signal T_in1 in response to the pull-up test signal T_PUON and the oscillator test signal T_ROD, and the pull-down test signal T_PDON. And generate the second test input signal T_in2 in response to the oscillator test signal T_ROD.

The test input signal generator 100 includes a first input signal generator 110 and a second input signal generator 120.

The first input signal generator 110 outputs the clock CLK as the first test input signal T_in1 when both the oscillator test signal T_ROD and the pull-up test signal T_PUON are enabled. When the oscillator test signal T_ROD is disabled and the pull-up test signal T_PUON is enabled, the first test input signal T_in1 is disabled. When the pull-up test signal T_PUON is disabled, the oscillator is disabled. The first test input signal T_in1 is enabled regardless of the test signal T_ROD.

The first input signal generator 110 includes first and second NAND gates ND11 and ND12. The first NAND gate ND11 receives the clock CLK and the oscillator test signal T_ROD. The second NAND gate ND12 receives the output signal of the first NAND gate ND11 and the pull-up test signal T_PUON to output the first test input signal T_in1.

The second input signal generator 120 outputs the clock CLK as the second test input signal T_in2 when both the oscillator test signal T_ROD and the pull-down test signal T_PDON are enabled. When the oscillator test signal T_ROD is disabled and the pull-down test signal T_PDON is enabled, the second test input signal T_in2 is disabled, and when the pull-down test signal T_PDON is disabled, the oscillator test The second test input signal T_in2 is enabled regardless of the signal T_ROD.

The second input signal generator 120 includes first and second NOR gates NOR11 and NOR12. The first NOR gate NOR11 receives the inverted signal T_RODB of the clock CLK and the oscillator test signal T_ROD. The second NOR gate NOR12 receives the output signal of the first NOR gate NOR11 and the pull-down test signal T_PDON and outputs the test input signal T_in2.

The test control signal generator 200 outputs a test voltage V_test as a voltage of the PMOS control signal P_ctrl or inverts the first test input signal T_in1 in response to the first test selection signal T_sel1. And output as the PMOS control signal P_ctrl and output the test voltage V_test as a voltage of the NMOS control signal N_ctrl in response to the second test selection signal T_sel2. T_in2) is inverted and output as the NMOS control signal N_ctrl.

The test control signal generator 200 outputs the test voltage V_test as a voltage of the PMOS control signal P_ctrl when the first test select signal T_sel1 is enabled, and the first test select signal. When T_sel1 is disabled, the first test input signal T_in1 is inverted and output as the PMOS control signal P_ctrl.

In addition, when the second test selection signal T_sel2 is enabled, the test control signal generation unit 200 outputs the test voltage V_test as the voltage of the NMOS control signal N_ctrl and the second test. When the selection signal T_sel2 is disabled, the second test input signal T_in2 is inverted and output as the NMOS control signal N_ctrl.

The test control signal generator 200 includes first to fourth switching units 210 to 240.

The first switching unit 210 outputs the test voltage V_test as a voltage of the PMOS control signal P_ctrl when the first test selection signal T_sel1 is enabled.

The first switching unit 210 is implemented as a first pass gate PG11, and the first pass gate PG11 transmits an inverted signal T_sel1B of the first test select signal T_sel1 to a first control terminal. The first test selection signal T_sel1 is input to the second control terminal, the test voltage V_test is input to the input terminal, and the PMOS control signal P_ctrl is output at the output terminal.

When the first test select signal T_sel1 is disabled, the second switching unit 220 inverts the first test input signal T_in1 and outputs the PMOS control signal P_ctrl.

The second switching unit 220 is implemented as a first control inverter IVC11, and the first control inverter IVC11 receives the first test selection signal T_sel1 from a first control terminal and receives a second control terminal. The inverting signal T_sel1B of the first test selection signal T_sel1 is input to the input terminal, and the PMOS control signal P_ctrl is output at the output terminal by receiving the first test input signal T_in1 at the input terminal.

When the second test select signal T_sel1 is enabled, the third switching unit 230 outputs the test voltage V_test as the voltage of the NMOS control signal N_ctrl.

The third switching unit 230 is implemented as a second pass gate PG12, and the second pass gate PG12 transmits an inverted signal T_sel2B of the second test select signal T_sel2 to a first control terminal. The input terminal receives the second test selection signal T_sel2 at the second control terminal, receives the test voltage V_test at the input terminal, and outputs the NMOS control signal N_ctrl at the output terminal.

When the second test select signal T_sel2 is disabled, the fourth switching unit 240 inverts the second test input signal T_in2 and outputs the NMOS control signal N_ctrl.

The fourth switching unit 240 is implemented as a second control inverter IVC12, and the second control inverter IVC11 receives the second test selection signal T_sel2 from a first control terminal and receives a second control terminal. The inverting signal T_sel2B of the second test selection signal T_sel2 is input to the second test input signal T_sel2B, and the input terminal receives the second test input signal T_in2 to output the NMOS control signal N_ctrl.

The test driver 300 performs a pull-up operation on the output node node_out connected to the pad PAD in response to the PMOS control signal P_ctrl and the output node in response to the NMOS control signal N_ctrl. Perform a pulldown operation on (node_out).

The test driver 300 includes first and second transistors P11 and N11. The PMOS control signal P_ctrl is input to a gate, an external voltage VDD is applied to a source, and the output node node_out is connected to a drain of the first transistor P11. The second transistor N11 receives the NMOS control signal N_ctrl on a gate, the output node node_out is connected to a drain, and a ground terminal VSS is connected to a source. In this case, the output node node_out is connected to the pad PAD.

The test using the test circuit of the semiconductor memory device according to the embodiment configured as described above is performed as follows.

First, a test for monitoring the output of the clock CLK, that is, the oscillator implemented in the semiconductor memory device will be described.

The oscillator test signal T_ROD and the pull-up test signal T_PUON are enabled to a high level. At this time, the inversion signal T_RODB of the oscillator test signal T_ROD is disabled to a low level. It also enables the pull-down test signal (T_PDON) to a low level. The first and second test select signals T_sel1 and T_sel2 are disabled to a low level.

The test input signal generator 100 outputs the clock CLK as a first test input signal T_in1 and a second test input signal T_in2.

The second and third switching units 220 and 230 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned on second and third switching units 220 and 230 invert the first and second test input signals T_in1 and T_in2, respectively, as PMOS control signals and NMOS control signals N_ctrl. Output

When the PMOS control signal P_ctrl is enabled at the low level, the test driver 300 performs a pull-up operation to increase the voltage level of the output node node_out and the NMOS control signal N_ctrl to the high level. When enabled, a pull-down operation is performed to lower the voltage level of the output node node_out.

As a result, when the clock CLK is at a high level, the first and second test input signals T_in1 and T_in2 are at a high level, and the PMOS and NMOS control signals P_ctrl and N_ctrl are at a low level. The test driver 300 performs a pull-up operation. In addition, when the clock CLK is at a low level, the first and second test input signals T_in1 and T_in2 are at a low level, and the PMOS and NMOS control signals P_ctrl and N_ctrl are at a high level. The test driver 300 performs a pull-down operation. The clock CLK is outputted to the outside of the semiconductor memory device through the pad PAD, and a test for monitoring the clock CLK can be performed.

Second, a test for monitoring the amount of output current of the PMOS transistor P11 driven in the saturation region will be described.

The oscillator test signal T_ROD and the pull-up test signal T_PUON are disabled to a low level. In this case, the inversion signal T_RODB of the oscillator test signal T_ROD is disabled to a high level. It also enables the pull-down test signal (T_PDON) to a low level. The first and second test select signals T_sel1 and T_sel2 are disabled to a low level.

The test input signal generator 100 outputs the first test signal T_in1 enabled at a high level and outputs the second test input signal T_in2 disabled at a high level.

The second and third switching units 220 and 230 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned on second and third switching units 220 and 230 invert the first and second test input signals T_in1 and T_in2, respectively, as PMOS control signals and NMOS control signals N_ctrl. Output

That is, the PMOS control signal P_ctrl is enabled at the low level, and the NMOS control signal N_ctrl is disabled at the low level.

The PMOS transistor P11 of the test driver 300 is turned on and the NMOS transistor N11 is turned off. The PMOS transistor P11 receives the PMOS control signal P_ctrl having a ground voltage VSS level. That is, the test driver 300 outputs the output current of the PMOS transistor P11 driven in the saturation region to the pad PAD via the output node node_out.

In this case, by monitoring the amount of current output from the pad PAD, the current output by the PMOS transistor in the saturation region implemented in the semiconductor memory device may be tested.

Third, a test for monitoring the amount of output current of the NMOS transistor N11 driven in the saturation region will be described.

The oscillator test signal T_ROD is disabled to a low level. The pull-up test signal T_PUON is enabled to a high level. In this case, the inversion signal T_RODB of the oscillator test signal T_ROD is enabled to a high level. It also disables the pull-down test signal (T_PDON) to a high level. The first and second test select signals T_sel1 and T_sel2 are disabled to a low level.

The test input signal generator 100 outputs the first test signal T_in1 disabled at a low level and outputs the second test input signal T_in2 enabled at a low level.

The second and third switching units 220 and 230 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned on second and third switching units 220 and 230 invert the first and second test input signals T_in1 and T_in2, respectively, as PMOS control signals and NMOS control signals N_ctrl. Output

That is, the PMOS control signal P_ctrl is disabled at a high level, and the NMOS control signal N_ctrl is enabled at a high level.

Then, the PMOS transistor P11 of the test driver 300 is turned off and the NMOS transistor N11 is turned on. The NMOS transistor N11 receives a gate of the NMOS control signal N_ctrl at an external voltage level VDD. That is, the test driver 300 outputs the output current of the NMOS transistor N11 driven in the saturation region to the pad PAD via the output node node_out.

In this case, by monitoring the amount of current output from the pad PAD, the current output by the NMOS transistor in the saturation region implemented in the semiconductor memory device may be tested.

Fourth, a test for monitoring the amount of current output to the output node node_out by the NMOS transistor N11 and the PMOS transistor P11 driven in the saturation region will be described.

The pull-up test signal T_PUON is disabled to a low level. In addition, the pull-down test signal T_PDON is disabled to a high level. The first and second test select signals T_sel1 and T_sel2 are disabled to a low level.

The test input signal generator 100 outputs the first test signal T_in1 enabled at a high level and outputs the second test input signal T_in2 enabled at a low level.

The second and third switching units 220 and 230 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned on second and third switching units 220 and 230 invert the first and second test input signals T_in1 and T_in2, respectively, as PMOS control signals and NMOS control signals N_ctrl. Output

That is, the PMOS control signal P_ctrl is enabled at a low level, and the NMOS control signal N_ctrl is enabled at a high level.

The PMOS transistor P11 and the NMOS transistor N11 of the test driver 300 are turned on. The NMOS transistor N11 is turned on by receiving the NMOS control signal N_ctrl having a level of an external voltage VDD at a gate thereof, and the PMOS transistor P11 is turned off at a ground voltage VSS level at a gate thereof. It is turned on by receiving the Morse control signal P_ctrl. That is, the test driver 300 outputs currents output from the NMOS transistor N11 and the PMOS transistor P11 in a saturation region to the pad PAD via the output node node_out.

In this case, by monitoring the amount of current output from the pad PAD, the current output from the NMOS transistor and the PMOS transistor in the saturation region implemented in the semiconductor memory device may be tested.

Fifth, a test for monitoring the amount of current output by the PMOS transistor P11 according to the voltage level input to the gate will be described.

The oscillator test signal T_ROD is disabled to a low level. In this case, the inversion signal T_RODB of the oscillator test signal T_ROD is enabled to a high level. It also enables the pull-down test signal (T_PDON) to a low level. The first test select signal T_sel1 is enabled at a high level and the second test select signal T_sel2 is disabled at a low level.

The test input signal generator 100 outputs the second test input signal T_in2 disabled to a high level.

The first and third switching units 210 and 230 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned-on first switching unit 210 outputs a test voltage V_test as a voltage of the PMOS control signal P_ctrl. The turned on third switching unit 230 inverts the second test input signal T_in2 and outputs the NMOS control signal N_ctrl.

That is, the NMOS control signal N_ctrl is disabled at a low level.

The NMOS transistor N11 of the test driver 300 is turned off. The PMOS transistor P11 receives the test voltage V_test at a gate thereof.

As a result, the PMOS transistor P11 receiving the test voltage V_test from the gate outputs an output current corresponding to the test voltage V_test level to the output node node_out.

In this case, by monitoring the amount of current output from the pad PAD connected to the output node node_out, the amount of current output by the PMOS transistor implemented in the semiconductor memory device according to the gate voltage level may be monitored.

Finally, a test for monitoring the amount of current outputted by the NMOS transistor N11 according to the voltage level input to the gate will be described.

The oscillator test signal T_ROD is disabled to a low level. In this case, the inversion signal T_RODB of the oscillator test signal T_ROD is enabled to a high level. It also enables the pull-up test signal T_PUON to a high level. The first test select signal T_sel1 is disabled to a low level and the second test select signal T_sel2 is enabled to a high level.

The test input signal generator 100 outputs the first test input signal T_in1 disabled to a low level.

The second and fourth switching units 220 and 240 of the first to fourth switching units 210 to 240 of the test control signal generator 200 are turned on. The turned-on second switching unit 220 inverts the first test input signal T_in1 and outputs the PMOS control signal P_ctrl. The turned on fourth switching unit 240 outputs a test voltage V_test as the voltage of the NMOS control signal N_ctrl.

That is, the PMOS control signal P_ctrl is disabled to a high level.

The PMOS transistor P11 of the test driver 300 is turned off. The NMOS transistor N11 receives the test voltage V_test at a gate thereof.

As a result, the test driver 300 outputs, to the output node node_out, a current output by the NMOS transistor N11 receiving the test voltage V_test from the gate according to the test voltage V_test level.

In this case, by monitoring the amount of current output from the pad PAD connected to the output node node_out, the amount of current output by the NMOS transistor implemented in the semiconductor memory device according to the gate voltage level may be monitored.

The test circuit of the semiconductor memory device according to the present invention can monitor the characteristic change of the transistor according to the P.V.T change, thereby reducing the test period of the semiconductor memory device.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a configuration diagram schematically illustrating a test circuit of a semiconductor memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: test input signal generator 200: test control signal generator

300: test driver

Claims (6)

A test input signal generator configured to generate a first test input signal and a second test input signal in response to an oscillator test signal, a pull-up test signal, a pull-down test signal, and a clock; Outputting a test voltage as a voltage of a PMOS control signal in response to a first test selection signal or inverting the first test input signal to output as a PMOS control signal, and outputting the test voltage in response to a second test selection signal A test control signal generator for outputting the voltage of the NMOS control signal or inverting the second test input signal and outputting the NMOS control signal; And And a test driver configured to pull up a voltage of an output node connected to a pad in response to the PMOS control signal, and to pull down a voltage of the output node in response to the NMOS control signal. Test circuit. The method of claim 1, The test input signal generator Outputting the clock as the first test input signal when both the oscillator test signal and the pull-up test signal are enabled; Disabling the first test input signal when the oscillator test signal is disabled and the pull-up test signal is enabled, And a first input signal generator configured to enable the first test input signal irrespective of the oscillator test signal when the pull-up test signal is disabled. The method of claim 2, The test input signal generator Outputting the clock as the first test input signal when both the oscillator test signal and the pull-down test signal are enabled; Disabling the second test input signal when the oscillator test signal is disabled and the pull-down test signal is enabled, And a second input signal generator configured to enable the second test input signal irrespective of the oscillator test signal when the pull-down test signal is disabled. The method of claim 1, The test control signal generator When the first test select signal is enabled, the test voltage is output as the voltage of the PMOS control signal. When the first test select signal is disabled, the first test input signal is inverted to be used as the PMOS control signal. Output, When the second test select signal is enabled, the test voltage is output as the voltage of the NMOS control signal, and when the second test select signal is disabled, the second test input signal is inverted to form the NMOS control signal. Outputting a test circuit of a semiconductor memory device. The method of claim 4, wherein The test control signal generator A first switching unit outputting the test voltage as a voltage of the PMOS control signal when the first test selection signal is enabled; A second switching unit which inverts the first test input signal and outputs the PMOS control signal when the first test selection signal is disabled; A third switching unit which outputs the test voltage as the voltage of the NMOS control signal when the second test selection signal is enabled, and And a fourth switching unit for inverting the second test input signal and outputting the second test input signal as the NMOS control signal when the second test select signal is disabled. The method of claim 1, The test driver A first transistor applying an external voltage to the output node in response to the PMOS control signal, and And a second transistor connecting the output node and the ground terminal in response to the NMOS control signal.

Images