KR20110074355A - Transistor - Google Patents

Abstract

PURPOSE: A transistor is provided to prevent etching issue, lack of uniformity, and a leakage current by increasing threshold voltage through an insertion layer between a source electrode and a channel layer. CONSTITUTION: In a transistor, a channel layer(C1) including an oxide semiconductor is formed on a substrate(SUB1). A gate electrode(G1) is formed on the channel layer. A source electrode(S1) and a drain electrode(D1) are respectively contacted with both ends of the channel layer. A semiconductor insertion layer(A1) is formed between the source electrode and the channel layer. A potential barrier between the source electrode and the channel layer is increased by the semiconductor insertion layer.

Description

Transistor

It relates to a transistor, and more particularly to an oxide transistor.

Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, the thin film transistor is usefully used in the field of flat panel display devices such as a liquid crystal display device or an organic light emitting display device.

In order to improve the operating characteristics of a transistor, a method of applying an oxide semiconductor layer as a channel layer has been attempted. This method is mainly applied to thin film transistors for flat panel display devices. However, in the case of a transistor having an oxide semiconductor layer as a channel layer (hereinafter referred to as an oxide transistor), there is a problem that it is not easy to control the threshold voltage.

In more detail, when the silicon layer is used as the channel layer, the threshold voltage can be easily controlled by adjusting the doping concentration, but in the case of the oxide transistor, the threshold due to doping due to self-compensation phenomenon Voltage regulation is not easy. Oxide transistors are also "majority carrier devices" of the same type of channel and type of carrier charge that moves from source to drain. Such majority carrier devices operate in an accumulation mode and typically have a threshold voltage less than zero (n-type reference). Therefore, when the oxide semiconductor layer is used as the channel layer, it is difficult to implement an enhancement mode transistor having a threshold voltage greater than zero (n-type reference).

Provided is an oxide transistor that can easily adjust a threshold voltage.

According to an aspect of the invention, a channel layer comprising an oxide semiconductor; A gate electrode corresponding to the channel layer; Source and drain electrodes in contact with both ends of the channel layer, respectively; And a semiconductor insertion layer provided between the channel layer and the source electrode, wherein the semiconductor insertion layer increases a potential barrier between the channel layer and the source electrode.

When the channel layer is n-type, the work function of the semiconductor insertion layer may be larger than the work function of the channel layer. In this case, the n-type carrier concentration of the semiconductor insertion layer may be lower than the n-type carrier concentration of the channel layer.

When the channel layer is p-type, the work function of the semiconductor insertion layer may be smaller than the work function of the channel layer. In this case, the p-type carrier concentration of the semiconductor insertion layer may be lower than the p-type carrier concentration of the channel layer.

The channel layer is any one or a series selected from the group consisting of ZnO, GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO and mixtures thereof It may include an oxide semiconductor.

The channel layer may be formed of a ZnO-based oxide semiconductor.

The ZnO-based oxide semiconductor may further include at least one element selected from the group consisting of In, Ga, Sn, Ti, Zr, Hf, Y, and Ta.

The semiconductor insertion layer is SiC, AlN, GaN, InN, AlP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnS, CdS, ZnTe, CdTe, CdSe, CdS, ZnO, GaO, InO, SnO, CdO, CaO It may include any one or a series of compounds selected from the group consisting of, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO and mixtures thereof.

The semiconductor insertion layer may have an energy band gap of about 0.5 to 4.0 eV.

The semiconductor insertion layer may have a thickness of about 1 to 300 Å.

The transistor may be in enhancement mode.

A separate semiconductor insertion layer may be further provided between the channel layer and the drain electrode.

The separate semiconductor insertion layer provided between the channel layer and the drain electrode may be formed of the same material as the semiconductor insertion layer provided between the channel layer and the source electrode.

The transistor may be a thin film transistor having a top-gate structure.

The transistor may be a thin film transistor having a bottom-gate structure.

It is possible to implement an oxide transistor that can easily adjust a threshold voltage. The oxide transistor may be in an enhancement mode.

Hereinafter, a transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The width and thickness of the layers or regions shown in the accompanying drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

1 shows a transistor according to an embodiment of the present invention. The transistor of this embodiment is a thin film transistor having a top-gate structure in which the gate electrode G1 is provided above the channel layer C1.

Referring to FIG. 1, a channel layer C1 may be provided on a substrate SUB1. The substrate SUB1 may be one of a silicon substrate, a glass substrate, and a plastic substrate, and may be transparent or opaque. The channel layer C1 may be an oxide semiconductor layer. The channel layer C1 may be n-type or p-type. When the channel layer C1 is an n-type oxide semiconductor layer, for example, a group consisting of ZnO, GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO and mixtures thereof It may include any one or a series of oxides selected from. In the case where the channel layer C1 is formed of a ZnO-based oxide semiconductor, the channel layer C1 may include at least one element selected from the group consisting of In, Ga, Sn, Ti, Zr, Hf, Y, and Ta. It may further include. When the channel layer C1 is a p-type oxide semiconductor layer, for example, the channel layer C1 may include any one or a series of oxides selected from the group consisting of NiO, CuO, and a mixture thereof. The channel layer C1 may have a single layer or a multilayer structure. Although not shown, an insulating layer (not shown) may be provided between the substrate SUB1 and the channel layer C1. That is, after the insulating layer is formed on the substrate SUB1, the channel layer C1 may be formed thereon.

A gate insulating layer GI1 covering the channel layer C1 may be provided on the substrate SUB1. The gate insulating layer GI1 may be a silicon oxide layer or a silicon nitride layer, but may be a high dielectric material layer having a higher dielectric constant than other material layers, for example, a silicon nitride layer. The gate insulating layer GI1 may have a structure in which at least two layers of a silicon oxide layer, a silicon nitride layer, and a high dielectric material layer are stacked.

The gate electrode G1 may be provided on the gate insulating layer GI1. The gate electrode G1 may be provided to correspond to the central portion of the channel layer C1. The gate electrode G1 may be formed of a general electrode material (metal, metal oxide, etc.).

Source electrodes S1 and drain electrodes D1 may be provided at both ends of the channel layer C1, respectively. The source electrode S1 and the drain electrode D1 may be formed of metal. The source electrode S1 and the drain electrode D1 may be the same metal layer as the gate electrode G1, or may be another metal layer.

A semiconductor insertion layer (hereinafter referred to as an insertion layer) A1 may be selectively provided between the source electrode S1 and the channel layer C1. In other words, the source electrode S1 and the channel layer C1 may be in contact with each other via the insertion layer A1. In this case, the drain electrode D1 and the channel layer C1 may be in direct contact.

The insertion layer A1 may serve to increase (or generate) a potential barrier between the channel layer C1 and the source electrode S1. That is, the potential barrier between the channel layer C1 and the source electrode S1 can be increased by the insertion layer A1. The height and thickness of the potential barrier may vary according to the material and thickness of the insertion layer A1, and as a result, the threshold voltage of the transistor may be adjusted. Therefore, the insertion layer A1 may be referred to as a threshold voltage adjusting layer. The insertion layer A1 is, for example, a non-oxide semiconductor layer containing at least one of a Group 4-4 compound, a Group 3-5 compound, a Group 2-6 compound, and a Group 1-7 compound, or an oxide semiconductor layer or a nonoxide. The semiconductor layer may be mixed with an oxide. More specifically, the insertion layer A1 may be formed of SiC, AlN, GaN, InN, AlP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnS, CdS, ZnTe, CdTe, CdSe, CdS, ZnO, GaO, InO, It may include any one or a series of compounds selected from the group consisting of SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO and mixtures thereof. When the insertion layer A1 is an oxide layer, it may include an oxide of the same series as the channel layer C1, but may not be. When the insertion layer A1 includes the same series of oxides as the channel layer C1, the oxygen concentration and the doping state of the insertion layer A1 and the channel layer C1 may be different. The energy bandgap of the insertion layer A1 may be about 0.5 to 4.0 eV. The thickness of the insertion layer A1 may be, for example, about 1 to 300 GPa.

When the channel layer C1 is n-type, the work function of the insertion layer A1 may be larger than the work function of the channel layer C1. If this condition is satisfied, the insertion layer A1 can be either n-type or p-type. The n-type carrier concentration of the insertion layer A1 may be lower than the n-type carrier concentration of the channel layer C1. Therefore, the insertion layer A1 may be an n-type semiconductor layer having a lower n-type carrier concentration than the channel layer C1 or a p-type semiconductor layer. If both the insertion layer A1 and the channel layer C1 are n-type oxide layers, the oxygen concentration of the insertion layer A1 may be higher than that of the channel layer C1. This is because, in the n-type oxide, the higher the oxygen concentration, the lower the carrier concentration.

When the channel layer C1 is p-type, the work function of the insertion layer A1 may be smaller than the work function of the channel layer C1. Also in this case, both the n type and the p type can be used for the insertion layer A1. The p-type carrier concentration of the insertion layer A1 may be lower than the p-type carrier concentration of the channel layer C1. Therefore, the insertion layer A1 may be a p-type semiconductor layer having a lower p-type carrier concentration than the channel layer C1 or an n-type semiconductor layer. If the insertion layer A1 and the channel layer C1 are p-type oxide layers, the oxygen concentration of the insertion layer A1 may be lower than that of the channel layer C1. This is because in the p-type oxide, the lower the oxygen concentration, the lower the carrier concentration.

As such, the material of the insertion layer A1 may be appropriately selected depending on the type of the channel layer C1. As described above, the material of the insertion layer A1 may be a non-oxide semiconductor including at least one of a Group 4-4 compound, a Group 3-5 compound, a Group 2-6 compound, and a Group 1-7 compound, and ZnO, It may be selected from oxide semiconductors such as GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO and the like.

In addition, the metal oxide such as TiO may vary greatly in its composition. For example, a metal oxide such as TiO may have semiconductor characteristics or conductor characteristics depending on its composition. In this embodiment, an oxide semiconductor having semiconductor characteristics is used as the insertion layer A1. In this case, the insertion layer A1 increases the potential barrier between the channel layer C1 and the source electrode S1. The insertion layer A1 may not be in ohmic contact with the source electrode S1.

The source electrode S1 and the channel layer C1 are in contact with the insertion layer A1 interposed therebetween, and the drain electrode D1 and the channel layer C1 are in direct contact with each other. The potential barriers on the electrode D1 side are different from each other. The potential barrier at the source electrode S1 may be higher than the potential barrier at the drain electrode D1. The structure in which the insertion layer A1 is selectively provided only between the source electrode S1 and the channel layer C1 is defined as an asymmetric source / drain structure. Since the threshold voltage of the transistor may be greatly influenced by the potential barrier of the source electrode S1 to which electrons or holes are supplied, the threshold voltage may be selectively provided by only the insertion layer A1 only on the source electrode S1 side. . The threshold voltage may be adjusted by the height and thickness of the potential barrier by the insertion layer A1.

In FIG. 1, an insulating layer IL1 covering the gate electrode G1 is provided on the gate insulating layer GI1 and exposes the channel layer C1 to the insulating layer IL1 and the gate insulating layer GI1. And second holes H1 and H2. The first hole H1 may expose one end of the channel layer C1 and the second hole H2 may expose the other end of the channel layer C1. The insertion layer A1 and the source electrode S1 may be provided in the first hole H1, and the drain electrode D1 may be provided in the second hole H2. This structure is merely exemplary and may be variously modified. For example, although the insertion layer A1 is illustrated as being formed only on the bottom surface of the first hole H1, the insertion layer A1 may be applied to the inner wall as well as the bottom surface of the first hole H1. In another embodiment, after the insertion layer A1 is formed at one end of the channel layer C1, the insulation layer IL1 is formed to cover the insertion layer A1, and then the insertion layer is formed on the insulation layer IL1. A hole exposing (A1) may be formed, and a source electrode S1 may be formed in the hole. In this case, the width of the insertion layer A1 may be wider than that of the source electrode S1. In FIG. 1, the insertion layer A1 is provided as a separate layer on the channel layer C1, but in another embodiment, a part of the upper surface portion of the channel layer C1 serves as the insertion layer A1. It may be. In addition, the structure of FIG. 1 may be modified in various ways.

As shown in the embodiment of FIG. 1, when the insertion layer A1 is provided between the source electrode S1 and the channel layer C1, the insertion layer A1 is disposed between the source electrode S1 and the channel layer C1. The potential barrier may increase and the threshold voltage of the transistor may increase. In the case of an n-type transistor, the threshold voltage increases in a positive direction, and in the case of a p-type transistor, the threshold voltage increases in a negative direction. The n-type transistor may be increased when the threshold voltage is greater than zero, and the n-type transistor may be increased when the threshold voltage is less than zero. Therefore, according to the present embodiment, an enhancement mode oxide transistor can be implemented. In the case of a transistor in which an oxide is applied as a channel layer, it is generally difficult to adjust the threshold voltage by doping due to a self-compensation phenomenon. In addition, oxide transistors were operated as an "majority carrier device," operating in an accumulation mode, and were easily turned on at low voltages, making it difficult to make them in enhancement mode. However, in the embodiment of the present invention, by using the insertion layer A1 which increases the potential barrier between the source electrode S1 and the channel layer C1 as described above, the threshold voltage of the oxide transistor can be increased and increased. An enhancement mode transistor can be implemented. In addition, the threshold voltage may be appropriately adjusted according to the purpose by adjusting the material and the thickness of the insertion layer A1.

2 shows a transistor according to another embodiment of the present invention. The transistor of this embodiment is a thin film transistor having a bottom-gate structure in which the gate electrode G2 is provided under the channel layer C2.

Referring to FIG. 2, a gate electrode G2 may be provided on the substrate SUB2. An insulating layer (not shown) may be formed on the substrate SUB2, and a gate electrode G2 may be formed thereon. A gate insulating layer GI2 covering the gate electrode G2 may be provided on the substrate SUB2. The channel layer C2 may be provided on the gate insulating layer GI2. The channel layer C2 may be provided above the gate electrode G2, and may have a width slightly larger than that of the gate electrode G2. The source electrode S2 and the drain electrode D2 may be provided in contact with both ends of the channel layer C2. A semiconductor insertion layer (hereinafter, referred to as an insertion layer) A2 may be selectively provided between the channel layer C2 and the source electrode S2. An insulating layer IL2 may be provided on the gate insulating layer GI2 to cover the channel layer C2, and first and second holes H1 ′ and H2 ′ may be formed in the insulating layer IL2. The insertion layer A2 and the source electrode S2 may be provided in the first hole H1 ′, and the drain electrode D2 may be provided in the second hole H2 ′. In FIG. 2, materials, configurations, thicknesses, and the like of the substrate SUB2, the gate electrode G2, the channel layer C2, the source electrode S2, the drain electrode D2, and the insertion layer A2 are illustrated in FIG. 1. It may be the same as or similar to that of SUB1, gate electrode G1, channel layer C1, source electrode S1, drain electrode D1, and insertion layer A1.

1 and 2, holes H1, H1 ', H2, and H2' are formed in the insulating layers IL1 and IL2, and source electrodes S1 and S2 and drain electrodes D1 and D2 are formed therein. Although one structure has been illustrated and described, in another embodiment, the source electrode and the drain electrode may be formed without using the holes. Examples are shown in FIGS. 3 and 4.

Referring to FIG. 3, a channel layer C3 may be provided on the substrate SUB3, and a source electrode S3 and a drain electrode D3 may be provided to cover both ends of the channel layer C3. An insertion layer A3 may be interposed between the channel layer C3 and the source electrode S3. A gate insulating layer GI3 covering the source electrode S3, the drain electrode D3, and the channel layer C3 may be provided. The gate electrode G3 may be provided on the gate insulating layer GI3. In FIG. 3, materials, configurations, thicknesses, and the like of the substrate SUB3, the gate electrode G3, the channel layer C3, the source electrode S3, the drain electrode D3, and the insertion layer A3 are illustrated in FIG. It may be the same as or similar to that of SUB1, gate electrode G1, channel layer C1, source electrode S1, drain electrode D1, and insertion layer A1.

Referring to FIG. 4, a gate electrode G4 may be provided on the substrate SUB4, and a gate insulating layer GI4 covering the gate electrode G4 may be provided. The channel layer C4 may be provided on the gate insulating layer GI4, and the source electrode S4 and the drain electrode D4 may be provided to cover both ends of the channel layer G4. An insertion layer A4 may be interposed between the channel layer C4 and the source electrode S4. In FIG. 4, materials, configurations, thicknesses, and the like of the substrate SUB4, the gate electrode G4, the channel layer C4, the source electrode S4, the drain electrode D4, and the insertion layer A4 are illustrated in FIG. It may be the same as or similar to that of SUB1, gate electrode G1, channel layer C1, source electrode S1, drain electrode D1, and insertion layer A1.

In FIGS. 3 and 4, the source electrodes S3 and S4 and the drain electrodes D3 and D4 are provided to contact both ends of the upper surfaces of the channel layers C3 and C4, but in another embodiment, the source electrode and the drain electrode are channel channels. It may be in contact with both ends of the lower surface.

9 shows an example of an energy band diagram of a source electrode, an insertion layer, and a channel layer of a transistor according to an embodiment of the present invention. 9 illustrates a case in which the channel layer is n-type. In FIG. 9, reference numerals E _C and E _V denote vacuum energy levels, lowest energy levels of conduction bands and highest energy levels of valence bands, and E _F denotes Fermi energy levels. This indication is the same in FIGS. 10 to 12.

9, the E _C E _C of the insertion layer is greater than the channel layer. This is because the work function of the insertion layer is larger than the work function of the channel layer so that when they are bonded, E _C and E _V of the channel layer are lowered as a whole. Therefore, a potential barrier Φ _B for electrons (e−) is generated between the source electrode (metal) and the channel layer by the insertion layer. The potential barrier Φ _B may serve to suppress the flow of electrons (e−) moving from the source electrode to the channel layer. A larger gate voltage may be required to move the electron e- over the potential barrier Φ _B. Therefore, the threshold voltage of the transistor may increase in the positive direction by the insertion layer. The increase in the threshold voltage may vary depending on the height of the potential barrier Φ _B and the thickness of the insertion layer. If the thickness of the insertion layer is very thin, the electron (e−) can be tunneled through it, and thus the effect of increasing the threshold voltage may be somewhat reduced. However, if it is desired to finely adjust the threshold voltage, it may be suitable to form a thin thickness of the insertion layer. Meanwhile, in the figure, E _F of the channel layer is very close to E _C , but E _F of the insertion layer is relatively far from E _C. This means that the n-type carrier concentration of the insertion layer is lower than the n-type carrier concentration of the channel layer.

10 shows an energy band diagram of a source electrode and a channel layer of a transistor according to a first comparative example without an insertion layer. At this time, the channel layer is n-type. That is, FIG. 10 is an energy band diagram of the case where the source electrode and the channel layer are in direct contact with the insertion layer removed in FIG. 9.

Referring to FIG. 10, when the source electrode and the channel layer are in direct contact, the potential barrier Φ _B therebetween is considerably lower than the potential barrier Φ _B in FIG. 9. In this case, the transistor is in a depletion mode where the threshold voltage is less than zero.

11 is an energy band diagram of a source electrode, an insertion layer and a channel layer of a transistor according to another embodiment of the present invention. 11 shows a case in which the channel layer is p-type.

11, the E _V E _V lower than that of the insertion layer in the channel layer. This is because the work function of the insertion layer is smaller than the work function of the channel layer so that when they are bonded, E _C and E _V of the channel layer move upwards as a whole. Therefore, the potential barrier Φ _B for the holes h is generated between the source electrode (metal) and the channel layer by the insertion layer. The potential barrier Φ _B may serve to suppress the flow of holes h that move from the source electrode to the channel layer. In order to move the hole h beyond the potential barrier Φ _B , a larger gate voltage may be required. Therefore, the threshold voltage of the transistor may increase in the negative direction by the insertion layer. The increase in the threshold voltage may vary depending on the height of the potential barrier Φ _B and the thickness of the insertion layer. Meanwhile, in the figure, E _F of the channel layer is very close to E _C , but E _F of the insertion layer is relatively far from E _C. This means that the p-type carrier concentration of the insertion layer is lower than the p-type carrier concentration of the channel layer.

12 shows an energy band diagram of a source electrode and a channel layer of a transistor according to a second comparative example without an insertion layer. At this time, the channel layer is p-type. That is, FIG. 12 is an energy band diagram of the case where the source electrode and the channel layer are directly contacted with the insertion layer removed in FIG. 11.

Referring to FIG. 12, when the source electrode and the channel layer are in direct contact, the potential barrier Φ _B therebetween is considerably smaller than the potential barrier Φ _B in FIG. 11. In this case, the transistor can be easily turned on.

9 and 11, when the insertion layer is used, the potential barrier is increased between the source electrode and the channel layer, thereby increasing the threshold voltage of the transistor. Thus, the transistor may be an enhancement mode transistor. However, the transistor of this embodiment does not necessarily need to be an increased type. Depending on the purpose, the threshold voltage may be adjusted while keeping the mode depleted.

1 to 4 illustrate and illustrate the asymmetric source / drain structure in which the semiconductor insertion layers A1 to A4 are formed only on the source electrodes S1 to S4, according to another embodiment of the present invention. The semiconductor insertion layers A1 to A4 can also be formed on the drain electrodes D1 to D4. Examples are shown in FIGS. 5 to 8.

5 to 8 are modified in the embodiments of FIGS. 1 to 4, respectively, and further include insertion layers A1 to A4 between the channel layers C1 to C4 and the drain electrodes D1 to D4. . The rest of the configuration is the same as that of FIGS. The structure in which the insertion layers A1 to A4 are provided on both the source electrodes S1 to S4 and the drain electrodes D1 to D4 is called a symmetric source / drain structure.

As shown in Figs. 5 to 8, insertion layers A1 to A4 are provided between the source electrodes S1 to S4 and the channel layers C1 to C4, and between the drain electrodes D1 to D4 and the channel layers C1 to C4. In this case, the manufacturing process may be simplified rather than forming an asymmetric source / drain structure as shown in FIGS. 1 to 4. In this case, the threshold voltage of the transistor may be controlled by the insertion layers A1 to A4 between the source electrodes S1 to S4 and the channel layers C1 to C4. This is because the threshold voltage of the transistor may depend on the potential barrier of the source electrodes S1 to S4 supplied with charge (electrons or holes) rather than the potential barrier of the drain electrodes D1 to D4.

As shown in FIGS. 1 to 4, a transistor having an asymmetric source / drain structure, that is, a transistor in which an insertion layer A1 to A4 is selectively provided only between the source electrodes S1 to S4 and the channel layers C1 to C4, is provided. 5 to 8 may be advantageous in terms of mobility than transistors of a symmetric source / drain structure. This is because in the transistor of the asymmetrical source / drain structure, the potential barrier on the drain electrodes D1 to D4 is low, so that the charge can be better escaped to the drain electrodes D1 to D4.

FIG. 13 is a graph illustrating gate voltage (Vg) and drain current (Id) characteristics of a transistor according to an embodiment of the present invention and a comparative example. Here, the transistor according to the embodiment has the structure of FIG. 5, but uses a GaInZnO layer as the channel layer C1 and an IZO layer as the insertion layer A1. The channel layer (GaInZnO layer) and the insertion layer (IZO layer) are both n-type oxide semiconductor layers, and the concentration of n-type carriers in the insertion layer (IZO layer) is relatively lower than that of the channel layer (GaInZnO layer). Characteristics were evaluated for the case where the thickness of the intercalation layer (IZO layer) was 50 ms and 130 ms. On the other hand, characteristics of the transistor (that is, the transistor according to the comparative example) without using the insertion layer were also evaluated. The transistor according to the comparative example has the same configuration as the transistor according to the above embodiment except that no insertion layer is used. The graph of the first group G1 is the result for the transistor according to the comparative example, and the graph of the second and third groups G2 and G3 is the result for the transistor according to the embodiment. The graph of the second group G2 is a case where the thickness of the intercalation layer (IZO layer) is 50 ms, and the graph of the third group G3 is a case where the thickness of the intercalation layer (IZO layer) is 130 ms.

Referring to FIG. 13, it can be seen that the graphs of the first group G1, which are the result of the transistor according to the comparative example without using the insertion layer, are turned on at a considerably low voltage. On the other hand, the graphs of the second and third groups G2 and G3, which are the results of the transistor according to the embodiment using the insertion layer, are located substantially to the right of the graph of the first group G1. This shows that when using the insertion layer, the threshold voltage increases in the positive direction. On the other hand, the graph of the third group G3 is located on the right side than the graph of the second group G2, which shows that the thicker the thickness of the insertion layer, the greater the effect of increasing the threshold voltage.

Additionally, another method for increasing the threshold voltage may be a method of forming a source electrode with a material (metal) forming a Schottky junction with a channel layer, but using an n-type oxide channel layer and a Schottky junction. In order to form a metal, a metal having a very high work function (about 4.5 to 4.7 eV or more) should be used. Therefore, the type of metal that can be used as the source electrode may be very limited. In addition, most of the metal having a high work function is expensive as a precious metal, and there is a problem that etching is difficult. In addition, when the Schottky junction is used, it is difficult to ensure uniformity of inter-transistor characteristics and a relatively large leakage current is generated. However, as in the embodiment of the present invention, when the threshold voltage is increased using the semiconductor insertion layer, the selection of the source / drain electrode materials can be expanded, and etching problems, non-uniformity of properties, leakage Current problems can be prevented or minimized.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art will appreciate that the idea of the present invention may be applied to other transistors other than thin film transistors. In addition, it will be appreciated that the components and structures of the transistors of FIGS. 1 to 8 may be diversified and modified, respectively. As a specific example, the transistor according to the embodiment of the present invention may have a double gate structure, and may use a channel layer formed of non-oxide. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 to 4 are cross-sectional views illustrating transistors of an asymmetric source / drain structure according to an embodiment of the present invention.

5 through 8 are cross-sectional views illustrating transistors having a symmetric source / drain structure according to another exemplary embodiment of the present invention.

9 is an energy band diagram of a source electrode, an insertion layer and a channel layer of a transistor according to an embodiment of the present invention.

10 is an energy band diagram of a source electrode and a channel layer of a transistor according to a first comparative example.

11 is an energy band diagram of a source electrode, an insertion layer, and a channel layer of a transistor according to another embodiment of the present invention.

12 is an energy band diagram of a source electrode and a channel layer of a transistor according to a second comparative example.

FIG. 13 is a graph illustrating gate voltage (Vg) and drain current (Id) characteristics of a transistor according to an embodiment of the present invention and a comparative example.

* Explanation of Signs of Major Parts of Drawings *

A1 to A4: insertion layer C1 to C4: channel layer

D1 to D4: Drain electrode G1 to G4: Gate electrode

H1, H1 ', H2, H2': hole GI1 to GI4: gate insulating layer

S1 to S4 Source electrodes SUB1 to SUB4 Substrates

Claims (16)

A channel layer comprising an oxide semiconductor; A gate electrode corresponding to the channel layer; Source and drain electrodes in contact with both ends of the channel layer, respectively; And And a semiconductor insertion layer provided between the channel layer and the source electrode. And a potential barrier between the channel layer and the source electrode is increased by the semiconductor insertion layer. The method of claim 1, The channel layer is n-type, And a work function of the semiconductor insertion layer is greater than a work function of the channel layer. The method of claim 2, The n-type carrier concentration of the semiconductor insertion layer is lower than the n-type carrier concentration of the channel layer. The method of claim 1, The channel layer is p-type, And a work function of the semiconductor insertion layer is smaller than a work function of the channel layer. The method of claim 4, wherein And a p-type carrier concentration of the semiconductor insertion layer is lower than a p-type carrier concentration of the channel layer. The method of claim 1, The channel layer is any one or a series selected from the group consisting of ZnO, GaO, InO, SnO, CdO, CaO, AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO and mixtures thereof A transistor comprising an oxide semiconductor. The method of claim 6, The channel layer is a transistor formed of a ZnO-based oxide semiconductor. The method of claim 7, wherein The ZnO-based oxide semiconductor further comprises at least one element selected from the group consisting of In, Ga, Sn, Ti, Zr, Hf, Y and Ta. 7. The method according to claim 1 or 6, The semiconductor insertion layer is SiC, AlN, GaN, InN, AlP, GaP, InAs, GaAs, AlAs, InSb, GaSb, ZnS, CdS, ZnTe, CdTe, CdSe, CdS, ZnO, GaO, InO, SnO, CdO, CaO And a compound comprising any one or a series of compounds selected from the group consisting of AlO, TiO, TaO, NbO, LnO, HfO, ZrO, YO, NiO, CuO, and mixtures thereof. The method of claim 1, And the semiconductor insertion layer has an energy band gap of 0.5 to 4.0 eV. The method of claim 1, The semiconductor insertion layer has a thickness of 1 to 300 GHz. The method of claim 1, The transistor is in an enhancement mode. The method of claim 1, The semiconductor insertion layer is a first semiconductor insertion layer, And a second semiconductor insertion layer between the channel layer and the drain electrode. The method of claim 13, And the first and second semiconductor insertion layers are the same material layer. The method of claim 1, The transistor is a thin film transistor having a top-gate structure. The method of claim 1, The transistor is a thin film transistor having a bottom-gate structure.

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