KR20110074171A - Apparatus and method for driving plasma display panel - Google Patents

Abstract

PURPOSE: An apparatus and a method for driving a plasma display panel are provided to reduce power consumption by changing an address order or forcedly reducing an address switching number in an inputted image. CONSTITUTION: A first calculation unit(903) produces a switching number of an address electrode when a scan electrode is scanned to a progressive scan mode. A second calculation unit(904) produces a switching number of the address electrode when the scan electrode is scanned to an interlaced scan method. A comparison unit(905) compares the switching number produced from the first calculation unit with the switching number produced from the second calculation unit. The comparison unit determines the scan mode having the small switching number between the progressive scan mode and the interlaced scan method. A plurality of address electrodes and a plurality of scan electrodes are arranged in a shape of an array.

Description

Apparatus and method for driving plasma display panel}

Embodiments relate to an apparatus and a method for driving a plasma display panel (PDP).

A plasma display panel (PDP) is an apparatus that displays an image using visible light generated from a phosphor when ultraviolet rays generated by gas discharge excite the phosphor. Such a PDP generally has a structure in which an upper substrate and a lower substrate are sealed.

1 is a configuration diagram of a conventional PDP. Referring to FIG. 1, scan electrodes Y1 to Yn and sustain electrodes Z are provided on an upper substrate of the PDP, and address electrodes X1 to Xm are provided on a lower substrate. In addition, discharge cells 1 are provided at a portion where the scan electrode and the sustain electrode cross each other.

2 is a reference diagram illustrating a principle of implementing an image of a plasma display panel. Referring to FIGS. 1 and 2, the PDP adopts a method of time division driving by dividing one frame into several subfields having different emission counts in order to realize gray scale of an image. Each subfield is divided into a reset period for uniformly generating a discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed in 256 gradations, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields SF1, SF2, ..., SF8 is divided into a reset period, an address period, and a sustain period as shown in FIG. Here, the reset time and address period of each subfield are the same for each subfield.

The address discharge for selecting the cell to be discharged is caused by the voltage difference between the address electrodes X1, X2, ..., Xm and the transparent electrodes which are the scan electrodes Y1, Y2, ..., Yn. There are two methods for generating an address discharge in an address period, a sequential scan method and an interlaced scan method. A sequential scan method is a method of sequentially scanning scan electrodes, and an interlaced scan method scans the scan electrodes in odd-numbered lines (Y1, Y3, Y5 ..). .) And even lines (Y2, Y4, Y6, ...) to scan odd lines first and then even lines alternately. On the other hand, the sustain period and the number of discharges thereof are increased at a ratio of 2 ⁿ (n = 0, 1, 2, 3, 4, 5, 6, 7) in each subfield in proportion to the number of sustain pulses. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

3 is a diagram for describing a method of sequentially scanning in a full white display. The input image of the PDP undergoes inverse gamma correction and is replaced with the address ON / OFF value of the address period. As shown in FIG. 3, in the method of sequentially scanning when the input image is full white, the address electrode is turned on once at the start of the scan and then turned off at the end of the scan so that the address switching is performed twice (low-). high, high-low), and thus the switching current is not large.

On the other hand, FIG. 4 is a diagram for describing a method of sequentially scanning in a 1 line ON & 1 line OFF pattern display. As shown in FIG. 4, when the input image is 1 line ON & 1 line OFF, the address electrode repeatedly turns ON / OFF every line when each line is sequentially scanned, and the address switching increases considerably. Accordingly the switching current is increased. That is, as the resolution becomes larger, the address switching current increases because more address electrodes and more scan lines increase. In addition, when the switching current increases, power consumption increases, heat generation of the device affects the reliability of the device, and even beyond the allowable range, there is a problem that the driving circuit is shut down.

According to an aspect of the present invention, a method of driving a plasma display panel for reducing power consumption, preventing deterioration of image quality, and protecting a driving circuit from shutdown by changing address order or forcibly reducing the number of address switching in an input image. It is about.

A driving device of a plasma display panel (PDP) according to an aspect of the present invention is a driving device of a plasma display panel including a plurality of address electrodes and a plurality of scan electrodes arranged in an array form. A first calculator configured to calculate the number of switching of the address electrodes when the scan electrodes are scanned in a sequential scan manner; A second calculator configured to calculate the number of switching of the address electrodes when the plurality of scan electrodes are scanned in an interlaced manner; And a comparing unit comparing the number of switches calculated by the first calculator and the number of switches calculated by the second calculator to determine a scan method having a smaller number of switches among the sequential scan method and the interlaced scan method.

A driving method of a plasma display panel according to another aspect of the present invention is a driving method of a plasma display panel including a plurality of address electrodes and a plurality of scan electrodes arranged in an array form, wherein the plurality of scan electrodes are sequentially scanned. Calculating (a) the number of switching of said address electrodes when being scanned; Calculating a number of switching of the address electrodes when the plurality of scan electrodes are scanned in an interlaced scan manner; And (c) comparing the number of switches calculated in step (a) and the number of switches calculated in step (b) to determine a scan method having a lower number of switching among the sequential scan method and the interlaced scan method. It is composed.

The driving method of the plasma display panel according to an aspect of the present invention can reduce the power consumption, prevent deterioration of image quality and protect the driving circuit from shutdown by changing the address order in the input image or by forcibly reducing the number of address switching. have.

Hereinafter, with reference to the accompanying drawings looks at in detail with respect to the preferred embodiment of the present invention.

5 is a diagram illustrating a method of driving a plasma display panel (PDP) according to an embodiment of the present invention. The method shown in FIG. 5 is presented as an example, and each step is not necessarily in order. In addition, each step may be slightly changed or modified according to the present invention.

Basically, when the input image comes in, the driving method predicts the number of address switching to determine whether to perform a sequential scan method or an interlace scan method. If the value is more than the set value, a method of forcibly reducing the number of address switching to protect the driving circuit.

Referring to FIG. 5, the PDP driving method according to an exemplary embodiment of the present invention first calculates the number of address switching in the sequential scan method (S501) and calculates the number of address switching in the interlaced scan method (S502).

The method of calculating the number of address switching is as follows. There is a method of calculating the number of address switching by comparing a scale value of an arbitrary line of an image and a next line. In the case of the sequential scan method, it can be predicted that a lot of switching occurs when the difference is large by comparing the input gray values of the nth line and the n + 1th line. In the interlaced scan method, the gray value of the nth line is compared with the gray value of the n + 2th line, and the cells having a large difference are added. Here, a large difference means that the difference is greater than or equal to a threshold set by the user so as not to lose an error in the driving circuit.

In this way, for example, in the case of a one-line ON / OFF pattern, the address electrodes are switched in every scan, which is proportional to the number of panel scan electrodes. If the resolution is XGA-class 1024x768, the number of switching per electrode in one subfield in the one-line ON / OFF pattern is 768 times. One screen of one subfield is 768 x 1024 (horizontal resolution) x 3 (RGB), and when this is calculated as one frame of an image, it is doubled by the number of subfields.

The 1-line ON / OFF pattern can be interlaced to reduce the number of switching and power consumption in the address period. For example, if the 1-line ON / OFF pattern turns on the pixels on odd lines and the cells on even lines turn off, the interlaced scan method addresses the first odd lines first and the next even lines. As a result, the switching of the address electrode occurs twice.

On the other hand, the two-line ON / OFF pattern is different. Addressing the two-line ON / OFF pattern by the interlaced scan method has the effect of addressing the one-line ON / OFF pattern by the sequential scan method. In this case, when addressing by interlaced scanning, the number of address switching is equal to the number of vertical lines, and when addressing by sequential scanning, the number of address switching decreases in half.

Returning to FIG. 5 again, as described above, after calculating the number of address switching in the sequential scan method and the number of address switching in the interlaced scan method (S501, S502), the two address switching numbers are compared (S503). )do. Next, the method with the smaller calculation result is selected (S505). In this way, addressing switching can be reduced. In general, only the methods described so far can easily reduce address switching. However, there are cases where it is difficult to reduce the addressing switching only with this method, which will be described below.

6 is a view showing an image of a two-line ON / 1 line OFF pattern. Such an image or its inverted image has almost the same number of switching when addressing with interlaced scanning and the number of switching when addressing with sequential scanning and the number of switching is not small. For example, in the case of XGA resolution 1024x768, when scanning in sequential scan or addressing by interlaced scan, the number of switching of the address electrode is similar to 512. In any addressing method, a lot of addressing switching causes a lot of current to flow. However, even in the interlaced scan method or the sequential scan method, there is a need for a method of protecting the driving circuit while minimizing deterioration of image quality for an image having a lot of address switching.

Referring back to FIG. 5, the present embodiment determines whether the number of address switching in the sequential scan method and the number of address switching in the interlaced scan method is greater than or equal to a preset upper limit value (S504), that is, the above-mentioned upper limit value. When it is impossible to solve simply by selecting the addressing method as in the case of the 2-line ON / 1 line OFF pattern, the number of addressing switching can be forcibly reduced (S506).

The predetermined upper limit means a value preset by the user so that the driving circuit can operate stably without causing an error even when input to the driving circuit.

In the present embodiment, the number of address switching can be reduced by selecting the number of addressing electrodes in one subfield. For example, the number of electrodes addressed can be selected in half in one subfield.

7 and 8 are diagrams for selecting half the number of the addressing electrode in one subfield. Referring to FIGS. 7 and 8, that is, as shown in FIG. 7, in the odd subfield, only the odd address electrodes are addressed and the even address electrodes are not addressed. In the field, only the even address electrodes are addressed and the odd address electrodes are not addressed. For example, only odd-numbered electrodes are displayed in the first subfield, only even-numbered electrodes are displayed in the second subfield, only odd-numbered electrodes are displayed in the third subfield, and only even-numbered electrodes are displayed in the fourth subfield. . The remaining subfields are displayed in the same manner.

At this time, the weights of the paired subfields are equalized to display a natural screen. In other words, the number of sustains in the first subfield and the second subfield are the same, and the number of sustains in the second subfield and the third subfield are the same. Otherwise, the brightness of the address odd and even electrodes may be different, and a distorted image may be displayed. In this way, the number of address discharges in one subfield can be reduced by half, thereby reducing power consumption.

Steps S504 and S506 are steps that can be selectively performed when it cannot be solved simply by selecting an addressing method as in steps S501 to S505, and according to an embodiment of the present invention. However, the steps may be omitted or changed, and are not necessarily steps to be performed.

9 is a block diagram of a system for implementing a method of driving a PDP according to an embodiment of the present invention. As shown in FIG. 9, the entire system for implementing the PDP driving method of the present invention includes a signal receiver 901, a driving circuit 900, a timing controller 906, a memory controller 907, an APL, a gamma, A weight correction unit 908 and a data array unit 909 are included. Here, the driving circuit 900 includes a two-line buffer unit 902, a sequential data calculation unit 903, an interlaced data calculation unit 904, and a comparison unit 905.

The signal receiver 901 serves to receive digital image data, that is, input image RGB data input through a video board of the PDP, and the two-line buffer unit 902 receives the input image RGB data. Line buffering Two-line buffering is performed to generate a one-line buffered image and a two-line buffered image, which will be described with reference to FIGS. 10A and 10B.

FIG. 10A is a timing diagram for describing two-line buffering of the two-line buffer unit. FIG. Referring to FIG. 10A, the two-line buffer unit first divides the input image RGB data 1001 into odd line data and even line data. The even line data is stored in the even line memory 1003 in accordance with the even signal of the line sync signal 1002, and the data stored in the even line memory 1003 is read for every line sync signal 1002. The odd line data is stored in the odd line memory 1004 in accordance with the odd signal of the line sync signal 1002, and the data stored in the odd line memory 1004 is read for every line sync signal 1002.

10B is a block diagram illustrating a two-line buffered result. Referring to FIG. 10B, the input image RGB data 1001 is divided into odd line data 1005 and even line data 1006 and input to odd line memory 1004 and even line memory 1003, respectively.

At this time, when the line sync signal is an even signal, the even line memory 1003 outputs even two-line buffered data 1010, and the odd line memory 1004 outputs odd one-line buffered data 1007. When the line synchronization signal is an odd signal, odd two-line buffered data 1008 is output from the odd line memory 1004, and even one-line buffered data 1009 is output from the even line memory 1003.

That is, referring again to FIGS. 10A and 10B, one-line buffered image data is read from the odd line memory 1004 at the even signal of the line sync signal, and read from the even line memory 1003 at the odd signal. . Therefore, since the one-line buffered image data starts when the line sync signal is two, the image data becomes one line delayed compared to the input image RGB data 1001.

Also, the two-line buffered image data is read from the even line memory 1003 in the even signal of the line sync signal, and from the odd line memory 1004 in the odd signal. Therefore, since the two-line buffered image data starts when the line synchronization signal is three, the two-line buffered image data becomes a two-line delayed image compared to the input image RGB data 1001.

Referring back to FIG. 9, the one-line buffered image data is input to the sequential data calculator 903, and the two-line buffered image data is input to the interlaced data calculator 904.

The sequential data calculator 903 roughly calculates the number of switching of the address electrodes when addressed in the sequential scan method. For accurate prediction, the weighted subfield data can be compared for each subfield. The RGB image data input first and the one-line buffered image data value are compared and counted when the difference between the data values is greater than or equal to a preset threshold. The reason for counting only above the preset threshold is to apply the present invention only to a special image that causes a lot of addressing switching. On the other hand, for example, a screen having an XGA resolution of 1024x768, the calculated value may be 768x1024x3 because the maximum number of switching per address electrode is 768 and the number of electrodes is 1024x3 (RGB).

The interlaced data calculator 904 roughly calculates the number of switching of the address electrodes when addressed by interlaced scanning. The first RGB image data and the second line buffered image data are compared and counted when the difference in data value is greater than or equal to a preset threshold.

The comparison unit 905 compares the sum of the switches calculated in the sequential data calculator 903 with the sum of the switches calculated in the interlaced data calculator 904 to determine an addressing method having a small value. For example, when the number of switching sums added by the sequential scan method is smaller, a signal of '0' is generated. When the number of switching sums is smaller by the interlaced scan method, a signal of '1' is generated. The determined signal is input to the timing controller 906 for controlling the scan electrodes and the memory controller 907 for arranging data in the scanning order.

If the smaller of the value calculated by the sequential scan method and the value calculated by the interlaced scan method is greater than or equal to a preset upper limit value, an address block signal is generated. Since the small value is larger than the preset upper limit value, the image causes a lot of address switching even when operated in the sequential scan method or interlaced scan method. In this case, it is necessary to forcibly reduce the number of addressing electrodes. When the compared small value is greater than or equal to the preset upper limit value, the address block signal is set to '1', otherwise it is set to '0'.

The address block signal is input to the APL, GAMMA, and weight correction unit 908 to change the APL, gamma, and weight values. The APL corrector for determining the number of sustains allows the number of sustains of the subfields to be paired when an address block signal is input. The weight correction unit selects a weight table having the same weight among the subfields to be a pair. The gamma correction unit selects a gamma table matched with the weight table to be resolved.

When the address block signal enters '1', the data array unit 909 processes the address electrode data as '0' according to the corresponding subfield. That is, for example, when the address block signal is '0' (normal video), the data is processed normally, and when the address block signal is '1', the even-numbered address data is '0' in the odd subfield. In the even-numbered subfield, odd-numbered address data is treated as '0' so that only half of the screen can be operated during one period of the subfield. When the number of address switching is finally calculated, the input of one image data is completed. Therefore, when displayed in the next frame, the data array unit 909 may block the address electrode.

While specific embodiments of the present invention have been illustrated and described, the technical spirit of the present invention is not limited to the accompanying drawings and the above description, and various modifications can be made without departing from the spirit of the present invention. It will be apparent to those skilled in the art, and variations of this form will be regarded as belonging to the claims of the present invention without departing from the spirit of the present invention.

1 is a block diagram of a conventional plasma display panel.

2 is a reference diagram illustrating a principle of implementing an image of a plasma display panel.

3 is a diagram for describing a method of sequentially scanning in a full white display.

4 is a diagram for describing a method of sequentially scanning in a one line ON & one line OFF pattern display.

5 is a diagram illustrating a method of driving a plasma display panel according to an embodiment.

6 is a view showing an image of a two-line ON / 1 line OFF pattern.

FIG. 7 illustrates an image of a two-line ON / 1 line OFF pattern in which only the odd address electrodes are addressed and the even address electrodes are not addressed in the odd subfields.

FIG. 8 is a diagram illustrating an image of a 2-line ON / 1 line OFF pattern in which only even-numbered address electrodes are addressed and even-numbered address electrodes are not addressed in even-numbered subfields.

9 is a block diagram of a system for implementing a method of driving a plasma display panel according to an embodiment.

FIG. 10A is a timing diagram for describing two-line buffering of the two-line buffer unit. FIG.

10B is a block diagram illustrating a two-line buffered result.

Claims (7)

A driving apparatus of a plasma display panel including a plurality of address electrodes and a plurality of scan electrodes arranged in an array form, A first calculator configured to calculate the number of switching of the address electrodes when the plurality of scan electrodes are scanned in a sequential scan manner; A second calculator configured to calculate the number of switching of the address electrodes when the plurality of scan electrodes are scanned in an interlaced manner; And And a comparing unit comparing the number of switches calculated by the first calculator and the number of switches calculated by the second calculator to determine a scan method having a smaller number of switching among the sequential scan method and the interlaced scan method. Driving device of the plasma display panel. The method of claim 1, And a suppressor for reducing the number of switching when the number of switching calculated by the first calculator and the number of switching calculated by the second calculator are equal to or greater than a preset upper limit. A driving method of a plasma display panel including a plurality of address electrodes and a plurality of scan electrodes arranged in an array form, Calculating a number of switching of the address electrodes when the plurality of scan electrodes are scanned in a sequential scan manner; Calculating the number of switching of the address electrodes when the plurality of scan electrodes are scanned in an interlaced manner; And Comparing the number of switches calculated in step (a) and the number of switches calculated in step (b) to determine (c) a scan method having a lower number of switching among the sequential scan method and the interlaced scan method. A method of driving a plasma display panel. The method of claim 3, wherein And (d) reducing the number of switching when the number of switching calculated in step (a) and the number of switching calculated in step (b) are greater than or equal to a preset upper limit. 5. The method of claim 4, Step (d) is, And selecting the number of address electrodes partly in one subfield. The method of claim 3, wherein In the step (a), the number of switching of the address electrode is calculated by comparing the first RGB image data and the one-line buffered image data and counting the difference between the data values when the difference is greater than or equal to a preset threshold. How to drive the panel. The method of claim 3, wherein Step (b) is to compare the first RGB image data and the two line buffered image data value and count when the difference of the data value is more than a predetermined threshold value to calculate the number of switching of the address electrode How to drive the panel.

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