KR20110067844A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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KR20110067844A
KR20110067844A KR1020090124609A KR20090124609A KR20110067844A KR 20110067844 A KR20110067844 A KR 20110067844A KR 1020090124609 A KR1020090124609 A KR 1020090124609A KR 20090124609 A KR20090124609 A KR 20090124609A KR 20110067844 A KR20110067844 A KR 20110067844A
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layer
film
polysilicon layer
region
forming
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KR1020090124609A
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Korean (ko)
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김지혜
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve the HEIP(Hot Electron Induced Punch) property of a PMOS device by removing a part of a liner nitride film when forming a gate in a peri area. CONSTITUTION: In a method for manufacturing a semiconductor device, a pad polysilicon layer(130) is formed in a semiconductor board having a cell region and a peri area. The pad polysilicon layer and a semiconductor substrate are etched to form an element isolation region. After the liner nitride film and SOD film are formed successively on the element isolation region, being etched until the pad polysilicon layer is exposed to outside to form an element isolation layer(160). The insulating layer is formed in a front side including the element isolation film. The insulating layer is etched by a mask exposing the peri area to outside. After the pad polysilicon layer and liner nitride film are eliminated, the gate oxidation film(220) is deposited.

Description

반도체 소자의 제조 방법{Method for Manufacturing Semiconductor Device}Method for Manufacturing Semiconductor Device {Method for Manufacturing Semiconductor Device}

본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히, PMOS 소자의 특성을 개선하는 기술에 대한 것이다. The present invention relates to a method for manufacturing a transistor of a semiconductor device, and more particularly, to a technique for improving the characteristics of a PMOS device.

반도체 소자의 고속화 및 고집적화가 급속하게 진행되고 있고, 이에 수반하여 패턴의 미세화 및 패턴 치수의 고정밀화에 대한 요구가 높아지고 있다. 이는 활성 영역에 형성되는 패턴뿐만 아니라 상대적으로 넓은 영역을 차지하는 소자분리막에도 해당한다.High speed and high integration of semiconductor devices are rapidly progressing, and along with this, there is a demand for miniaturization of patterns and high precision of pattern dimensions. This is not only a pattern formed in the active region but also a device isolation layer occupying a relatively large region.

여기서, 기존의 소자분리막 형성 방법으로는 로코스(LOCOS) 공정을 이용하였으나, 상단 코너부에 새부리 형상의 버즈빅(bird's beak)이 발생하기 때문에 활성 영역의 크기를 감소시키는 단점과 함께 한계점이 드러나게 되었다. 따라서 현재 대부분의 반도체 소자는 활성 영역의 크기를 확보하여 고집적 소자의 구현을 가능하게 하는 STI(Shallow Trench Isolation) 공정을 이용하여 소자분리막을 형성하고 있다.Here, although the LOCOS process is used as a conventional method of forming an isolation layer, a bird's beak of a beak shape is generated at the upper corner, thereby reducing the size of the active region and revealing limitations. It became. Therefore, at present, most semiconductor devices form a device isolation layer by using a shallow trench isolation (STI) process, which secures the size of the active region to enable the implementation of highly integrated devices.

최근의 반도체 소자의 고집적화 추세에 따라, 활성 영역 사이의 필드 영역의 폭이 감소하고 필드 영역에 형성되는 트렌치의 종횡비가 증가하여 트렌치 내에 소 자분리막을 매립시키는 공정이 점점 어려워지고 있다. 따라서 소자분리막의 매립 특성을 향상시키기 위해 화학기상증착(CVD)방식으로 고밀도 플라즈마(HDP)를 사용한 산화막 대신 스핀 코팅(spin coating) 방식으로 증착되는 SOD(Spin on dielectric) 물질을 이용하여 트렌치를 매립하는 기술이 제안되었으나, 이러한 SOD 물질은 습식 식각률이 높고 불균일한 물질 특성을 가지고 있다.With the recent trend of higher integration of semiconductor devices, the width of the field region between the active regions decreases, and the aspect ratio of the trenches formed in the field region increases, making it increasingly difficult to embed the element separator in the trench. Therefore, in order to improve the buried characteristics of the device isolation layer, the trench is embedded by using a spin on dielectric (SOD) material deposited by spin coating instead of an oxide film using high density plasma (HDP) by chemical vapor deposition (CVD). The SOD material has been proposed, but the SOD material has high wet etching rate and non-uniform material properties.

특히, PMOS 소자의 경우, 활성 영역의 라이너 질화막에 전자들이 트랩(trap) 되어 상기 전자들이 PMOS 소자의 홀을 끌어당기어 문턱 전압(Vt)을 낮추고 트랜지스터의 특성을 열화시키는 문제점이 있다.In particular, in the PMOS device, electrons are trapped in the liner nitride layer of the active region, and the electrons attract holes of the PMOS device to lower the threshold voltage Vt and deteriorate the characteristics of the transistor.

본 발명은 셀 영역의 매립 게이트와 페리 영역의 게이트 형성 시, 셀 영역의 매립 게이트 형성 후, 페리 영역에 게이트 형성 시 라이너(Liner) 질화막의 일부를 제거해줌으로써 PMOS 소자의 HEIP(Hot Electron Induced Punch) 특성을 개선할 수 있는 반도체 소자의 제조 방법을 제공한다.The present invention removes a portion of the liner nitride film during the formation of the buried gate of the cell region and the gate of the ferry region, and removes a part of the liner nitride film when forming the gate of the ferry region. Provided is a method of manufacturing a semiconductor device capable of improving characteristics.

본 발명은 셀 영역 및 페리 영역이 구비된 반도체 기판상에 패드 폴리실리콘층을 형성하는 단계, 상기 패드 폴리실리콘층 및 상기 반도체 기판을 식각하여 소자 분리 영역을 형성하는 단계, 상기 소자 분리 영역 상부에 라이너 질화막 및 SOD막을 순차적으로 형성한 후, 상기 패드 폴리실리콘층이 노출될 때까지 평탄화 식각하여 소자 분리막을 형성하는 단계, 상기 소자분리막을 포함한 전면에 절연막을 형성하는 단계, 상기 페리 영역을 노출시키는 마스크로 상기 절연막을 식각하는 단계 및 상기 패드 폴리실리콘층 및 상기 라이너 질화막을 제거한 후, 게이트 산화막을 증착하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.According to an embodiment of the present invention, a pad polysilicon layer is formed on a semiconductor substrate having a cell region and a ferry region. After forming the liner nitride film and the SOD film sequentially, forming a device isolation layer by planarizing etching until the pad polysilicon layer is exposed, forming an insulating film on the entire surface including the device isolation film, exposing the ferry region And etching the insulating film with a mask, removing the pad polysilicon layer and the liner nitride film, and depositing a gate oxide film.

바람직하게는, 상기 반도체 기판과 상기 패드 폴리실리콘층 사이에 패드 산화막 및 패드 질화막을 형성하는 단계를 포함한다.Preferably, forming a pad oxide film and a pad nitride film between the semiconductor substrate and the pad polysilicon layer.

바람직하게는, 상기 절연막은 산화막(Oxide) 또는 질화막(Nitride)으로 형성하는 것을 특징으로 한다.Preferably, the insulating film is formed of an oxide film or a nitride film.

바람직하게는, 상기 패드 폴리실리콘층은 건식 또는 습식 식각 공정을 이용 하여 제거하는 것을 특징으로 한다.Preferably, the pad polysilicon layer is removed using a dry or wet etching process.

바람직하게는, 상기 라이너 질화막은 습식 클리닝 공정을 이용하여 제거하는 것을 특징으로 한다.Preferably, the liner nitride film is removed using a wet cleaning process.

바람직하게는, 상기 소자 분리막을 형성하는 단계 후, 상기 셀 영역에 매립 게이트를 형성하는 단계를 더 포함한다.The method may further include forming a buried gate in the cell region after forming the device isolation layer.

본 발명은 셀 영역의 매립 게이트와 페리 영역의 게이트 형성 시, 셀 영역의 매립 게이트 형성 후, 페리 영역에 게이트 형성 시 라이너(Liner) 질화막의 일부를 제거해줌으로써 PMOS 소자의 HEIP(Hot Electron Induced Punch) 특성을 개선할 수 있는 장점이 있다.The present invention removes a portion of the liner nitride film during the formation of the buried gate of the cell region and the gate of the ferry region, and removes a part of the liner nitride film when forming the gate of the ferry region. There is an advantage to improve the characteristics.

이하, 첨부한 도면을 참조하여 본 발명의 실시 예에 대해 상세히 설명하고자 한다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들로서, (ⅰ)은 셀 영역을 도시한 것이고, (ⅱ)은 페리 영역을 도시한 것이다.1A to 1E are cross-sectional views showing a method of manufacturing a semiconductor device according to the present invention, (i) shows a cell region, and (ii) shows a ferry region.

도 1a를 참조하면, 셀 영역 및 페리 영역이 구비된 반도체 기판(100) 상부에 패드 산화막(110), 패드 질화막(120), 패드 폴리실리콘층(130) 및 소자 분리 영역을 한정하는 감광막 패턴(미도시)을 차례로 형성한다.Referring to FIG. 1A, a photoresist layer pattern defining a pad oxide layer 110, a pad nitride layer 120, a pad polysilicon layer 130, and an isolation region may be formed on a semiconductor substrate 100 having a cell region and a ferry region. Not shown).

상기 감광막 패턴을 마스크로 상기 패드 폴리실리콘층(130), 패드 질화막(120), 패드 산화막(110) 및 반도체 기판(100)을 식각하여 활성 영역(140)을 정 의하는 소자 분리 영역(미도시)을 형성한다.An isolation region (not shown) defining the active region 140 by etching the pad polysilicon layer 130, the pad nitride layer 120, the pad oxide layer 110, and the semiconductor substrate 100 using the photoresist pattern as a mask. ).

상기 소자 분리 영역에 라이너(Liner) 질화막(150) 및 SOD막을 순차적으로 증착한 후, 상기 패드 폴리실리콘층(130)이 노출될 때까지 평탄화 식각(Chemical Mechanical Polishing) 공정을 실시하여 소자분리막(160)을 완성한다.After sequentially depositing a liner nitride film 150 and an SOD film on the device isolation region, the device isolation layer 160 may be formed by performing a chemical mechanical polishing process until the pad polysilicon layer 130 is exposed. To complete).

이후, 소자분리막(160)을 포함한 전면에 제 1 질화막(Nitride, 170)을 증착한 후, 제 1 질화막(170)을 포함한 전면에 감광막을 형성한 후, 셀 영역(1000a)을 노출시키는 매립 게이트 마스크를 이용하여 상기 제 1 질화막(170), 패드 폴리실리콘층(130), 패드 질화막(120), 패드 산화막(110) 및 활성 영역(140)을 식각하여 매립 게이트 영역(미도시)을 형성한다.Subsequently, after the first nitride film 170 is deposited on the entire surface including the device isolation layer 160, the photoresist film is formed on the entire surface including the first nitride film 170, and the buried gate exposing the cell region 1000a. A buried gate region (not shown) is formed by etching the first nitride layer 170, the pad polysilicon layer 130, the pad nitride layer 120, the pad oxide layer 110, and the active region 140 using a mask. .

상기 매립 게이트 영역에 도전 물질 및 SOD 물질을 증착한 후, 평탄화 식각하여 매립 게이트(180)를 형성한다.After the conductive material and the SOD material are deposited in the buried gate region, the buried gate 180 is formed by planarization etching.

다음에는, 셀 영역의 매립 게이트(180) 및 페리 영역을 포함한 전면에 제 2 질화막(190), 산화막(200) 및 제 3 질화막(210)을 순차적으로 증착한다.Next, the second nitride film 190, the oxide film 200, and the third nitride film 210 are sequentially deposited on the entire surface including the buried gate 180 and the ferry region of the cell region.

도 1b를 참조하면, 제 3 질화막(210)을 포함한 전면에 감광막을 형성한 후, 페리 영역을 노출하는 마스크를 이용한 노광 및 현상 공정으로 감광막 패턴(220)을 형성한다.Referring to FIG. 1B, after the photoresist film is formed on the entire surface including the third nitride film 210, the photoresist pattern 220 is formed by an exposure and development process using a mask exposing a ferry region.

상기 패드 폴리실리콘층(130)이 노출될 때까지 감광막 패턴(220)을 마스크로 페리 영역의 제 3 질화막(210), 산화막(200), 제 2 질화막(190) 및 제 1 질화막(170)을 식각한다.The third nitride film 210, the oxide film 200, the second nitride film 190, and the first nitride film 170 of the ferry region are covered using the photoresist pattern 220 as a mask until the pad polysilicon layer 130 is exposed. Etch it.

도 1c 및 도 1d를 참조하면, 페리 영역의 패드 폴리실리콘층(130)을 제거한 다. 이때, 패드 폴리실리콘층(130)은 건식(Dry) 또는 습식(Wet) 식각 공정을 이용하여 제거한다. 이후, 습식 클리닝 방법을 이용하여 'A'와 같이 상기 라이너 질화막(150)을 제거한다. 여기서, 라이너 질화막(150)을 제거한 후, 패드 폴리실리콘층(130)을 제거할 수도 있다.1C and 1D, the pad polysilicon layer 130 in the ferry region is removed. In this case, the pad polysilicon layer 130 is removed using a dry (dry) or wet (wet) etching process. Thereafter, the liner nitride layer 150 is removed using a wet cleaning method as in 'A'. Here, after removing the liner nitride film 150, the pad polysilicon layer 130 may be removed.

도 1e를 참조하면, 제거된 영역에 게이트 산화막(220)을 증착하거나, Vt 스크린 산화막을 증착할 수 있다.Referring to FIG. 1E, the gate oxide layer 220 may be deposited or the Vt screen oxide layer may be deposited on the removed region.

전술한 바와 같이, 본 발명은 셀 영역의 매립 게이트와 페리 영역의 게이트 형성 시, 셀 영역의 매립 게이트 형성 후, 페리 영역에 게이트 형성 시 라이너(Liner) 질화막의 일부를 제거해줌으로써 PMOS 소자의 HEIP(Hot Electron Induced Punch) 특성을 개선할 수 있는 장점이 있다.As described above, the present invention removes a part of the liner nitride film when forming the buried gate of the cell region and the gate of the ferry region, and after forming the buried gate of the cell region. Hot Electron Induced Punch) has the advantage of improving the characteristics.

아울러 본 발명의 바람직한 실시 예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다. It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

도 1a 내지 도 1e는 본 발명에 따른 반도체 소자의 제조 방법을 도시한 단면도들.1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (6)

셀 영역 및 페리 영역이 구비된 반도체 기판상에 패드 폴리실리콘층을 형성하는 단계;Forming a pad polysilicon layer on a semiconductor substrate having a cell region and a ferry region; 상기 패드 폴리실리콘층 및 상기 반도체 기판을 식각하여 소자 분리 영역을 형성하는 단계Etching the pad polysilicon layer and the semiconductor substrate to form a device isolation region 상기 소자 분리 영역 상부에 라이너 질화막 및 SOD막을 순차적으로 형성한 후, 상기 패드 폴리실리콘층이 노출될 때까지 평탄화 식각하여 소자 분리막을 형성하는 단계;Forming a device isolation layer by sequentially forming a liner nitride layer and an SOD layer on the device isolation region, and then planarizing etching until the pad polysilicon layer is exposed; 상기 소자분리막을 포함한 전면에 절연막을 형성하는 단계;Forming an insulating film on the entire surface including the device isolation film; 상기 페리 영역을 노출시키는 마스크로 상기 절연막을 식각하는 단계; 및Etching the insulating film with a mask exposing the ferry region; And 상기 패드 폴리실리콘층 및 상기 라이너 질화막을 제거한 후, 게이트 산화막을 증착하는 단계Removing the pad polysilicon layer and the liner nitride layer, and then depositing a gate oxide layer 를 포함하는 반도체 소자의 제조 방법.Wherein the semiconductor device is a semiconductor device. 제 1 항에 있어서, The method of claim 1, 상기 반도체 기판과 상기 패드 폴리실리콘층 사이에 패드 산화막 및 패드 질화막을 형성하는 단계를 포함하는 반도체 소자의 제조 방법.Forming a pad oxide film and a pad nitride film between the semiconductor substrate and the pad polysilicon layer. 제 1 항에 있어서, The method of claim 1, 상기 절연막은 산화막(Oxide) 또는 질화막(Nitride)으로 형성하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the insulating film is formed of an oxide film or a nitride film. 제 1 항에 있어서, The method of claim 1, 상기 패드 폴리실리콘층은 건식 또는 습식 식각 공정을 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 제조 방법.The pad polysilicon layer is removed using a dry or wet etching process. 제 1 항에 있어서, The method of claim 1, 상기 라이너 질화막은 습식 클리닝 공정을 이용하여 제거하는 것을 특징으로 하는 반도체 소자의 제조 방법.And the liner nitride film is removed using a wet cleaning process. 제 1 항에 있어서, The method of claim 1, 상기 소자 분리막을 형성하는 단계 후, 상기 셀 영역에 매립 게이트를 형성하는 단계를 더 포함하는 반도체 소자의 제조 방법.And forming a buried gate in the cell region after forming the device isolation layer.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928073B2 (en) 2012-03-20 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor devices including guard ring structures
US10325802B2 (en) 2016-12-21 2019-06-18 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8928073B2 (en) 2012-03-20 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor devices including guard ring structures
US10325802B2 (en) 2016-12-21 2019-06-18 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device

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