KR20110064960A - Electrophoretic display - Google Patents

Abstract

PURPOSE: An electrophoresis display device is provided to prevent a picture quality due to a parasitic transistor. CONSTITUTION: An electrophoresis display device a display panel includes an upper array, an upper common electrode and pixel electrodes, a lower common electrode, a TFTs, and a lower array. A timing controller generates digital data which is displayed on the electrophoresis cells. A data driving circuit supplies the digital data to the data lines by converting the digital data into a data voltage. A gate driving circuit supplies a scan pulse to the gate lines. A common voltage generating circuit supplies a first common voltage to the upper common electrode by generating a reference level and supplies a second common voltage to the lower common electrode.

Description

Electrophoretic Display {Electrophoretic Display}

The present invention relates to an electrophoretic display device capable of preventing image degradation caused by parasitic transistors.

Conventional electrophoretic display (EPD) is excellent in flexibility and portability, and has electrophoresis (light electrophoresis) in which the charged particles move toward the anode or cathode in the electric field. It is a kind of flat panel display used.

An electrophoretic display is a display that forms a thin film transistor array on a thin, flexible base substrate such as plastic or metal foil, and drives electrophoretic floating particles by a vertical electric field between a pixel electrode of the thin film transistor array and an opposite common electrode. It is a display device that is also expected as a next generation electronic paper.

The electrophoretic display has an upper array and a lower array adhered to the upper array. The upper array is provided with an upper common electrode and an electrophoretic film positioned on the upper common electrode and including a plurality of capsules. Each of the capsules contains black and white particles charged with different polarities. In the lower array, a plurality of data lines and gate lines cross each other, and thin film transistors (hereinafter referred to as TFTs) for driving an electrophoretic cell are formed at each intersection thereof. In addition, a storage capacitor is formed in the lower array to maintain the voltage of the electrophoretic cell. The storage capacitor includes a pixel electrode and a lower common electrode which overlap each other with an insulating layer therebetween. The common voltage of the same level is applied to the lower common electrode and the upper common electrode. The charged particles of the electrophoretic film are driven by the potential difference between the common voltage applied to the upper common electrode and the data voltage applied to the pixel electrode, thereby realizing black or white while being divided into white particles and black particles.

The electrophoretic display device forms a storage capacitor larger than other display devices in order to improve unique memory characteristics. That is, the lower common electrode ECD overlapping the pixel electrode is largely formed as shown in FIG. 1. As a result, an active redundancy may be formed between the data line and the drain electrode of the TFT during the lower array forming process. The remaining semiconductor film may act as a charge transfer channel by a voltage applied between the lower common electrode ECD and the data line. Thus, a parasitic transistor can be formed between the data line and the drain electrode of the TFT by the remaining semiconductor film. In FIG. 1, "SUB" means lower substrate, "GI" means gate insulating film, and "n +" and "a-Si" mean semiconductor layer, respectively.

Typically, in an electrophoretic display, a scan pulse for driving a TFT is swinged between -20 V (turn off level) to 22 V (turn on level), and the data voltage applied to the pixel electrode through the data line is white gray. + 15V for display, -15V for black gradation display, 0V for initialization of charged particles prior to gradation display, and a common voltage applied to upper and lower common electrodes is 0V. The parasitic transistor Tc is turned on only when the voltage Vcd between the lower common electrode and the data line is greater than or equal to its threshold voltage.

As shown in FIG. 2A, when the data voltage Vdata of + 15V is applied to the data line, the voltage Vcd applied between the lower common electrode and the data line is applied to the parasitic transistor Tc. It is turned off because it is kept at -15V below the threshold voltage. In this case, image quality deterioration due to the parasitic transistor Tc does not occur. On the other hand, the parasitic transistor Tc has a voltage Vcd applied between the lower common electrode and the data line when a data voltage Vdata of -15V is applied to the data line for black gray display as shown in FIG. 2B. It is turned on because it is maintained at + 15V above its threshold voltage. According to the experiment, it can be seen that when the parasitic transistor Tc is turned on, the off current of the TFT increases as shown in FIG. 3. In Fig. 3, the vertical axis represents the current Id flowing through the drain electrode of the TFT, and the horizontal axis represents the voltage Vg applied to the gate electrode of the TFT. Since the upper and lower common electrodes are coupled to the TFT through the storage capacitor Cst, when the off current of the TFT increases, the common voltage Vcom applied to the upper and lower common electrodes also increases. By the increase of the common voltage Vcom, the black gradation is not displayed properly, and poor image quality such as white speckle occurs.

Accordingly, it is an object of the present invention to provide an electrophoretic display device capable of preventing deterioration of image quality due to parasitic transistors.

In order to achieve the above object, an electrophoretic display device according to an exemplary embodiment of the present invention includes an upper array having an upper common electrode and an electrophoretic film, data lines and gate lines intersecting each other, and the electrophoretic film at each intersection thereof. A display panel including pixel electrodes facing the upper common electrode, the lower common electrode overlapping the pixel electrodes, and a lower array having TFTs driving the electrophoretic cells; A timing controller for generating digital data to be displayed on the electrophoretic cells; A data driving circuit converting the digital data into a data voltage and supplying the digital data to the data lines; A gate driving circuit supplying scan pulses to the gate lines; And generating a first common voltage at a reference level and supplying it to the upper common electrode, and generating a second common voltage at the reference level or a first level lower than the reference level according to the polarity of the data voltage. And a common voltage generating circuit for supplying to the.

The upper common electrode and the lower common electrode are electrically separated.

The common voltage generation circuit determines the polarity of the data voltage with reference to the digital data, and generates the second common voltage at the reference level or the first level according to the determination result.

The common voltage generation circuit generates the second common voltage at the reference level when the digital data has a value corresponding to the positive polarity data voltage.

The common voltage generation circuit generates the second common voltage at the first level when the digital data has a value corresponding to the negative data voltage.

The common voltage generation circuit generates the second common voltage at the first level when any one of the digital data to be displayed on the electrophoretic cells has a value corresponding to the negative data voltage.

A parasitic transistor is formed between the data line and the pixel electrode by a potential difference between the data voltage and the second common voltage; The first level is determined within a voltage range capable of turning off the parasitic transistor during a period in which the negative data voltage is applied to the data line.

The first level is determined within a range in which the gate-source voltage of the parasitic transistor is lower than the threshold voltage of the parasitic transistor.

The electrophoretic display according to the present invention is formed by electrically separating the upper common electrode and the lower common electrode, supplying the first common voltage of the reference level to the upper common electrode constantly, and applying the polarity of the data voltage to the lower common electrode. Therefore, by supplying the second common voltage of the reference level or the first level lower than the reference level, the increase in the off current of the TFT due to the parasitic transistor is suppressed. As a result, the electrophoretic display according to the present invention can effectively prevent a problem of deterioration of image quality such as white spots caused by parasitic transistors during black gray scale display.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 10.

4 shows an electrophoretic display device according to an embodiment of the present invention.

Referring to FIG. 4, an electrophoretic display device according to an exemplary embodiment of the present invention may include a display panel 10, a timing controller 11, a data driver circuit 12, a gate driver circuit 13, and a common voltage generator circuit 14. ).

5 and 6, the display panel 10 includes an upper array, a lower array facing the upper array, and an adhesive layer ADH for adhering the upper and lower arrays. .

The lower array includes a plurality of gate lines G1 to Gn and data lines D1 to Dm that define an electrophoretic cell Cink by crossing the gate insulating layer GI therebetween on the lower substrate SUB2. And TFTs formed at each intersection to drive an electrophoretic cell (Cink), and a pixel electrode (EP) formed in the pixel region provided in the intersection structure. The TFT overlaps the gate electrode G connected to the gate line, the source electrode S connected to the data line, the drain electrode D connected to the pixel electrode EP, and the gate electrode G, and the source electrode ( A semiconductor layer ACT, which forms a channel between S) and the drain electrode D, is provided. The semiconductor layer ACT includes an active layer for forming a channel between the source electrode S and the drain electrode D, and an ohmic contact layer for ohmic contact between the source electrode S and the drain electrode D. FIG. The TFT selects one horizontal line of electrophoretic cells (Cinks) to be displayed by being turned on in response to a scan pulse from the gate line. The pixel electrode EP is in contact with the drain electrode D through the contact hole CT exposing the drain electrode D through the passivation layer PAS protecting the TFT.

The lower array further includes a storage capacitor Cst for maintaining the voltage of the electrophoretic cell Cink. The storage capacitor Cst includes the pixel electrode EP and the lower common electrode ECD that overlap each other with the insulating layers GI and PAS interposed therebetween. The second common voltage Vcom2 is applied to the lower common electrode ECD. Since the electrophoretic display is a reflective display and a memory function is important in view of its characteristics, the area occupied by the lower common electrode ECD in the pixel area is much larger than that of other display devices as shown in FIG. 6. As a result, an active redundancy (see FIG. 1) may be formed between the data line and the drain electrode D of the TFT during the lower array forming process. The remaining semiconductor film may act as a charge transfer channel by a voltage applied between the lower common electrode ECD and the data line. Accordingly, the parasitic transistor Tc may be formed between the data line and the drain electrode of the TFT by the semiconductor remaining film.

The upper array includes an upper common electrode ECU formed on the upper substrate SUB1 having flexibility, and an electrophoretic film FLM positioned on the upper common electrode ECU. The upper common electrode ECU includes a transparent conductive material through which light can pass, and is formed to be electrically separated from the lower common electrode ECD. The first common voltage Vcom1 is applied to the lower common electrode ECD. Electrophoretic film (FLM) comprises a plurality of capsules 20 consisting of charged particles. In the capsule 20, positively charged white particles 22 and negatively charged black particles 21 are mixed in a solvent. The charged particles are driven by the potential difference between the first common voltage Vcom1 applied to the upper common electrode ECU and the data voltage applied to the pixel electrode EP. The charged particles are divided into white particles 22 and black particles 21 in response to negative or positive data voltages, thereby implementing black or white.

The adhesive layer ADH bonds the lower array and the upper array. The upper and lower arrays are attached to each other such that the pixel electrode EP and the upper common electrode ECU are vertically opposed to each other with an electrophoretic film FLM interposed through a hot laminating process using a pressure roller.

The timing controller 11 receives a vertical / horizontal synchronization signal (V, H) and a clock signal (CLK) from an external system board (not shown) and receives a data control signal for controlling the operation timing of the data driving circuit 12. (DDC) and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13 are generated. The timing controller 11 compares an image of a previous frame and an image of a current frame stored in a plurality of memories for storing the first digital data Data 1 supplied from the system board and according to the comparison result. Second digital data corresponding to the driving waveform of the data voltage to be supplied to each electrophoretic cell during a plurality of frame periods by using a look-up table for determining a driving waveform of the plurality of frames and a frame counter for counting the number of frames. 2) is generated and the digital data (Data 2) is supplied to the data driving circuit (12). The data Data2 output from the lookup table is digital data such as '00', '01', '10', and '11', and voltages of three states supplied to the pixel electrode EP of each electrophoretic cell Cink. To indicate. '00' and '11' indicate 0V, '01' indicates + 15V, and '10' indicates -15V.

The data driver circuit 12 is composed of a plurality of data driver integrated circuits each including a shift register, a latch, a decoder, a level shifter, and the like. The data driving circuit 12 latches the second digital data Data2 under the control of the timing controller 11 and stores the digital data Data2 at an appropriate voltage, i.e., + 15V for white gray scale display, through a decoder and a level shifter. -15V for the black gradation display and 0V for the initialization of the charged particles prior to the gradation display are converted and supplied to the data lines D1 to Dm.

The gate driving circuit 13 includes a shift register and a level shifter for converting the swing width of the output signal of the shift register into a swing width suitable for driving the TFT, and an output buffer connected between the level shifter and the gate lines G1 to Gn. A plurality of gate drive integrated circuits each include. The gate driving circuit 13 sequentially supplies scan pulses synchronized with the data voltages supplied to the data lines D1 to Dm to the gate lines G1 to Gn under the control of the timing controller 11.

The common voltage generation circuit 14 generates the first common voltage Vcom1 at the reference level L0 and supplies it to the upper common electrode ECU as shown in FIG. 8. The common voltage generation circuit 14 determines the polarity of the data voltage Vdata with reference to the second digital video data Data2 from the timing controller 11 as shown in FIG. The voltage Vcom2 is generated at the reference level L0 or the first level L1 lower than the reference level L0 and supplied to the lower common electrode ECD. That is, the common voltage generation circuit 14 has a second common voltage when the second digital video data Data2 to be displayed on the electrophoretic cells Cink has a value of '01' corresponding to + 15V (positive polarity). Generates Vcom2 to the reference level L0. On the other hand, the common voltage generation circuit 14 has a second value when any one of the second digital video data Data2 to be displayed on the electrophoretic cells Cink has a value of '10' corresponding to −15V (negative polarity). The common voltage Vcom2 is generated at the first level L1. Since the gate potential of the parasitic transistor Tc is determined by the second common voltage Vcom2, the parasitic transistor Tc is applied to the first level L1 when a negative data voltage is applied to the data line for black gray display. Is determined within the range of voltages that can be turned off. In other words, the first level L1 is determined within a range in which the gate-source voltage of the parasitic transistor Tc is lower than the threshold voltage of the parasitic transistor Tc.

9A and 9B show an example in which the level of the second common voltage is differently applied according to the polarity of the data voltage.

As shown in FIG. 9A, when a data voltage Vdata of + 15V is applied to the data line for displaying white gray levels, the second common voltage Vcom2 is the same reference level as the first common voltage Vcom1 (ie, 0V) to the lower common electrode. The parasitic transistor Tc is turned off because its gate-source voltage, that is, the voltage Vcd applied between the lower common electrode and the data line is maintained at −15 V lower than its threshold voltage. In this case, image quality deterioration due to the parasitic transistor Tc does not occur.

As shown in FIG. 9B, when a data voltage Vdata of −15 V is applied to the data line for displaying a black gray level, the second common voltage Vcom2 may turn off the parasitic transistor Tc. The voltage is applied to the lower common electrode at a first level lower than the voltage Vcom1. For example, assuming that the threshold voltage of the parasitic transistor Tc is + 10V, the first level is a gate-source voltage of the parasitic transistor Tc, that is, the voltage Vcd applied between the lower common electrode and the data line is + 10V. It is applied with a value less than -5V to be less than. As a result, the parasitic transistor Tc is turned off and the increase in the off current of the TFT is suppressed as shown in FIG. In Fig. 10, the vertical axis represents the current Id flowing through the drain electrode of the TFT, and the horizontal axis represents the voltage Vg applied to the gate electrode of the TFT. When the increase in the off current of the TFT is suppressed, a problem of deterioration of image quality such as white speckle in black gradation display is effectively prevented.

As described above, the electrophoretic display according to the present invention is formed by electrically separating the upper common electrode and the lower common electrode, and supplying the first common voltage of the reference level to the upper common electrode constantly, By supplying the second common voltage of the reference level or the first level lower than the reference level in accordance with the polarity of the data voltage, an increase in the off current of the TFT due to the parasitic transistor is suppressed. As a result, the electrophoretic display according to the present invention can effectively prevent a problem of deterioration of image quality such as white spots caused by parasitic transistors during black gray scale display.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 illustrates an example in which a semiconductor residual film is formed in a process of forming an electrophoretic display.

2A illustrates an example in which a parasitic transistor is turned off in a conventional electrophoretic display.

2B is a diagram illustrating an example in which a parasitic transistor is turned on in a conventional electrophoretic display.

3 is a graph showing that the off current of the TFT is increased when the parasitic transistor is turned on.

4 illustrates an electrophoretic display device according to an embodiment of the present invention.

FIG. 5 is an assembled cross-sectional view of the display panel shown in FIG. 4.

FIG. 6 is a plan view of the bottom array shown in FIG. 5; FIG.

FIG. 7 shows the microcapsule structure of the cell shown in FIG. 5 in detail.

8 illustrates levels of first and second common voltages.

9A and 9B illustrate an example in which a parasitic transistor is turned off in an electrophoretic display according to an exemplary embodiment of the present invention.

10 is a graph showing that the off current increase of the TFT is suppressed due to the turn off of the parasitic transistor.

<Description of Symbols for Main Parts of Drawings>

10: display panel 11: timing controller

12: data driving circuit 13: gate driving circuit

14: common voltage generating circuit

Claims (8)

An upper array having an upper common electrode and an electrophoretic film, pixel electrodes facing the upper common electrode with the electrophoretic film intersecting each other and having the electrophoretic film therebetween; A display panel including an overlapping lower common electrode and a lower array on which TFTs for driving electrophoretic cells are formed; A timing controller for generating digital data to be displayed on the electrophoretic cells; A data driving circuit converting the digital data into a data voltage and supplying the digital data to the data lines; A gate driving circuit supplying scan pulses to the gate lines; And A first common voltage is generated at a reference level and supplied to the upper common electrode, and a second common voltage is generated at the reference level or a first level lower than the reference level according to the polarity of the data voltage to the lower common electrode. And a common voltage generator circuit for supplying the electrophoretic display device. The method of claim 1, And the upper common electrode and the lower common electrode are electrically separated from each other. The method of claim 1, The common voltage generation circuit, The polarity of the data voltage is determined by referring to the digital data, and the second common voltage is generated at the reference level or the first level according to the determination result. The method of claim 3, wherein The common voltage generation circuit, And the second common voltage is generated at the reference level when the digital data has a value corresponding to a positive polarity data voltage. The method of claim 3, wherein The common voltage generation circuit, And when the digital data has a value corresponding to a negative data voltage, generating the second common voltage at the first level. The method of claim 5, The common voltage generation circuit, And the second common voltage is generated at the first level when any one of the digital data to be displayed on the electrophoretic cells has a value corresponding to a negative data voltage. The method of claim 5, A parasitic transistor is formed between the data line and the pixel electrode by a potential difference between the data voltage and the second common voltage; And wherein the first level is determined within a voltage range capable of turning off the parasitic transistor during a period in which the negative data voltage is applied to the data line. The method of claim 7, wherein And the first level is determined within a range in which the gate-source voltage of the parasitic transistor is lower than the threshold voltage of the parasitic transistor.

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