KR20110064892A - Iq inverse quantization digital vector modulator - Google Patents

Abstract

PURPOSE: An IQ(Inverse Quantization) digital vector modulator is provided to replace an analog control method by a digital control method so that it can make the DA converter unnecessary. CONSTITUTION: An IQ signal generator(503) generates a signal, supplied via an input part(502), into two signals whose phases are 0 and 90 degrees. 180 degree digital phase shifters(504a,504b) switch the two signals to two signals whose phases are 0 and 180 degrees. Multiple bit digital attenuators(505a,505b) change amplitudes of signals passing the 180 degree digital phase shifters. A two directional power coupler(507) combines the two amplitude-modulated signals with each other. An output unit(508) outputs the combined signal.

Description

IQ INVERSE QUANTIZATION DIGITAL VECTOR MODULATOR}

The present invention relates to an IQ (INVERSE QUANTIZATION) digital vector modulator, and more specifically, to enable full digital control without a separate A / D converter, IQ digital is composed of a passive circuit that minimizes insertion loss by using an nMOS switch. A vector modulator is provided, which improves uniformity of vector distribution, and minimizes vector error caused by amplitude modulation in a specific phase.

For high frequency systems that perform phased array systems or carrier modulation, variable phase shifters and variable attenuators (or variable amplifiers) or vector modulators that allow control of the phase and amplitude of the signal are internal. To have.

In the case of a phased array system, an array antenna is configured to form a beam. At this time, hundreds or thousands of vector modulators are used. In order to reliably and efficiently control such a large amount of circuits, it is advantageous to be digitally controlled.

To date, vector modulators have been implemented using transistors based on semiconductor technology, but research and development have proceeded with phase and amplitude control relying mainly on analog methods.

Mahesh Kumar, Raymond J. Menna, Ho-Chung Huang, "Broad-Band Active Phase Shifter Using Dual-Gate MESFET," IEEE Transaction on Microwave Theory and Techniques, vol. 29, no. 10, pp. 1098 ?? 1102, Oct. 1981]. In this report, as indicated in FIG. 1A, a signal is received via the input 102 and a differential signal is generated through a balanced signal generator 180 ^o Balun 103 where each signal and signal is a 3 dB directional coupler. Through 104), orthogonal signals of 0 ^o , 90 ^o , 180 ^o and 270 ^o are generated.

Each of these signals is then amplitude controlled via a variable gain amplifier 105 in the next stage, and the quadrature signals of amplitude modulated 0 ^o , 90 ^o , 180 ^o and 270 ^o are used in four-way power to synthesize IQ vectors. A 4-way power combiner 106 is passed through to the output 107 for the final signal.

1B shows an example generated vector, in which signals of four orthogonal components 109a, 109b, 109c and 109d are synthesized to produce a final vector signal 110. Since this method requires the use of four variable gain amplifiers, a complex phased array system is disadvantageous due to the complexity and power consumption of the D / A converter, and huge passive elements are frequently used to generate and synthesize four quadrature signals.

Seward T. Salvage, Edward E. Messer, Jr., "MONOLITHIC VECTOR MODULATOR / COMPLEX WEIGHTING USING ALL-PASS NETWORK," US Patent, no. 4,806,888. Feb. 1989]. In this report, as indicated in FIG. 2A, an all-pass network 203 is used as a balanced IQ signal generator by receiving a signal from the input unit 202.

The generated signal is generated by four orthogonal signals through two differential amplifiers 204a and 204b, and four orthogonal signals 206a, 206b, 206c and 206d, which are amplitude modulated while passing through the attenuator 205, respectively. The final signal appears at the output 208 via the four-way power combiner 207.

2B shows an example generated vector, in which signals of four orthogonal components 209a, 209b, 209c and 209d are synthesized to produce a final vector signal 210. This method uses four dual-gate MESFETs, which also provide analog control.

Pei-Si Wu, Hong-Yeh Chang, Ming-Da Tsai, Tian-Wei Huang, Huei Wang "New Miniature 15-20 GHz Continuous-Phase / Amplitude Control MMICs Using 0.18-um CMOS Technology," IEEE Transaction on Microwave Theory and Techniques, vol. 52, no. 1, pp. 10 ?? 20, Jan. 2006]. This report presents the structure shown in FIGS. 3 and 4.

First, FIG. 3A receives a signal from the input unit 302 to make a differential signal through a balance signal generator (180 ^o Balun) 303 and modulates each signal through a primary variable gain amplifier (304).

After the modulated signal has passed the 3 dB directional coupler 305, again through the secondary variable gain amplifier 306, the final signals 307a and 307b are generated which are then passed through the two-way power combiner 308 to the output. Get signal at 309. By properly controlling the gain of the primary and secondary gain amplifiers, one can determine the phase and amplitude of the vector.

3B shows an example generated vector, and the signal magnitudes of four quadrature components are determined by gain adjustment of each primary and secondary variable gain amplifiers. If gain A ₁ of the two primary gain amplifiers 304 is greater than A ₃ , it appears as signals 310a and 310b through the secondary gain amplifier 306, and 312 through the two-way power combiner. The same signal is generated.

Conversely, if the gain A ₁ of the two primary gain amplifiers 304 is less than A ₃ , it appears as signals 312a and 312b through the secondary gain amplifier 306 and through the two-way power combiner 313. Signal is generated. However, four variable gain amplifiers must be analog controlled and a 3 dB directional coupler must be used.

FIG. 4A illustrates a 3 dB directional coupler connected to the Varactor 405 as a reflective phase shifter after generating a differential signal through a balance signal generator (180 ^o Balun) 403 after receiving a signal from the input unit 402. 404) produces variable phase signals of 90 ^o -180 ^o and 270 ^o -360 ^o .

After passing through the variable gain amplifier 406 to amplitude modulate it, the generated signals 407a and 407b apply a signal to the output 409 via the two-way power combiner 408. 4B shows an example generated vector, and the signals 410a and 410b passing through the 3 dB directional coupler 404 are located in quadrants 1 and 3, respectively, according to the phase change according to the Varactor adjustment. After passing through each of the variable gain amplifiers 406, they are combined to produce a final signal 411. In this method, the control of the varactor and the variable gain amplifier is analog.

The present invention uses an IQ signal generator, a two-way power combiner, a digitally controllable phase shifter and a signal attenuator to form an IQ vector modulator with full digital control. Then, we devised a method for reducing the vector error due to the uniformity of the vector distribution and the amplitude modulation in a specific phase. We also proposed a structure that can improve the signal gain while enabling digital control.

An object of the present invention is to provide an IQ digital vector modulator, which is capable of full digital control without a separate analog-to-digital converter and consists of a passive circuit using an nMOS switch.

In addition, another object of the present invention is to provide an IQ digital vector modulator by using a gain amplifier for each I- and Q-channel having an appropriate gain in order to reduce the insertion loss which is a disadvantage of the passive structure. .

The IQ digital vector modulator of the present invention for achieving the technical problem, IQ signal generator 503 for generating a signal received through the input unit 502 into two signals of 0, 90 ^o ; 180 ^o digital phase shifters 504a and 504b for switching the two signals, two phases of 0 ^o and 180 ^o respectively; Multi-bit digital attenuators 505a and 505b for varying the amplitude of the signals passing through the 180 ^o digital phase shifters 504a and 504b; A two-way power combiner 507 for combining the two converted signals 506a and 506b; An output unit 508 for outputting a combined signal; It includes.

According to the present invention as described above, since it is possible to replace the vector modulator having an analog control scheme to a fully digital control scheme, there is no need to use a D / A converter. Therefore, there is an effect that it is possible to efficiently construct a large part of a phased array system or the like which is more complicated by a D / A converter or the like.

Specific features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings. Prior to this, terms and words used in the present specification and claims are to be interpreted in accordance with the technical idea of the present invention based on the principle that the inventor can properly define the concept of the term in order to explain his invention in the best way. It should be interpreted in terms of meaning and concept. It is to be noted that the detailed description of known functions and constructions related to the present invention is omitted when it is determined that the gist of the present invention may be unnecessarily blurred.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

FIG. 5 is a block diagram illustrating an IQ digital vector modulator according to the present invention, and FIG. 6 is a circuit diagram of 180 ^o digital phase shifters 504a and 504b, which is one of the basic structural units of FIG. 7A and 7B illustrate a structure of a 1-bit digital attenuator having low pass phase variation, which is one of the basic structural units of FIG. 5, and FIG. 7C illustrates a structure of an n-bit digital attenuator composed of FIGS. 7A and 7B. Indicates.

The structure of FIG. 5 itself is a known configuration method as long as it is implemented in an analog manner, but a separate method is required in order to enable full digital control, which must digitally control a phase shifter and an attenuator to configure an IQ vector modulator. To reveal.

As shown in FIG. 5, the signal applied through the input unit 502 generates two signals, 0 and 90 ^o , through the IQ signal generator 503. These two signals pass through 180 ^o digital phase shifters 504a and 504b that switch between two phases of 0 ^o and 180 ^o , respectively, and through multi-bit digital attenuators 505 a and 505 b for amplitude variations. Here, the multi-bit digital attenuator used is configured to have low pass phase variation.

The two signals 506a and 506b thus processed are finally shown through the output unit 508 via the two-way power combiner 507.

FIG. 6 shows a circuit diagram of the 180 ^° digital phase shifter of FIG. 5. After passing through a high pass filter 605 or a low pass filter 606 through a switch 603a or 604a that receives a signal from the input unit 602 and operates complementarily, The signal is output to the final output unit 611 via the switch 603b or 604b that is complementary to operate.

At this time, the switches 603a, 603b, 604a, and 604b use nMOS transistors, respectively, and apply a control voltage to the respective gate terminals through the high series resistors 607, 608, 609, and 610, and the switches 603a and 604a. In addition, the switches 603b and 604b operate in the same manner as the single-pole-double-throw (SPDT) switches, respectively, and the control voltages of the switches can be individually controlled.

FIG. 7 is a detailed circuit diagram and an overall configuration diagram of the multi-bit digital attenuator of FIG. 5.

FIG. 7A illustrates a Pi-type digital attenuator structure in which a series switch 703 is connected between an input 702 and an output 708, and is also parallel to the input 702 and output 708, respectively. Switch 704 and a resistor 705 connected in series thereto.

In addition, the parallel capacitance 707 was used as the low pass filter to have a low pass phase variation, and the series switch 703 was configured to allow a desired signal attenuation by connecting the series resistor 706 at both ends, and the series switch 703 is a parallel switch. Complementary with 704, the series switch 703 is turned to the reference state when turned on, and turned to the attenuated state when turned off. 1-bit digital control is possible.

FIG. 7B has a T-type digital attenuator structure, in which a series switch 711 is connected between an input unit 710 and an output unit 717, a resistor 714 for matching, and a resistor ( 714 is composed of a parallel switch 712 and a resistor 713 connected in series thereto.

A low pass filter has a parallel capacitance 716 as a low pass filter, and a series resistor 715 is connected across the input 710 and the output 717 to enable desired signal attenuation. . At this time, the series switch 711 is complementary to the parallel switch 712, when the series switch 711 is turned on (on) it is switched to the reference state, turn-off (turn-off) Once attenuated, it can be switched to 1-bit digital control.

FIG. 7C is an N-bit digital attenuator using the structure described in FIGS. 7A and 7B as a 1-bit digital attenuator, and inserts an inductance component for matching between each 1-bit digital attenuator. do.

Hereinafter, the operation principle of the IQ digital vector modulator according to the present invention will be described with reference to FIG. 8A.

8A illustrates an example of generating a specific vector according to a phase change of a 180 ^° digital phase shifter and a amplitude change of a digital attenuator. First, FIG. 8A shows two SPDT switches of the 180 ^° digital phase shifter of FIG. 5. And a detailed circuit unit of the high band / low band filter.

According to the control voltage of the SPDT switch, respectively, the high-band and low-band filters are switched. At this time, the difference between the two phases is 180 ^o , and a signal is input to the input unit 802 to be 0 ^o by the IQ signal generator 803. , 90 ^o signal is generated.

Passing 180 ^o digital phase shifters respectively, the following four kinds of phase component combinations ((0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 270) ^o )) may be generated, respectively, and this signal passes through digital attenuators 804a and 804b to appear at 805a and 805b.

These two signals 805a and 805b are combined by a two-way in-phase power combiner 806, resulting in a final signal. FIG. 8B shows that when the SPDT switch of the 180 ^° digital phase shifter shown in FIG. 8A is in the above state, each I- and Q-channel has a phase component of 0 ^o and 90 ^o .

If the attenuation of the digital attenuator is the same, signals 808a and 808b are generated at 805a and 805b, and finally 809 signals having a phase of 45 ^o through the vector sum. Depending on the state of the SPDT switch, the above four types of phase combinations ((0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 270 ^o )) may occur. And all 360 ^o phases on a vector diagram.

On the other hand, when each of the I- and Q- channel while having a phase component of 0 ^o and 90 ^o becomes greater than the attenuation of the digital attenuator (804a) 804b, 805a and 805b has been to create a signal 810a and 810b and finally This results in a signal like 811 with a 60 ^o phase through the vector sum.

On the other hand, when 9 is the phase of a vector 0 ^o, of 90 ^o, 180 ^o and 270 ^o, by showing that the phase error is increased in accordance with the attenuation in the amplitude, for example, the phase is 0 ^o signal of the vector To generate, only the vector signal 902 appears on the output, but the 0 ^o phase signal by the vector sum of the 0 ^o signal 902 and the 90 ^o signal 903 with maximum attenuation, depending on the manner of operation of the IQ digital vector modulator according to the invention. Will generate 904.

Therefore, a phase error 907 occurs according to the maximum attenuation magnitude of the digital attenuator. If the phase component is 0 ^o and the amplitude is reduced to 905, the vector sum is represented by 906, where the vector error 908 is further increased.

Two methods can be considered to reduce the vector error as described above. First, increase the maximum attenuation value of the digital attenuator. However, this adds to the design burden of the digital attenuator and increases the number of bits for additional attenuation while maintaining the resolution, which also increases the area of the semiconductor circuit and is disadvantageous in terms of insertion loss.

The second method is to switch the 180 ^o digital phase shifter in a different way when the phase components are 0 ^o , 90 ^o , 180 ^o and 270 ^o . In other words, in the case of these four components, it is advantageous to completely block the I- or Q-channel signal transmission. Therefore, in addition to the two phase states of the 180 ^o digital phase shifter, an additional high isolation characteristic may be added. .

As shown in FIG. 10, if one 180 ^o digital phase shifter 1003b controls the switch to have a high isolation characteristic, and the next stage of the digital attenuator 1004b has a maximum attenuation value, The magnitude of the signal will be smaller because the isolation characteristic of the 180 ^° digital phase shifter is added in addition to the maximum attenuation of the digital attenuator. Thus, in this manner, it is possible to reduce phase errors of signals having phase components 0 ^o , 90 ^o , 180 ^o and 270 ^o .

In order to achieve the above object, it is possible to separately adjust the switch control voltage of the 180 ^o digital phase shifter without using an additional circuit. 11A illustrates a case where all of the switch control voltages of the 180 ^° digital phase shifter are applied with a turn-off voltage (0 V).

This turns off all switches to achieve high isolation. However, when the high frequency signal is transmitted, parasitic components of the nMOS switch appear large, which causes a problem of deteriorating input / output matching characteristics and isolation characteristics.

In order to maintain the input / output matching characteristics to some extent, as shown in FIG. 11B, the switch 1110a is operated like a switch operation of a 180 ^o digital phase shifter in a phase other than when the phase component is 0 ^o , 90 ^o , 180 ^o , 270 ^o . And 1111a are complementary to each other. At the same time, in order to obtain high isolation characteristics, 1110a and 1110b are also complementary to each other, and 1110b and 1111b are complementary to each other. Here, the I / O matching characteristics and isolation characteristics according to the control voltage for operating the switch can be seen through the simulation results.

12A and 12B show the characteristics of the input match (S (1,1)) and the output match S (2,2) according to the control voltage Vctr. According to the isolation characteristic (S (2,1)).

The case where the control voltage is 0 V means the case of FIG. 11A described above, in which the signals of 0 V are input to all the switches. At this time, it can be confirmed through simulation results that the input / output matching characteristics deteriorate very much. Even if all switches are turned off (0 V), it is difficult to achieve full isolation due to parasitics in high frequency operation.

When the control voltage Vctr is 1.8 V, it can be confirmed that the input / output matching characteristics are further improved as expected in the case shown in FIG. 11B. However, it is still insufficient to obtain sufficient matching characteristics. Since the switch is formed of an nMOS transistor, in order to obtain high matching characteristics, a 50 Ω match should be made. Therefore, it is understood that the on-resistance of the nMOS should be applied to a voltage close to 50 Ω.

Therefore, as shown in FIG. 11C, a switch 1118a that is connected in parallel between the input unit 1116 and the output unit 1123 is constituted, and a switch connected in series between the input unit 1116 and the output unit 1123 ( 1118b, connected in series between the input unit 1116 and the switch 1117b, a high pass filter 1119 for filtering an applied signal, and between the switch 1117a and the output unit 1123. A low pass filter 1120 for filtering an applied signal connected in parallel with each other is configured.

In addition, a series switch 1117a and a resistor 1121 which are connected in series between the input unit 1116 and the high pass filter 1119 to perform the function of the nMOS transistor so that the applied signal is matched to 50Ω. And a series switch 1118b connected in parallel between the switch 1117b, the low pass filter 1120, and the output unit 1123 to perform an nMOS transistor function so that the applied signal matches 50Ω. ) And the resistor 1122 can be configured to have excellent matching characteristics.

12D shows the on-resistance of an nMOS transistor according to a control voltage. In other words, if a control voltage of 1.8 V is applied, the value of the on-resistance becomes very small, making it unsuitable for 50 Ω matching. Therefore, the appropriate control voltage must be selected. It can be seen that it has 50 Ω at a control voltage slightly higher than the threshold voltage. When the switch operation is performed with the control voltage (Vctr = 0.6 V) thus determined, it can be seen that the matching characteristics are very good in FIGS. 12A and 12B. Looking at the isolation characteristics of FIG. 12C, a high isolation characteristic of 20 dB or less is obtained. Can be confirmed.

Therefore, when the 180 ^o digital phase shifter adopts a separate switching method, a method of setting the switch control voltage to an appropriate value is required in order to have high input / output matching and isolation characteristics.

13A is a structure in which the overall gain is improved by inserting unidirectional amplifiers 1305a and 1305b having appropriate gains into the I- and Q-channels of the designed IQ digital vector modulator, respectively. FIG. 13B illustrates a structure in which bidirectional amplifiers 1310a and 1310b are inserted into the I- and Q-channels, respectively, to improve the overall gain while maintaining the bidirectional signal transmission characteristic of the designed IQ digital vector modulator.

As described above and described with reference to a preferred embodiment for illustrating the technical idea of the present invention, the present invention is not limited to the configuration and operation as shown and described as described above, it is a deviation from the scope of the technical idea It will be understood by those skilled in the art that many modifications and variations can be made to the invention without departing from the scope of the invention. And all such modifications and changes as fall within the scope of the present invention are therefore to be regarded as being within the scope of the present invention.

1A shows a conventional vector modulator, a vector modulator having a balanced signal generator, two 3 dB directional couplers, four variable gain amplifiers and a four-way power combiner.

FIG. 1B is a vector diagram illustrating the vector signal generation of FIG. 1A. FIG.

FIG. 2A shows a conventional vector modulator, showing a vector modulator having an all-pass network, two differential amplifiers, four variable attenuators and a four-way power combiner as a balanced IQ signal generator. FIG.

FIG. 2B is a vector diagram illustrating the vector signal generation of FIG. 2A. FIG.

3A shows a conventional vector modulator, a vector modulator having a balanced signal generator, a 3 dB directional coupler, four variable gain amplifiers, and a two-way power combiner.

FIG. 3B is a vector diagram illustrating the vector signal generation of FIG. 3A. FIG.

4A shows a conventional vector modulator, showing a balanced signal generator, a 3 dB directional coupler with Varactor connected as a reflective phase shifter, two variable gain amplifiers, and a vector modulator with a two-way power combiner.

FIG. 4B is a vector diagram illustrating the vector signal generation of FIG. 4A. FIG.

FIG. 5A shows an IQ digital vector modulator comprising an IQ signal generator at an input, a 180 ^o digital phase shifter operating using a switching transistor, a multi-bit digital attenuator and a two-way power combiner at the output. Diagram shown.

6 is a schematic diagram of a detailed circuit of the 180 ^o digital phase shifter of FIG. 5;

7A and 7B are schematic diagrams of a 1-bit digital attenuator circuit forming the digital attenuator of FIG.

FIG. 7C is a schematic diagram of a 1-bit digital attenuator connected in series to configure the multi-bit digital attenuator of FIG. 5. FIG.

FIG. 8A is a block diagram specifically showing the 180 ^o digital phase shifter of FIG. 5 to illustrate the operation of the IQ digital vector modulator of the present invention. FIG.

FIG. 8B is a vector diagram illustrating the vector signal generation of FIG. 8A. FIG.

9 is a vector diagram for explaining the increase of the phase error according to the attenuation of the amplitude when generating a signal with phase components 0 ^o , 90 ^o , 180 ^o , 270 ^o .

10 is a configuration diagram for explaining a method for solving an increase in phase error due to attenuation of an amplitude when generating a signal having a phase component of 0 ^o , 90 ^o , 180 ^o , 270 ^o .

11A, 11B and 11C are schematic diagrams for explaining a method for increasing the isolation characteristics of a 180 ^° digital phase shifter.

12A and 12B are graphs showing simulation results of input and output matching characteristics according to control voltages.

12C is a graph showing the results of simulation of isolation characteristics with control voltage.

12D is a graph showing results of simulation of on-resistance values of nMOS switches according to control voltages.

FIG. 13A illustrates an IQ digital vector modulator structure inserting a unidirectional amplifier into each of the I- and Q-channels of FIG. 5 described above to increase overall gain. FIG.

FIG. 13B illustrates an IQ digital vector modulator structure inserting a bidirectional amplifier into each of the I- and Q-channels of FIG. 5 described above to increase overall gain. FIG.

** Description of symbols for the main parts of the drawing **

102, 202, 302, 402, 502, 602, 702, 710, 719, 802, 1002, 1102, 1109, 1116, 1302: Input section

103, 303, 403: balanced signal generator

104, 305, 404: 3 dB Directional Coupler

105, 304, 306, 406: Variable Gain Amplifier

106: 4-way power combiner

107, 208, 309, 409, 508, 611, 708, 717, 807, 1007, 1107, 1114, 1123, 1309: output

203: full-band network

204a, 204b: differential amplifier

205: attenuator

207: 4-way power combiner

308, 408, 507, 806, 1006, 1308: 2-way power combiner

405: varactor

503, 803, 1003, 1303: IQ signal generator

504a, 504b, 803a, 803b, 1003a, 1003b, 1304a, 1304b: 180 ^o digital phase shifter

505a, 505b, 804a, 804b, 1004a, 1004b, 1036a, 1036b: multi-bit digital attenuator

603a 603b, 604a, 604b, 703, 704, 711, 712, 1103a, 1103b, 1104a, 1104b, 1110a, 1110b, 1111a, 1111b, 1117a, 1117b, 1118a, 1118b: switch

607, 608, 609, 610, 705, 706, 713, 714, 715, 1121, 1122: resistance

605, 1105, 1112, 1119: high pass filter

606, 1106, 1113, 1120: low pass filter

707, 716: capacitance

1305a, 1305b: unidirectional amplifier

1310a, 1310b: unidirectional amplifier

Claims (9)

In the IQ digital vector converter, An IQ signal generator 503 for generating a signal received through the input unit 502 into two signals of 0 and 90 ^o ; 180 ^o digital phase shifters (504a, 504b) for switching the two signals, two phases of 0 ^o and 180 ^o respectively; A multi-bit digital attenuator (505a, 505b) for varying the amplitude of the signals passing through the 180 ^o digital phase shifters (504a, 504b); A two-way power combiner 507 for combining the two converted signals 506a and 506b; And An output unit 508 for outputting the combined signal; IQ digital vector converter comprising a. The method of claim 1, The 180 ^o digital phase shifters 504a, 504b, A switch 603a or 604a which receives a signal from the input unit 502 and operates complementarily; A high pass filter 605 or a low pass filter 606 for filtering the signal received from the switch 603a or 604a; A switch 603b or 604b configured to operate complementarily by receiving a signal from the high pass filter 605 or the low pass filter 606; And An output unit 611 for outputting a signal received from the switch 603b or 604b to the IQ signal generator 503; IQ digital vector converter, characterized in that consisting of. The method of claim 1, The multi-bit digital attenuators 505a, 505b, An input unit 702 which receives a signal from the 180 ^o digital phase shifters 504a and 504b; A series switch 703 provided between the input unit 702 and the output unit 708; Each parallel switch 704 provided between the input unit 702 and the output unit 708; A resistor 705 connected in series with each of the parallel switches 704; A series resistor 706 connected across the parallel switch 704 to attenuate a desired signal; And A parallel capacitance 707 connected between the series resistors 706 and performing a low pass filter function to have a low pass phase variation; Including, The series switch 703 and the parallel switch 704 operate complementarily, and the series switch 703 is in a reference state when turned on, and attenuated when turned off. IQ digital vector converter characterized by providing 1-bit digital control. The method of claim 1, The multi-bit digital attenuators 505a, 505b, An input unit 710 which receives a signal from the 180 ^o digital phase shifters 504a and 504b; A series switch 711 provided between the input unit 710 and the output unit 717; A resistor 714 connected to the input unit 710 and the output unit 717 for matching between the input unit 710 and the output unit 717; A parallel switch 712 provided between the resistors 714; A resistor 713 connected in series with the parallel switch 712; The series resistor 715 connected to the input unit 710 and the output unit 717; And A parallel capacitance 716 connected between the series resistors 715 to perform a low pass filter function to have a low pass phase variation; Including, The series switch 711 and the parallel switch 712 operate complementarily, and when the series switch 711 is turned on, it is in a reference state, and when it is turned off, the attenuated state is turned off. IQ digital vector converter characterized by providing 1-bit digital control. The method of claim 1, The 180 ^o digital phase shifters 504a, 504b, An input unit 802 receiving a signal from the input unit 502; An IQ signal generator (803) for converting the phase difference of the signal received from the input unit (802) to 180 ^o ; Phase components of the 0 ^o and 90 ^o signals generated by the IQ signal generator 803 are respectively (0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 270 ^{o) o} 180 phase shifter (803a, 803b for generating the in-phase component); Digital attenuators 804a and 804b for attenuating the phase components of the (0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 270 ^o ) through low band filtering ; And A two-way in-phase power combiner (806) for coupling the signals (805a, 805b) received from the digital attenuators (804a, 804b); Including, If the attenuation of the digital attenuator 804a and the digital attenuator 804b are the same, the attenuated signals 805a and 805b are generated as 808a and 808b, and these signals 808a and 808b are the two-way in-phase power combiner. A vector 804 via 806 generates a signal 809 having a phase of 45 ^o , and when the attenuation of the digital attenuator 804a is greater than the digital attenuator 804b, the attenuated signals 805a and 805b. Are generated as 810a and 810b, and these signals 810a and 810b generate a signal 811 having a phase of 60 ^o through vector addition via the two-way in-phase power combiner 806. IQ Digital Vector Converter. The method of claim 1, The 180 ^o digital phase shifters 504a, 504b, An input unit 1002 receiving a signal from the input unit 502; An IQ signal generator (1003) for converting the phase difference of the signal received from the input unit (1002) to 180 ^o ; The phase components of the 0 ^o and 90 ^o signals generated by the IQ signal generator 1003 are respectively (0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 180 ^o phase shifters 1003a and 1003b, which produce a phase component of 270 ^o ); Digital attenuators 1004a and 1004b for attenuating the phase components of the (0 ^o , 90 ^o ), (0 ^o , 270 ^o ), (180 ^o , 90 ^o ) and (180 ^o , 270 ^o ) through low band filtering ; And A two-way in-phase power combiner (1006) for combining the signals (1005a, 1005b) received from the digital attenuators (1004a, 1004b); Including, The 180 ^o phase shifter 1003b controls the switch to have a high isolation characteristic and the digital attenuator 1004b has a maximum attenuation value, thereby minimizing the signal magnitude of the 1005b so that the phase component is 0 ^o , IQ digital vector converter characterized by minimizing phase error of signals of 90 ^o , 180 ^o and 270 ^o . The method of claim 1, The 180 ^o digital phase shifters 504a, 504b, An input unit 1116 receiving a signal from the input unit 502; A switch 1118a connected in parallel between the input unit 1116 and the output unit 1123; A switch 1118b connected in series between the input unit 1116 and the output unit 1123; A high pass filter 1119 for filtering an applied signal connected in series between the input unit 1116 and the switch 1117b; A low pass filter 1120 for filtering an applied signal connected in parallel between the switch 1117a and the output unit 1123; A series switch 1117a and a resistor 1121 connected in series between the input unit 1116 and a high pass filter 1119 to perform an nMOS transistor function so that an applied signal is matched to 50Ω; A series switch 1118b connected in parallel between the switch 1117b, the low pass filter 1120 and the output unit 1123 to perform an nMOS transistor function so that an applied signal matches 50 Ω; Resistance 1122; And An output unit 1123 for outputting a signal received from the switch 1117b or the serial switch 1118b to the IQ signal generator 503; IQ digital vector converter comprising a. The method of claim 1, Unidirectional amplifiers 1305a and 1305b between the 180 ^° digital phase shifters 504a and 504b and the multi-bit digital attenuators 505a and 505b to increase the overall gain; IQ digital vector converter further comprises. The method of claim 1, Bidirectional amplifiers 1310a and 1310b between the 180 ^° digital phase shifters 504a and 504b and the multi-bit digital attenuators 505a and 505b to increase the overall gain; IQ digital vector converter further comprises.

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