CN117856803A - Radio frequency chip for improving flatness of transmission channel - Google Patents

Abstract

A Radio Frequency (RF) chip comprising: a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal; an amplifying stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to the first control signal; and a compensation capacitor bank provided between the mixer and the amplification stage. The compensation capacitor bank is configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

Description

RF chip with improved transmit channel flatness

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of priority to Korean Patent Application No. 10-2022-0128659 filed on October 7, 2022 and Korean Patent Application No. 10-2022-0180454 filed on December 21, 2022, the disclosures of which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates to radio frequency (RF) chips.

Background technique

The transmitter supports the function of adjusting the gain of the driver amplifier for the dynamic range. For example, the driver amplifier may include a plurality of unit amplifiers, and the gain of the driver amplifier may be adjusted based on the operation of slicing the plurality of unit amplifiers. In this case, the number of sliced unit amplifiers may vary depending on the gain adjustment. Therefore, the input impedance of the driver amplifier may vary. The change in the input impedance of the driver amplifier may cause degradation of the channel flatness.

Summary of the invention

Example embodiments provide an RF chip with improved channel flatness.

According to some example embodiments, an RF chip includes: a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal; an amplifier stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to a first control signal; and a compensation capacitor group provided between the mixer and the amplifier stage. The compensation capacitor group is configured to adjust the capacitance of the compensation capacitor group based on a second control signal, the second control signal being complementary to the first control signal.

According to some example embodiments, an operating method includes: outputting an RF signal by mixing a baseband signal with a local oscillation signal; amplifying the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and adjusting the capacitance of a compensation capacitor group provided at input terminals of the plurality of unit amplifiers based on a second control signal, the second control signal being complementary to the first control signal.

According to some example embodiments, an electronic device includes: a processor; an RF chip configured to receive a baseband signal from the processor and output an RF signal from the baseband signal; a front end module (FEM) configured to amplify the RF signal; and an antenna configured to transmit the RF signal. The RF chip may include: a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal; an amplifier stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to a first control signal; and a compensation capacitor group provided between the mixer and the amplifier stage. The compensation capacitor group is configured to adjust the capacitance of the compensation capacitor group based on a second control signal, the second control signal being complementary to the first control signal.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

FIG. 1 is a diagram illustrating an RF chip according to some example embodiments.

FIG. 2 is a diagram illustrating an RF chip according to some example embodiments.

FIG. 3 is a diagram illustrating a compensation capacitor bank according to some example embodiments.

FIG. 4 is a diagram illustrating a sub-capacitor group of FIG. 3 .

FIG. 5 is a diagram illustrating an RF chip capable of selecting a sub-capacitor group according to some example embodiments.

FIG. 6 is a diagram provided to describe an operation of the sub capacitor groups of FIG. 5 .

FIG. 7 is a flowchart illustrating an operating method of an RF chip according to some example embodiments.

8A and 8B are graphs showing amplifier input capacitance based on whether a compensation capacitor bank is present or absent.

9A and 9B are graphs showing channel flatness of an RF signal depending on whether a compensation capacitor bank is present or absent.

FIG. 10 is a diagram illustrating an electronic device according to some example embodiments.

Detailed ways

Hereinafter, example embodiments will be described with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating an RF chip according to some example embodiments.

1, a radio frequency (RF) chip 100 according to some example embodiments may be defined as a chip or an integrated circuit (IC) including various components for converting a baseband signal BB or an intermediate frequency (IF) signal into a radio frequency signal RF, amplifying the radio frequency signal RF, and transmitting the amplified signal. The RF chip 100 may be included as part of an RF chain or a transmission chain (TX chain). The RF chip 100 may include a mixer 110, an amplifier stage 120, and a compensation capacitor bank 130.

The mixer 110 may receive the baseband signal BB and may mix the baseband signal BB with a local oscillator (LO) signal to output a radio frequency signal RF. The local oscillation signal may have a frequency for up-converting the frequency of the baseband signal BB to an RF band.

The amplifier stage 120 may adjust the gain of the radio frequency signal RF output from the mixer 110. The amplifier stage 120 may include a plurality of unit amplifiers 121 for a dynamic range DR of the radio frequency signal RF. In some example embodiments, the plurality of unit amplifiers 121 may be connected in parallel to each other and may operate in response to a first control signal EN. The first control signal EN may be an enable signal for slicing (e.g., turning on or off) each of the plurality of unit amplifiers 121. The first control signal EN may be a digital signal for controlling each of the plurality of unit amplifiers 121.

In some example embodiments, when the number of unit amplifiers 121 is n (where n is a positive integer), the first control signal EN may have an n-bit magnitude. Each of the plurality of unit amplifiers 121 may be turned on or off based on the logic state of each bit of the first control signal EN. The amplifier stage 120 may control the number of unit amplifiers 121 turned on based on the first control signal EN to adjust the gain of the radio frequency signal RF.

The amplification stage 120 may amplify the radio frequency signal RF through a plurality of unit amplifiers 121 operating in response to the first control signal EN, and may output an amplified RF signal A_RF.

In some example embodiments, when a plurality of unit amplifiers 121 are implemented based on transistors, in the unit amplifier 121 turned off by the first control signal EN, the gate bias of the transistor may be adjusted to the ground voltage VSS. As the gate bias is adjusted to the ground voltage VSS, the input capacitance of the turned-off unit amplifier 121 may be relatively reduced compared to the input capacitance of the turned-on unit amplifier 121. For example, the input capacitance Cin_Amp (or impedance) of the amplification stage 120 may vary depending on the number of the unit amplifiers 121 turned on or off based on the adjustment of the dynamic range DR.

For example, as the number of closed unit amplifiers 121 increases relatively, the input capacitance Cin_Amp of the amplifier stage 120 may decrease. When the input capacitance Cin_Amp changes, the tuning frequency of the radio frequency signal RF may be shifted up to a relatively high frequency. Such a shift in the tuning frequency may cause channel flatness to deteriorate.

In some example embodiments, the RF chip 100 may additionally include a compensation capacitor group 130 between the mixer 110 and the amplifier stage 120 to compensate for the change in the input capacitance Cin_Amp depending on the above-mentioned gain adjustment of the amplifier stage 120. The compensation capacitor group 130 may be provided between the mixer 110 and the amplifier stage 120. One end of the compensation capacitor group 130 may be connected to the output terminal of the mixer 110, and the other end thereof may be connected to the input terminal of the amplifier stage 120. In some example embodiments, the mixer 110 and the amplifier stage 120 may communicate with the compensation capacitor group 130 (e.g., be electrically connected through/via the compensation capacitor group 130).

The compensation capacitor group 130 may have a capacitance adjusted based on a second control signal ENB that is complementary to the first control signal EN. The term "complementary" may mean that the second control signal ENB is configured to control an operation opposite to the operation based on the first control signal EN. For example, the logic level of each bit included in the second control signal ENB may be opposite to the logic level of each bit included in the first control signal EN. The second control signal ENB operates only to complement the first control signal EN, so that when the number of unit amplifiers 121 is n, similar to the first control signal EN, the second control signal ENB may have an amplitude of n bits.

In some example embodiments, when a relatively large number of unit amplifiers 121 are turned off based on the first control signal EN, the input capacitance Cin_Amp of the amplification stage 120 may be relatively reduced. Therefore, the second control signal ENB complementary to the first control signal EN may control the compensation capacitor group 130 to increase the input capacitance Cin_comp of the compensation capacitor group 130. For example, as the number of the unit amplifiers 121 turned off among the plurality of unit amplifiers 121 increases, the capacitance of the compensation capacitor group 130 may have a larger value.

As an example, when a relatively large number of unit amplifiers 121 are turned on based on the first control signal EN, the input capacitance Cin_Amp of the amplification stage 120 may be relatively increased. Therefore, the second control signal ENB complementary to the first control signal EN may control the compensation capacitor bank 130 to reduce the input capacitance Cin_comp of the compensation capacitor bank 130.

According to some example embodiments, the capacitance of the compensation capacitor group 130 may compensate for the input impedance of the amplifier stage 120 that varies depending on the first control signal EN. Therefore, from the output terminal of the mixer 110, the input impedance or input capacitance Cin_comp of the compensation capacitor group 130 may remain constant regardless of the capacitance variation depending on the gain adjustment of the amplifier stage 120.

According to some example embodiments, when the input capacitance Cin_Amp of the amplifier stage 120 varies depending on the gain adjustment of the amplifier stage 120, the variation may be compensated by the compensation capacitor group 130 provided between the mixer 110 and the amplifier stage 120 to maintain the tuning frequency and prevent or reduce channel flatness degradation. For example, the compensation capacitor group 130 may be controlled by a second control signal ENB complementary to a first control signal EN of the amplifier stage 120 for gain adjustment to control the capacitance of the compensation capacitor group 130 in a direction that compensates for the variation of the input capacitance Cin_Amp of the amplifier stage 120.

Hereinafter, some example embodiments related to the above-mentioned RF chip will be described in detail.

FIG. 2 is a diagram illustrating an RF chip according to some example embodiments.

2 , an RF chip 200 according to some example embodiments may include mixers 111 and 112 , an amplification stage 120 , a compensation capacitor group 130 , and a matching network 140 .

The mixers 111 and 112 may receive the I_baseband signals BB_I-1 and BB_I-2 and the Q_baseband signals BB_Q-1 and BB_Q-2 and mix them with the local oscillation signal LO to output RF signals RF_1 and RF_2. Each of the I_baseband signals BB_I-1 and BB_I-2 may be a differential signal, and each of the Q_baseband signals BB_Q-1 and BB_Q-2 may also be a differential signal. The first I_baseband signal BB_I-1 and the second I_baseband signal BB_I-2 may have opposite phases, and the first Q_baseband signal BB_Q-1 and the second I_baseband signal BB_Q-2 may have opposite phases. The I_baseband signals BB_I-1 and BB_I-2 and the Q_baseband signals BB_Q-1 and BB_Q-2 converted into RF frequencies by the mixers 111 and 112 may be integrated by the matching network 140.

The matching network 140 may receive the output signals of the mixers 111 and 112, and may output RF signals RF_1 and RF_2. The RF signals RF_1 and RF_2 may be differential signals, including a first RF signal RF_1 and a second RF signal RF_2 having opposite phases. In some example embodiments, the matching network 140 may be implemented as a transformer-based network, a shunt inductor-based network, an L-network-based network, an LC tank-based network, etc. Alternatively, the matching network 140 may be omitted, as shown in FIG. 1 .

The amplification stage 120 may include a plurality of first unit amplifiers 122 and a plurality of second unit amplifiers 123 that process differential signals, respectively. The plurality of first unit amplifiers 122 may be configured to adjust the gain of the first RF signal RF_1, and the plurality of second unit amplifiers 123 may be configured to adjust the gain of the second RF signal RF_2. A first amplified RF signal A_RF_1 having a gain adjusted by the plurality of first unit amplifiers 122 may be output, and a second amplified RF signal A_RF_2 having a gain adjusted by the plurality of second unit amplifiers 123 may be output.

Each of the plurality of first unit amplifiers 122 and each of the plurality of second unit amplifiers 123 may be turned on or off based on the first control signal EN.

The compensation capacitor bank 130 may be provided between the matching network 140 and the amplifier stage 120. The compensation capacitor bank 130 may operate in response to a second control signal ENB that is complementary to the first control signal EN that controls the amplifier stage 120 (e.g., as shown in FIG. 1 ). The capacitance of the compensation capacitor bank 130 may be adjusted based on the second control signal ENB, thereby allowing the input capacitance Cin_Comp of the compensation capacitor bank 130 to be adjusted.

In some example embodiments, the radio frequency signal RF output from the amplifier stage 120 may be tuned to a specific tuning frequency. The tuning frequency may be determined based on the input capacitance Cin_Amp of the amplifier stage 120, the capacitance of the compensation capacitor bank 130, and the impedance of the matching network 140. For example, the tuning frequency may be determined based on the input impedance of the output terminals of the mixers 111 and 112 or the input terminals of the matching network 140. In this case, as described above, the input capacitance Cin_Amp of the amplifier stage 120 may vary depending on the gain adjustment, and therefore, the tuning frequency may also vary.

For example, when the RF chip 200 operates at a low gain, the number of the unit amplifiers 121 that are turned off among the plurality of first unit amplifiers 122 and the plurality of second unit amplifiers 123 may be relatively increased. This means a reduction in the input capacitance Cin_Amp of the amplifier stage 120. The compensation capacitor group 130 may operate in response to a second control signal ENB complementary to the first control signal EN for operating the amplifier stage 120 to compensate for the reduced input capacitance of the amplifier stage 120. Therefore, even when the input capacitance Cin_Amp of the amplifier stage 120 changes, the capacitance of the compensation capacitor group 130 may compensate for the change in the input capacitance Cin_Amp of the amplifier stage 120, so that the input impedance of the input terminal of the matching network 140 may be kept constant.

FIG. 3 is a diagram illustrating a compensation capacitor bank according to some example embodiments.

3 , the compensation capacitor group 130 may be connected to first differential ports P1-1 and P1-2 connected to the mixer 110 or the matching network 140, and to second differential ports P2-1 and P2-2 connected to the amplifier stage 120. The compensation capacitor group 130 may include one or more sub-capacitor groups 131_1, 131_2 to 131_k.

The one or more sub-capacitor groups 131_1, 131_2 to 131 — k may operate in response to the commonly applied second control signal ENB. The capacitance of each of the one or more sub-capacitor groups 131_1, 131_2 to 131 — k may be adjusted based on the second control signal ENB.

Even when the second control signal ENB is commonly applied, the capacitances of the sub-capacitor groups 131_1, 131_2 to 131_k may be different from each other. For example, based on the second control signal ENB, the capacitance of the first sub-capacitor group 131_1 may be adjusted by Ca, the capacitance of the second sub-capacitor group 131_2 may be adjusted by Cb, and the capacitance of the third sub-capacitor group 131_k may be adjusted by Cc, where Ca, Cb, and Cc may be different real value values.

In some example embodiments, each of the sub-capacitor groups 131_1, 131_2 to 131_k may be implemented to have a value that varies depending on a gain step of the amplifier stage 120, in which the capacitance is adjusted based on the first control signal EN. In addition, the sub-capacitor groups 131_1, 131_2 to 131_k may include k sub-capacitor groups (where k is a positive integer), and k may also be set to vary depending on the gain step of the amplifier stage 120.

FIG. 4 is a diagram illustrating a sub-capacitor group of FIG. 3 .

4 , each of the individual sub-capacitor groups (eg, the sub-capacitor group 131 — k as shown in FIG. 4 ) may include a plurality of capacitor adjustment circuits 132_1 , 132_2 to 132 — n .

The capacitor adjustment circuits 132_1, 132_2 to 132_n may include switches S1, S2 to Sn and unit capacitors C1, C2 to Cn connected to the switches S1, S2 to Sn, respectively. For ease of description, in FIG. 4, each capacitor adjustment circuit is shown as including a single unit capacitor. However, in some example embodiments, one or more unit capacitors may be connected to a single switch. The number of capacitor adjustment circuits 132_1, 132_2 to 132_n may be n, which is the same as the number of unit amplifiers 121.

The second control signal ENB may be applied to each capacitor adjustment circuit 132_1, 132_2 to 132_n to independently operate the capacitor adjustment circuit 132_1, 132_2 to 132_n. For example, when the second control signal ENB is an n-bit signal, the second control signal ENB may be applied to each capacitor adjustment circuit 132_1, 132_2 to 132_n in units of bits.

The same number of capacitor adjustment circuits 132_1, 132_2 to 132_n as the number of unit amplifiers 121 may be provided for each of the sub-capacitor groups 131_1, 131_2 to 131_k so that the plurality of capacitor adjustment circuits 132_1, 132_2 to 132_n operate independently. For example, when the number of unit amplifiers 121 is n, n capacitor adjustment circuits 132_1, 132_2 to 132_n may also be provided for each of the sub-capacitor groups 131_1, 131_2 to 131_k.

The switches S1, S2 to Sn respectively included in the capacitor adjustment circuits 132_1, 132_2 to 132_n may be turned on or off based on the second control signal ENB applied in units of bits. For example, when the first control signal EN applied to the amplifier stage 120 in units of bits is EN<n-1>, EN<n-2>, and EN<0>, the second control signal ENB applied to the plurality of capacitor adjustment circuits 132_1, 132_2, and 132_n in units of bits may be ENB<n-1>, ENB<n-2>, and ENB<0>. Each of ENB<n-1>, ENB<n-2>, and ENB<0> may have a different logic level from that of each of EN<n-1>, EN<n-2>, and EN<0>.

For example, when EN<n-1>, EN<n-2>, and EN<0> have logic levels 1, 1, and 1, respectively, ENB<n-1>, ENB<n-2>, and ENB<0> may have logic levels 0, 0, and 0, respectively. In this case, all of switches S1, S2, and Sn may be turned off. For example, when EN<n-1>, EN<n-2>, and EN<0> have logic levels 1, 1, and 0, respectively, ENB<n-1>, ENB<n-2>, and ENB<0> may have logic levels 0, 0, and 1, respectively. In this case, among the plurality of capacitor adjustment circuits 132_1, 132_2, and 132_n, only the capacitor adjustment circuit 132_n to which ENB<0> is applied may operate, and the other capacitor adjustment circuits may be turned off. In the above example embodiment, for clarity of explanation, n is 3; however, example embodiments are not limited thereto, and n may be another real number.

According to some example embodiments, when the capacitor adjustment circuits 132_1, 132_2 to 132_n do not operate because the switches S1, S2 to Sn are turned off, one or more unit capacitors C1, C2 to Cn connected to the switches S1, S2 to Sn may no longer affect the total capacitance of the sub-capacitor groups 131_1, 131_2 to 131_k.

When m unit amplifiers (where m is a positive integer less than or equal to n) among the n unit amplifiers 121 are turned on based on the first control signal EN, n-m capacitor adjustment circuits 132_1, 132_2 to 132_n may be turned on based on switches S1, S2 to Sn operated in response to the second control signal ENB. In some example embodiments, the number n of unit amplifiers 121 and capacitor adjustment circuits 132_1 to 132_n may be in an on state, wherein a ratio of the turned-on unit amplifiers 121 to the turned-on capacitor adjustment circuits 132_1 to 132_n varies with the first control signal EN and the second control signal ENB.

When one or more switches S1, S2 to Sn are turned on, the capacitance obtained by summing the equivalent capacitances of the one or more unit capacitors C1, C2 to Cn connected to the turned-on switches S1, S2 to Sn may be the total capacitance of the compensation capacitor group 130. Therefore, as the number of unit amplifiers 121 turned off based on the first control signal EN increases, the number of capacitor adjustment circuits 132_1, 132_2 to 132_n turned on based on the second control signal ENB may increase, and thus, the total capacitance of the compensation capacitor group 130 may also increase. As a result, even when the input capacitance Cin_Amp of the amplification stage 120 decreases as the number of turned-off unit amplifiers 121 increases, the decreased capacitance may be compensated by the compensation capacitor group 130.

FIG. 5 is a diagram illustrating an RF chip capable of selecting a sub-capacitor group according to some example embodiments.

5 , in the RF chip 100 , the compensation capacitor group 130 may be additionally applied with a selection signal (hereinafter referred to as a “third control signal Sel”) for independently operating one or more sub-capacitor groups 131_1 , 131_2 to 131 — k. The third control signal Sel may be applied to the compensation capacitor group 130 .

The third control signal Sel may be applied individually to the plurality of sub-capacitor groups 131_1, 131_2 to 131_k to select each of the plurality of sub-capacitor groups 131_1, 131_2 to 131_k. When the number of sub-capacitor groups 131_1, 131_2 to 131_k is k, k third control signals Sel may be applied. In addition, the adjusted capacitances of the sub-capacitor groups 131_1, 131_2 to 131_k may be different from each other.

Among the plurality of sub-capacitor groups 131_1, 131_2 to 131_k, one or more sub-capacitor groups 131_1, 131_2 to 131_k may each be turned on or off based on the third control signal Sel. The fact that each of the sub-capacitor groups 131_1, 131_2 to 131_k is turned off may mean that the capacitance of the turned-off sub-capacitor groups 131_1, 131_2 to 131_k does not affect the total capacitance of the compensation capacitor group 130, similar to the above-mentioned unit capacitors C1, C2 to Cn.

By turning on or off a plurality of sub-capacitor groups 131_1, 131_2 to 131_k based on the third control signal Sel, the RF chip 100 can compensate for capacitance more finely (e.g., precisely, specifically). For example, the capacitance of the first sub-capacitor group 131_1, 131_2 to 131_k to which the k-1 third control signal Sel_k-1 is applied can be implemented to be higher than the capacitance of the second sub-capacitor group 131_1, 131_2 to 131_k to which the k-2 third control signal Sel_k-2 is applied. In this case, when the input capacitance Cin_Amp of the amplifier stage 120 that depends on the change of the first control signal EN is high, the first sub-capacitor group 131_1, 131_2 to 131_k can be selected to compensate for capacitance more roughly (e.g., roughly). Alternatively, when the varying input capacitance Cin_Amp of the amplifier stage 120 is low, the second sub-capacitor groups 131_1 , 131_2 to 131 — k may be selected to more finely (eg, precisely, specifically) compensate for the capacitance.

Alternatively, two or more sub-capacitor groups 131_1 , 131_2 to 131 — k may be selected and combined based on the varying input capacitance Cin_Amp of the amplification stage 120 .

According to example embodiments, as the number k of the plurality of sub-capacitor groups 131_1 , 131_2 to 131 — k further increases, the capacitance may be more finely compensated. For example, the capacitance may be more finely tuned.

FIG. 6 is a diagram provided to describe an operation of the sub capacitor groups of FIG. 5 .

6, according to some example embodiments, the control circuits 133_1, 133_2 to 133_n that control the compensation capacitor group 130 based on the second control signal ENB and the third control signal Sel_k (described with respect to the kth control signal for ease of description) may be connected to the plurality of capacitor adjustment circuits 132_1, 132_2 to 132_n included in the sub-capacitor groups 131_1, 131_2 to 131_k. The control circuits 133_1, 133_2 to 133_n may be provided in plural to be connected to the switches S1, S2 to Sn, respectively.

The control circuits 133_1, 133_2 to 133_n may be connected to a plurality of switches S1, S2 to Sn included in the plurality of capacitor adjustment circuits 132_1, 132_2 to 132_n, respectively. The control circuits 133_1, 133_2 to 133_n may take the second control signal ENB and the third control signal Sel_k as input. In some example embodiments, for each unit of bit, the second control signal ENB may be applied to the control circuits 133_1, 133_2 to 133_n (e.g., as ENB<n-1> applied to the control circuit 133_1, etc.), and the third control signal Sel_k may be applied to the control circuits 133_1, 133_2 to 133_n in units of a single sub-capacitor group 131_1, 131_2, or 131_k. For example, the common third control signal Sel_k may be applied to the control circuits 133_1 , 133_2 to 133 — n connected to a single sub-capacitor group 131_1 , 131_2 , or 131 — k.

The control circuits 133_1, 133_2 to 133_n can turn on or off the switches S1, S2 to Sn based on the logic states of the second control signal ENB and the third control signal Sel_k, respectively. For example, when the third control signal Sel_k instructs the sub-capacitor groups 131_1, 131_2 to 131_k to be turned on, the control circuits 133_1, 133_2 to 133_n can turn on or off each of the switches S1, S2 to Sn based on the logic state of each bit of the second control signal ENB. For example, when the third control signal Sel_k instructs the sub-capacitor groups 131_1, 131_2 to 131_k to be turned off, the control circuits 133_1, 133_2 to 133_n can turn off all of the switches S1, S2 to Sn. In this case, a single sub-capacitor group 131_1 , 131_2 , or 131 — k to which the control circuits 133_1 , 133_2 , or 131 — k are connected may not affect the total capacitance of the compensation capacitor group 130 .

As a result, the control circuits 133_1, 133_2 to 133_n can operate one or more sub-capacitor groups 131_1, 131_2 to 131_k among the multiple sub-capacitor groups 131_1, 131_2 to 131_k based on the third control signal Sel_k, and the multiple capacitor adjustment circuits 132_1, 132_2 to 132_n respectively included in the operated one or more sub-capacitor groups 131_1, 131_2 to 131_k can be turned on or off based on the second control signal ENB.

According to some example embodiments, the compensation capacitor group 130 may be controlled by the control circuits 133_1, 133_2 to 133_n. For example, considering that the input capacitance Cin_Amp of the amplification stage 120 varies depending on the first control signal EN, some sub-capacitor groups 131_1, 131_2 to 131_k among the plurality of sub-capacitor groups 131_1, 131_2 to 131_k having different capacitances may operate, or any sub-capacitor group 131_1, 131_2 to 131_k may operate. As a result, capacitance may be compensated more accurately (e.g., over a smaller range) or roughly (e.g., approximately, over a wider range) based on the degree of input capacitance variation, and channel flatness may be improved.

FIG. 7 is a flowchart illustrating an operating method of an RF chip according to some example embodiments.

7 , in operation S1010 , the RF chip 100 (or, for example, the RF chip 200 ) may output a radio frequency signal RF by mixing a local oscillation signal with a baseband signal BB.

In operation S1020, the RF chip 100 or 200 may amplify the radio frequency signal RF through the plurality of unit amplifiers 121 operating in response to the first control signal EN. In this case, at least one of the plurality of unit amplifiers 121 may be turned on or off based on the first control signal EN, and thus the gain of the radio frequency signal RF may be adjusted.

In operation S1030, the RF chip 100 or 200 may adjust the capacitance of the compensation capacitor group 130 provided at the input terminals of the plurality of unit amplifiers 121 based on the second control signal ENB complementary to the first control signal EN. In this case, when the number of the unit amplifiers 121 is n, the first control signal EN and the second control signal ENB may have an n-bit amplitude.

Operation S1030 may be performed to complement operation S1020. For example, the gain of the radio frequency signal RF may be adjusted based on the application of the first control signal EN, and the input capacitance Cin_Amp of the amplifier stage 120 may be compensated, which varies depending on the adjustment of the gain of the radio frequency signal RF based on the application of the second control signal ENB.

In some example embodiments, the operating method may further include applying a third control signal Sel to individually operate one or more sub-capacitor groups 131 included in the compensation capacitor group 130. Applying the third control signal Sel may be performed together with operation S1030. Considering the logic state of the second control signal ENB and the logic state of the third control signal Sel, the control circuits 133_1, 133_2 to 133_n applied with the third control signal Sel may turn on or off the compensation capacitor group 130 and the capacitor adjustment circuits 132_1, 132_2 to 132_n included in the compensation capacitor group 130.

8A and 8B are graphs illustrating amplifier input capacitance based on whether a compensation capacitor group exists or does not exist. For ease of description, in FIGS. 8A and 8B , the first control signal is illustrated as a 4-bit signal, but example embodiments are not limited thereto.

It can be seen from Figure 8A that in the absence of the compensation capacitor group 130, as the number of logic "0" bits among the bits of the first control signal EN increases (for example, the number of unit amplifiers 121 turned off increases), the input capacitance on the Smith chart decreases.

At the same time, as can be seen from Figure 8B, in the presence of the compensation capacitor group 130, even when the state of the unit amplifier 121 changes depending on the first control signal EN, the input capacitance hardly changes and remains within a predetermined (or alternatively, desired, selected or determined) range, which means that the changing input capacitance Cin_Amp of the amplifier stage 120 is compensated by the compensation capacitor group 130.

9A and 9B are graphs showing channel flatness of an RF signal depending on whether a compensation capacitor group exists or not. In FIG9A and 9B , a slice refers to the number of unit amplifiers 121 that are turned on among a plurality of unit amplifiers 121 .

9A , in the absence of the compensation capacitor group 130, when all the unit amplifiers 121 are in the on state, the radio frequency signal RF may be transformed so that the upper sideband and the lower sideband are symmetrical with respect to the frequency of the local oscillation signal (the point where the offset frequency is zero). However, as the number of slices decreases, for example, the number of turned-off unit amplifiers 121 increases, the input capacitance Cin_Amp of the amplifier stage 120 may decrease, and therefore, the tuning frequency may gradually shift to a high frequency (which may be referred to as high-shift). Ultimately, this may result in poor channel flatness.

At the same time, as in the present disclosure, in the presence of the compensation capacitor bank 130, as can be seen from FIG. 9B, the tuning frequency is maintained because the varying input capacitance can be compensated even when the number of slices is reduced. When the tuning frequency is maintained, the symmetry (or substantial symmetry) between the upper sideband and the lower sideband can be maintained, and therefore, the channel flatness can also be maintained or improved.

The preservation of the channel refers to the reduction of the power Pout deviation in the channel, which means that the performance of the error vector magnitude (EVM) is improved. In addition, the asymmetry between the upper sideband and the lower sideband means that the power is asymmetric depending on the resource block (RB). When the compensation capacitor bank 130 does not exist, calibration should be performed additionally to solve the power asymmetry between RBs.

However, when the compensation capacitor group 130 according to example embodiments is provided, the asymmetry between RBs can be resolved. Therefore, there is no need to additionally perform frequency-based calibration.

Fig. 10 is a diagram illustrating an electronic device according to some example embodiments. Hereinafter, detailed descriptions of repeated technical features will be omitted.

10 , an electronic device 10 according to some example embodiments may include a processor 11 , an RF chip 100 , a front end module (FEM) 12 , and an antenna 13 .

The processor 11 may process a digital signal and then convert the digital signal into an analog signal. Alternatively, the processor 11 may convert the analog signal into a digital signal and then process the digital signal. The converted analog signal or the analog signal to be converted may be a baseband signal BB having a baseband. The processor 11 may send the baseband signal BB to the RF chip 100. The processor 11 may be, for example, a modem, an application processor (AP), or a modem & application processor (ModAP) in which a modem function is integrated into the AP.

The RF chip 100 may up-convert the baseband signal BB received from the processor 11 to output a radio frequency signal RF to the FEM 12. The RF chip 100 may be implemented according to some of the above-described example embodiments.

In some example embodiments, the RF chip 100 may include a mixer 110, an amplifier stage 120, and a compensation capacitor group 130. The mixer 110 may convert a baseband signal BB sent from the processor 11 to an RF band. The gain of the amplifier stage 120 may be adjusted based on a first control signal EN. Each of a plurality of unit amplifiers 121 included in the amplifier stage 120 may be turned on or off based on the first control signal EN, resulting in a change in the input capacitance Cin_Amp of the amplifier stage 120.

When the gain of the amplifier stage 120 is adjusted based on the first control signal EN, the capacitance of the compensation capacitor group 130 may be adjusted based on the second control signal ENB complementary to the first control signal EN and/or the third control signal Sel for selecting a plurality of capacitors included in the compensation capacitor group 130. In some example embodiments, the second control signal ENB and/or the third control signal Sel may be applied to the RF chip 100 by the processor 11.

Therefore, a change in the input capacitance Cin_Amp of the amplifier stage 120 can be compensated by the capacitance of the compensation capacitor group 130. Then, the input capacitance can be kept constant as seen from the output terminal of the mixer 110. As a result, the tuning frequency of the radio frequency signal RF can be maintained regardless of the operation of the amplifier stage 120, and therefore, degradation of the channel flatness can be prevented or reduced.

The FEM 12 may be configured to amplify the radio frequency signal RF output from the RF chip 100, or to guide the amplified radio frequency signal RF to one or more signal paths. To this end, the FEM 12 may include one or more power amplifiers Pa and one or more switches. The FEM 12 may be connected to the RF chip 100 via various connection interfaces (e.g., a mobile industry processor interface (MIPI) etc.), and may operate under the control of the RF chip 100.

The antenna 13 may transmit the radio frequency signal RF received from the FEM 12 to another wireless communication device.

Although the electronic device 10 according to some example embodiments has been described from the aspect of a transmission chain, the electronic device 10 may include a reception chain (Rx chain). In this case, the electronic device 10 may perform operations to process a received radio frequency signal RF.

As described above, according to example embodiments, an RF chip having improved channel flatness may be provided.

As described herein, any electronic device and/or portion thereof according to any example embodiment may include, may be included in, and/or may be implemented by: one or more instances of a processing circuit such as hardware including a logic circuit; a hardware/software combination such as a processor executing software; or any combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA) and a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), and the like. In some example embodiments, the processing circuit may include: a non-transitory computer-readable storage device (e.g., a memory) storing an instruction program, such as a DRAM device; and a processor (e.g., a CPU) configured to execute the instruction program to implement the functions and/or methods performed by some or all of the devices, systems, modules, units, controllers, circuits, architectures, and/or portions thereof according to any and/or any portion thereof in the example embodiments.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims (20)

1. A Radio Frequency (RF) chip comprising:

a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal;

an amplifying stage configured to amplify the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and

a compensation capacitor bank is provided between the mixer and the amplification stage, the compensation capacitor bank being configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

2. The RF chip of claim 1 wherein

Each of the plurality of unit amplifiers is configured to be turned off or on by the first control signal.

3. The RF chip of claim 1 wherein

The compensation capacitor bank includes one or more sub-capacitor banks, each sub-capacitor bank including a plurality of capacitor adjustment circuits.

4. The RF chip of claim 3 wherein

Each of the plurality of capacitor adjustment circuits includes:

a switch configured to be turned on or off based on the second control signal; and

one or more unit capacitors connected to the switch.

5. The RF chip of claim 3 wherein

The number of the plurality of capacitor adjustment circuits is the same as the number of the plurality of unit amplifiers, wherein the number of the plurality of unit amplifiers is n, and n is a positive integer.

6. The RF chip of claim 5 wherein

Based on m unit amplifiers being turned on, m is less than or equal to n, n-m capacitor adjustment circuits of the plurality of capacitor adjustment circuits are configured to be turned on based on the second control signal.

7. The RF chip of claim 2 wherein

The capacitance increases based on an increase in the number of turned-off unit amplifiers among the plurality of unit amplifiers.

8. The RF chip of claim 3, further comprising:

a control circuit configured to control the compensation capacitor bank based on the second control signal and a third control signal for independently operating the one or more sub-capacitor banks.

9. The RF chip of claim 8 wherein

The one or more sub-capacitor banks are each configured to be turned on or off based on the third control signal, and

the plurality of capacitor adjustment circuits are each configured to be turned on or off based on the second control signal.

10. The RF chip of claim 1 wherein

The compensation capacitor bank is configured to adjust the capacitance to compensate for an input impedance of the amplification stage, the input impedance varying based on the first control signal.

11. The RF chip of claim 1 wherein

Based on the number of the plurality of unit amplifiers being n, each of the first control signal and the second control signal has an amplitude of n bits.

12. The RF chip of claim 1, further comprising:

a matching network between the mixer and the compensation capacitor bank.

13. A method of operation, comprising:

outputting a Radio Frequency (RF) signal by mixing the baseband signal with a local oscillation signal;

amplifying the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and

the capacitance of the compensation capacitor bank provided at the input terminals of the plurality of unit amplifiers is adjusted based on a second control signal, which is complementary to the first control signal.

14. The method of operation of claim 13, further comprising:

a third control signal is applied to independently operate one or more sub-capacitor banks included in the compensation capacitor bank.

15. The method of operation of claim 13, wherein

Based on the number of the plurality of unit amplifiers being n, each of the first control signal and the second control signal has an amplitude of n bits.

16. An electronic device, comprising:

a processor;

a Radio Frequency (RF) chip configured to receive a baseband signal from the processor and output an RF signal from the baseband signal;

a Front End Module (FEM) configured to amplify the RF signal; and

an antenna configured to transmit the RF signal,

the RF chip may include a plurality of RF chips,

a mixer configured to mix a local oscillation signal with the baseband signal to output the RF signal;

an amplifying stage configured to amplify the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and

a compensation capacitor bank is provided between the mixer and the amplification stage, the compensation capacitor bank being configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

17. The electronic device of claim 16, wherein

The compensation capacitor bank includes one or more sub-capacitor banks, each sub-capacitor bank including a plurality of capacitor adjustment circuits, and

providing as many of the plurality of capacitor adjustment circuits as the plurality of unit amplifiers.

18. The electronic device of claim 17, wherein

Based on m unit amplifiers being turned on, m being less than or equal to n, n being the number of the plurality of unit amplifiers, n-m capacitor adjustment circuits of the plurality of capacitor adjustment circuits are configured to be turned on based on the second control signal.

19. The electronic device of claim 17, further comprising:

the RF chip further includes a control circuit configured to control the compensation capacitor bank based on the second control signal and a third control signal for independently operating the one or more sub-capacitor banks.

20. The electronic device of claim 16, wherein

The compensation capacitor bank is configured to adjust the capacitance to compensate for an input impedance of the amplification stage, the input impedance varying in dependence on the first control signal.