CN117856803A

CN117856803A - Radio frequency chip for improving flatness of transmission channel

Info

Publication number: CN117856803A
Application number: CN202311289976.0A
Authority: CN
Inventors: 李重根; 郑大喆; 裵廷烈; 李钟洙; 刘相珉
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-10-07
Filing date: 2023-10-07
Publication date: 2024-04-09

Abstract

A Radio Frequency (RF) chip comprising: a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal; an amplifying stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to the first control signal; and a compensation capacitor bank provided between the mixer and the amplification stage. The compensation capacitor bank is configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

Description

Radio frequency chip for improving flatness of transmission channel

Cross reference to related applications

The present application claims the benefit of priority from korean patent application No. 10-2022-0128659, filed on 10 months 07 of 2022, and korean patent application No. 10-2022-0180454, filed on 21 of 12 months of 2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to Radio Frequency (RF) chips.

Background

The transmitter supports the function of adjusting the gain of the drive amplifier for dynamic range. For example, the driving amplifier may include a plurality of unit amplifiers, and the gain of the driving amplifier may be adjusted based on a slicing (sliding) operation of the plurality of unit amplifiers. In this case, the number of unit amplifiers to be fragmented may vary depending on the gain adjustment. Thus, the input impedance of the driver amplifier may vary. Variations in the input impedance of the driver amplifier may lead to degradation of channel flatness.

Disclosure of Invention

Example embodiments provide an RF chip with improved channel flatness.

According to some example embodiments, an RF chip includes: a mixer (mixer) configured to mix the local oscillation signal with the baseband signal to output an RF signal; an amplifying stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to the first control signal; and a compensation capacitor bank provided between the mixer and the amplification stage. The compensation capacitor bank is configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

According to some example embodiments, a method of operation includes: outputting an RF signal by mixing the baseband signal with a local oscillation signal; amplifying the RF signal by a plurality of unit amplifiers operating in response to the first control signal; and adjusting the capacitance of the compensation capacitor bank provided at the input terminals of the plurality of unit amplifiers based on a second control signal, the second control signal being complementary to the first control signal.

According to some example embodiments, an electronic device includes: a processor; an RF chip configured to receive a baseband signal from the processor and output an RF signal from the baseband signal; a Front End Module (FEM) configured to amplify the RF signal; and an antenna configured to transmit the RF signal. The RF chip may include: a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal; an amplifying stage configured to amplify the RF signal through a plurality of unit amplifiers operating in response to the first control signal; and a compensation capacitor bank provided between the mixer and the amplification stage. The compensation capacitor bank is configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

Drawings

The foregoing and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

Fig. 1 is a diagram illustrating an RF chip according to some example embodiments.

Fig. 2 is a diagram illustrating an RF chip according to some example embodiments.

Fig. 3 is a diagram illustrating a compensation capacitor bank according to some example embodiments.

Fig. 4 is a diagram illustrating the sub-capacitor bank of fig. 3.

Fig. 5 is a diagram illustrating an RF chip capable of selecting a sub-capacitor bank according to some example embodiments.

Fig. 6 is a diagram provided to describe the operation of the sub-capacitor bank of fig. 5.

Fig. 7 is a flowchart illustrating a method of operation of an RF chip according to some example embodiments.

Fig. 8A and 8B are diagrams showing amplifier input capacitances based on whether a compensation capacitor bank is present or absent.

Fig. 9A and 9B are diagrams showing the channel flatness of the RF signal depending on whether the compensation capacitor bank exists or does not exist.

Fig. 10 is a diagram illustrating an electronic device according to some example embodiments.

Detailed Description

Hereinafter, example embodiments will be described with reference to the accompanying drawings.

Referring to fig. 1, a Radio Frequency (RF) chip 100 according to some example embodiments may be defined as a chip or an Integrated Circuit (IC) including various components for converting a baseband signal BB or an Intermediate Frequency (IF) signal into a radio frequency signal RF, amplifying the radio frequency signal RF, and transmitting the amplified signal. The RF chip 100 may be included as part of an RF chain or a transmit chain (TX chain). The RF chip 100 may include a mixer 110, an amplifying stage 120, and a compensation capacitor bank 130.

The mixer 110 may receive the baseband signal BB and may mix the baseband signal BB with a Local Oscillator (LO) signal to output a radio frequency signal RF. The local oscillation signal may have a frequency for up-converting the frequency of the baseband signal BB to the RF band.

The amplifying stage 120 may adjust a gain of the radio frequency signal RF output from the mixer 110. The amplifying stage 120 may include a plurality of unit amplifiers 121 for a dynamic range DR of the radio frequency signal RF. In some example embodiments, the plurality of unit amplifiers 121 may be connected in parallel with each other and may operate in response to the first control signal EN. The first control signal EN may be an enable signal for slicing (e.g., turning on or off) each of the plurality of unit amplifiers 121. The first control signal EN may be a digital signal for controlling each of the plurality of unit amplifiers 121.

In some example embodiments, when the number of unit amplifiers 121 is n (where n is a positive integer), the first control signal EN may have an n-bit amplitude (magnitide). Each of the plurality of unit amplifiers 121 may be turned on or off based on a logic state of each bit of the first control signal EN. The amplifying stage 120 may control the number of unit amplifiers 121 turned on based on the first control signal EN to adjust the gain of the radio frequency signal RF.

The amplifying stage 120 may amplify the radio frequency signal RF through a plurality of unit amplifiers 121 operating in response to the first control signal EN, and may output the amplified RF signal a_rf.

In some example embodiments, when the plurality of unit amplifiers 121 are implemented based on transistors, in the unit amplifiers 121 turned off by the first control signal EN, gate bias of the transistors may be adjusted to the ground voltage VSS. As the gate bias is adjusted to the ground voltage VSS, the input capacitance of the turned-off unit amplifier 121 may be relatively reduced as compared to the input capacitance of the turned-on unit amplifier 121. For example, the input capacitance cin_amp (or impedance) of the amplifying stage 120 may vary depending on the number of unit amplifiers 121 that are turned on or off based on the adjustment of the dynamic range DR.

For example, as the number of turned-off unit amplifiers 121 relatively increases, the input capacitance cin_amp of the amplifying stage 120 may decrease. When the input capacitance cin_amp changes, the tuning frequency of the radio frequency signal RF can be shifted up to a relatively high frequency. Such a shift in tuning frequency may cause degradation in channel flatness.

In some example embodiments, the RF chip 100 may additionally include a compensation capacitor bank 130 between the mixer 110 and the amplification stage 120 to compensate for variations in the input capacitance cin_amp in dependence on the above-described gain adjustment of the amplification stage 120. A compensation capacitor bank 130 may be provided between the mixer 110 and the amplifier stage 120. One end of the compensation capacitor bank 130 may be connected to an output terminal of the mixer 110, and the other end thereof may be connected to an input terminal of the amplifying stage 120. In some example embodiments, the mixer 110 and the amplification stage 120 may be in communication with the compensation capacitor bank 130 (e.g., electrically connected through/via the compensation capacitor bank 130).

The compensation capacitor bank 130 may have a capacitance adjusted based on the second control signal ENB complementary to the first control signal EN. The term "complementary" may mean that the second control signal ENB is configured to control an operation opposite to an operation based on the first control signal EN. For example, the logic level of each bit included in the second control signal ENB may be opposite to the logic level of each bit included in the first control signal EN. The second control signal ENB operates to be complementary to only the first control signal EN, so that when the number of unit amplifiers 121 is n, the second control signal ENB may have an n-bit amplitude similar to the first control signal EN.

In some example embodiments, when the relatively large number of unit amplifiers 121 are turned off based on the first control signal EN, the input capacitance cin_amp of the amplifying stage 120 may be relatively reduced. Accordingly, the second control signal ENB, which is complementary to the first control signal EN, may control the compensation capacitor bank 130 to increase the input capacitance cin_comp of the compensation capacitor bank 130. For example, as the number of the unit amplifiers 121 that are turned off among the plurality of unit amplifiers 121 increases, the capacitance of the compensation capacitor bank 130 may have a larger value.

As an example, when a relatively large number of unit amplifiers 121 are turned on based on the first control signal EN, the input capacitance cin_amp of the amplifying stage 120 may relatively increase. Accordingly, the second control signal ENB, which is complementary to the first control signal EN, may control the compensation capacitor bank 130 to reduce the input capacitance cin_comp of the compensation capacitor bank 130.

According to some example embodiments, the capacitance of the compensation capacitor bank 130 may compensate for the input impedance of the amplifying stage 120 that varies depending on the first control signal EN. Thus, from the output terminal of mixer 110, the input impedance or input capacitance cin_comp of compensation capacitor bank 130 may remain constant regardless of the capacitance change that depends on the gain adjustment of amplifier stage 120.

According to some example embodiments, when the input capacitance cin_amp of the amplifying stage 120 varies depending on the gain adjustment of the amplifying stage 120, the variation may be compensated by a compensation capacitor bank 130 provided between the mixer 110 and the amplifying stage 120 to maintain the tuning frequency and prevent or reduce channel flatness degradation. For example, the compensation capacitor bank 130 may be controlled by a second control signal ENB complementary to the first control signal EN of the amplifying stage 120 for gain adjustment to control the capacitance of the compensation capacitor bank 130 in a direction of compensating for the variation of the input capacitance cin_amp of the amplifying stage 120.

Hereinafter, some exemplary embodiments related to the above-described RF chip will be described in detail.

Referring to fig. 2, an RF chip 200 according to some example embodiments may include mixers 111 and 112, an amplifying stage 120, a compensation capacitor bank 130, and a matching network 140.

Mixers 111 and 112 may receive i_baseband signals bb_i-1 and bb_i-2 and q_baseband signals bb_q-1 and bb_q-2 and mix them with local oscillation signal LO to output RF signals rf_1 and rf_2. Each of the i_base signals bb_i-1 and bb_i-2 may be a differential signal, and each of the q_base signals bb_q-1 and bb_q-2 may also be a differential signal. The first and second i_baseband signals bb_i-1 and bb_i-2 may have opposite phases, and the first and second q_baseband signals bb_q-1 and bb_q-2 may have opposite phases. The i_baseband signals bb_i-1 and bb_i-2 and the q_baseband signals bb_q-1 and bb_q-2 converted to RF frequencies by the mixers 111 and 112 may be integrated by the matching network 140.

Matching network 140 may receive the output signals of mixers 111 and 112 and may output RF signals rf_1 and rf_2. The RF signals rf_1 and rf_2 may be differential signals including a first RF signal rf_1 and a second RF signal rf_2 having opposite phases. In some example embodiments, the matching network 140 may be implemented as a transformer-based network, a shunt (shunt) inductor-based network, an L-network-based network, an LC tank circuit-based network, or the like. Alternatively, the matching network 140 may be omitted, as shown in fig. 1.

The amplifying stage 120 may include a plurality of first unit amplifiers 122 and a plurality of second unit amplifiers 123 that respectively process the differential signals. The plurality of first unit amplifiers 122 may be configured to adjust the gain of the first radio frequency signal rf_1, and the plurality of second unit amplifiers 123 may be configured to adjust the gain of the second radio frequency signal rf_2. The first amplified RF signal a_rf_1 having the gain adjusted by the plurality of first unit amplifiers 122 may be output, and the second amplified RF signal a_rf_2 having the gain adjusted by the plurality of second unit amplifiers 123 may be output.

Each of the plurality of first unit amplifiers 122 and each of the plurality of second unit amplifiers 123 may be turned on or off based on the first control signal EN.

A compensation capacitor bank 130 may be provided between the matching network 140 and the amplification stage 120. The compensation capacitor bank 130 may operate in response to a second control signal ENB that is complementary to the first control signal EN controlling the amplification stage 120 (e.g., as shown in fig. 1). The capacitance of the compensation capacitor bank 130 may be adjusted based on the second control signal ENB, thereby allowing the input capacitance cin_comp of the compensation capacitor bank 130 to be adjusted.

In some example embodiments, the radio frequency signal RF output from the amplification stage 120 may be tuned to a particular tuning frequency. The tuning frequency may be determined based on the input capacitance cin_amp of the amplification stage 120, the capacitance of the compensation capacitor bank 130, and the impedance of the matching network 140. For example, the tuning frequency may be determined based on the input impedance of the output terminals of mixers 111 and 112 or the input terminal of matching network 140. In this case, as described above, the input capacitance cin_amp of the amplifying stage 120 may vary depending on the gain adjustment, and thus, the tuning frequency may also vary.

For example, when the RF chip 200 operates at a low gain, the number of the turned-off unit amplifiers 121 among the plurality of first unit amplifiers 122 and the plurality of second unit amplifiers 123 may be relatively increased. This means a reduction of the input capacitance cin_amp of the amplifier stage 120. The compensation capacitor bank 130 may operate in response to a second control signal ENB complementary to the first control signal EN operating the amplifying stage 120 to compensate for the reduced input capacitance of the amplifying stage 120. Accordingly, even when the input capacitance cin_amp of the amplifying stage 120 varies, the capacitance of the compensation capacitor bank 130 can compensate for the variation of the input capacitance cin_amp of the amplifying stage 120, so that the input impedance of the input terminal of the matching network 140 can be kept constant.

Referring to fig. 3, the compensation capacitor bank 130 may be connected to first differential ports P1-1 and P1-2, the first differential ports P1-1 and P1-2 being connected to the above-described mixer 110 or matching network 140; and to the second differential ports P2-1 and P2-2, which second differential ports P2-1 and P2-2 are connected to the amplifying stage 120. The compensation capacitor bank 130 may include one or more sub-capacitor banks 131_1, 131_2 to 131—k.

One or more of the sub-capacitor banks 131_1, 131_2 to 131—k may operate in response to the commonly applied second control signal ENB. The capacitance of each of the one or more sub-capacitor banks 131_1, 131_2 to 131—k may be adjusted based on the second control signal ENB.

Even when the second control signal ENB is commonly applied, capacitances of the sub-capacitor groups 131_1, 131_2 to 131—k may be different from each other. For example, based on the second control signal ENB, the capacitance of the first sub-capacitor bank 131_1 may be adjusted by Ca, the capacitance of the second sub-capacitor bank 131_2 may be adjusted by Cb, and the capacitance of the third sub-capacitor bank 131—k may be adjusted by Cc, wherein Ca, cb, and Cc may be different real values.

In some example embodiments, each of the sub-capacitor banks 131_1, 131_2 to 131—k may be implemented to have a value that varies depending on the gain step of the amplifying stage 120, the capacitance being adjusted in the amplifying stage 120 based on the first control signal EN. In addition, the sub-capacitor banks 131_1, 131_2 to 131—k may include k sub-capacitor banks (where k is a positive integer), and k may also be set to vary depending on the gain step of the amplifying stage 120.

Fig. 4 is a diagram illustrating the sub-capacitor bank of fig. 3.

Referring to fig. 4, each of the single sub-capacitor banks (e.g., the sub-capacitor bank 131—k as shown in fig. 4) may include a plurality of capacitor adjusting circuits 132_1, 132_2 to 132—n.

The capacitor adjustment circuits 132_1, 132_2 to 132—n may include switches S1, S2 to Sn and unit capacitors C1, C2 to Cn connected to the switches S1, S2 to Sn, respectively. For ease of description, in fig. 4, each capacitor adjustment circuit is shown to include a single unit capacitor. However, in some example embodiments, one or more unit capacitors may be connected to a single switch. The number of the capacitor adjustment circuits 132_1, 132_2 to 132—n may be n, which is the same as the number of the unit amplifiers 121.

The second control signal ENB may be applied to the respective capacitor adjustment circuits 132_1, 132_2 to 132—n to independently operate the capacitor adjustment circuits 132_1, 132_2 to 132—n. For example, when the second control signal ENB is an n-bit signal, the second control signal ENB may be applied to the respective capacitor adjustment circuits 132_1, 132_2 to 132—n in units of bits.

The same number of capacitor adjustment circuits 132_1, 132_2 to 132—n as the plurality of unit amplifiers 121 may be provided for each of the sub-capacitor groups 131_1, 131_2 to 131—k, so that the plurality of capacitor adjustment circuits 132_1, 132_2 to 132—n operate independently. For example, when the number of unit amplifiers 121 is n, n capacitor adjustment circuits 132_1, 132_2 to 132—n may also be provided for each of the sub-capacitor groups 131_1, 131_2 to 131—k.

The switches S1, S2 to Sn respectively included in the capacitor adjustment circuits 132_1, 132_2 to 132—n may be turned on or off based on the second control signal ENB applied in units of bits. For example, when the first control signals EN applied to the amplifying stage 120 in units of bits are EN < n-1>, EN < n-2> and EN <0>, the second control signals ENB applied to the plurality of capacitor adjusting circuits 132_1, 132_2 and 132_n in units of bits may be ENB < n-1>, ENB < n-2> and ENB <0>. Each of ENB < n-1>, ENB < n-2> and ENB <0> may have a logic level different from that of each of EN < n-1>, EN < n-2> and EN <0>.

For example, when EN < n-1>, EN < n-2> and EN <0> have logic levels 1, 1 and 1, respectively, ENB < n-1>, ENB < n-2> and ENB <0> may have logic levels 0, 0 and 0, respectively. In this case, all of the switches S1, S2, and Sn may be turned off. For example, when EN < n-1>, EN < n-2> and EN <0> have logic levels 1, 1 and 0, respectively, ENB < n-1>, ENB < n-2> and ENB <0> may have logic levels 0, 0 and 1, respectively. In this case, among the plurality of capacitor adjustment circuits 132_1, 132_2, and 132—n, only the capacitor adjustment circuit 132—n to which ENB <0> is applied may operate, and the other capacitor adjustment circuits may be turned off. In the above-described exemplary embodiments, n is 3 for clarity of explanation; however, the example embodiments are not limited thereto, and n may be another real number.

According to some example embodiments, in case the capacitor adjusting circuits 132_1, 132_2 to 132—n are not operated because the switches S1, S2 to Sn are turned off, the one or more unit capacitors C1, C2 to Cn connected to the switches S1, S2 to Sn may no longer affect the total capacitance of the sub-capacitor banks 131_1, 131_2 to 131—k.

When m unit amplifiers (where m is a positive integer less than or equal to n) among the n unit amplifiers 121 are turned on based on the first control signal EN, the n-m capacitor adjusting circuits 132_1, 132_2 to 132—n may be turned on based on the switches S1, S2 to Sn operated in response to the second control signal ENB. In some example embodiments, the number n of unit amplifiers 121 and the capacitor adjustment circuits 132_1 to 132—n may be in an on state, wherein a ratio of the on unit amplifiers 121 to the on capacitor adjustment circuits 132_1 to 132—n varies with the first control signal EN and the second control signal ENB.

When the one or more switches S1, S2 to Sn are turned on, the capacitance obtained by summing the equivalent capacitances of the one or more unit capacitors C1, C2 to Cn connected to the turned-on switches S1, S2 to Sn may be the total capacitance of the compensation capacitor bank 130. Accordingly, as the number of unit amplifiers 121 turned off based on the first control signal EN increases, the number of capacitor adjusting circuits 132_1, 132_2 to 132—n turned on based on the second control signal ENB may increase, and thus, the total capacitance of the compensation capacitor bank 130 may also increase. As a result, even when the input capacitance cin_amp of the amplifying stage 120 decreases as the number of turned-off unit amplifiers 121 increases, the decreased capacitance can be compensated by the compensation capacitor bank 130.

Referring to fig. 5, in the RF chip 100, the compensation capacitor bank 130 may be additionally applied with a selection signal (hereinafter, referred to as a "third control signal Sel") for independently operating one or more sub-capacitor banks 131_1, 131_2 to 131—k. The third control signal Sel may be applied to the compensation capacitor bank 130.

The third control signal Sel may be separately applied to the plurality of sub-capacitor banks 131_1, 131_2 to 131—k to select each of the plurality of sub-capacitor banks 131_1, 131_2 to 131—k. When the number of the sub-capacitor banks 131_1, 131_2 to 131—k is k, k third control signals Sel may be applied. In addition, the adjusted capacitances of the sub-capacitor banks 131_1, 131_2 to 131—k may be different from each other.

Among the plurality of sub-capacitor banks 131_1, 131_2 to 131—k, one or more of the sub-capacitor banks 131_1, 131_2 to 131—k may be turned on or off, respectively, based on the third control signal Sel. The fact that each of the sub-capacitor banks 131_1, 131_2 to 131—k is turned off may mean that the capacitances of the turned-off sub-capacitor banks 131_1, 131_2 to 131—k do not affect the total capacitance of the compensation capacitor bank 130, similar to the unit capacitors C1, C2 to Cn described above.

By switching on or off the plurality of sub-capacitor groups 131_1, 131_2 to 131—k based on the third control signal Sel, the rf chip 100 can compensate the capacitance more finely (e.g., accurately, for ground). For example, the capacitances of the first sub-capacitor groups 131_1, 131_2 to 131_k to which the k-1 th third control signal sel_k-1 is applied may be implemented to be higher than the capacitances of the second sub-capacitor groups 131_1, 131_2 to 131_k to which the k-2 th third control signal sel_k-2 is applied. In this case, when the input capacitance cin_amp of the amplifying stage 120 depending on the variation of the first control signal EN is high, the first sub-capacitor groups 131_1, 131_2 to 131—k may be selected to more roughly (e.g., approximately) compensate the capacitance. Alternatively, the second sub-capacitor group 131_1, 131_2 to 131—k may be selected to compensate the capacitance more finely (e.g., accurately, for ground) when the varying input capacitance cin_amp of the amplification stage 120 is low.

Alternatively, two or more sub-capacitor banks 131_1, 131_2 to 131—k may be selected and combined based on the varying input capacitance cin_amp of the amplifying stage 120.

According to example embodiments, as the number k of the plurality of sub-capacitor banks 131_1, 131_2 to 131—k further increases, the capacitance may be more finely compensated. For example, the capacitance may be tuned more finely.

Referring to fig. 6, according to some example embodiments, control circuits 133_1, 133_2 to 133—n controlling the compensation capacitor bank 130 based on the second control signal ENB and the third control signal sel_k (for convenience of description, description about the kth control signal) may be connected to a plurality of capacitor adjusting circuits 132_1, 132_2 to 132—n included in the sub-capacitor banks 131_1, 131_2 to 131—k. The control circuits 133_1, 133_2 to 133—n may be provided plural to be connected to the switches S1, S2 to Sn, respectively.

The control circuits 133_1, 133_2 to 133—n may be connected to a plurality of switches S1, S2 to Sn included in the plurality of capacitor adjustment circuits 132_1, 132_2 to 132—n, respectively. The control circuits 133_1, 133_2 to 133—n may have the second control signal ENB and the third control signal sel_k as inputs. In some example embodiments, the second control signal ENB may be applied to the control circuits 133_1, 133_2 to 133—n (e.g., ENB < n-1> as applied to the control circuit 133_1, etc.) for each unit bit, and the third control signal sel_k may be applied to the control circuits 133_1, 133_2 to 133—n in units of a single sub-capacitor bank 131_1, 131_2, or 131_k. For example, the common third control signal sel_k may be applied to the control circuits 133_1, 133_2 to 133—n connected to the individual sub-capacitor groups 131_1, 131_2 or 131—k.

The control circuits 133_1, 133_2 to 133—n may turn on or off the switches S1, S2 to Sn based on the logic states of the second control signal ENB and the third control signal sel_k, respectively. For example, when the third control signal sel_k instructs the sub-capacitor banks 131_1, 131_2 to 131_k to be turned on, the control circuits 133_1, 133_2 to 133—n may turn on or off each of the switches S1, S2 to Sn based on the logic state of each bit of the second control signal ENB. For example, when the third control signal sel_k instructs to turn off the sub-capacitor banks 131_1, 131_2 to 131_k, the control circuits 133_1, 133_2 to 133—n may turn off all of the switches S1, S2 to Sn. In this case, the individual sub-capacitor bank 131_1, 131_2 or 131—k to which the control circuits 133_1, 133_2 to 133—n are connected may not affect the total capacitance of the compensation capacitor bank 130.

As a result, the control circuits 133_1, 133_2 to 133—n may operate one or more of the plurality of sub-capacitor banks 131_1, 131_2 to 131—k based on the third control signal sel—k, and the plurality of capacitor adjusting circuits 132_1, 132_2 to 132—n respectively included in the operated one or more sub-capacitor banks 131_1, 131_2 to 131—k may be turned on or off based on the second control signal ENB.

According to some example embodiments, the compensation capacitor bank 130 may be controlled by the control circuits 133_1, 133_2 to 133—n. For example, considering that the input capacitance cin_amp of the amplifying stage 120 varies depending on the first control signal EN, some of the sub-capacitor banks 131_1, 131_2 to 131_k among the plurality of sub-capacitor banks 131_1, 131_2 to 131_k having different capacitances may operate, or any of the sub-capacitor banks 131_1, 131_2 to 131_k may operate. As a result, based on the degree of variation in the input capacitance, the capacitance can be compensated more accurately (e.g., over a smaller range) or coarsely (e.g., approximately, over a wider range), and the channel flatness can be improved.

Referring to fig. 7, in operation S1010, the RF chip 100 (or, for example, the RF chip 200) may output a radio frequency signal RF by mixing a local oscillation signal with a baseband signal BB.

In operation S1020, the RF chip 100 or 200 may amplify the radio frequency signal RF through the plurality of unit amplifiers 121 operated in response to the first control signal EN. In this case, at least one of the plurality of unit amplifiers 121 may be turned on or off based on the first control signal EN, and thus the gain of the radio frequency signal RF may be adjusted.

In operation S1030, the RF chip 100 or 200 may adjust the capacitances of the compensation capacitor bank 130 provided at the input terminals of the plurality of unit amplifiers 121 based on the second control signal ENB complementary to the first control signal EN. In this case, when the number of unit amplifiers 121 is n, the first control signal EN and the second control signal ENB may have an amplitude of n bits.

Operation S1030 may be performed to be complementary to operation S1020. For example, the gain of the radio frequency signal RF may be adjusted based on the application of the first control signal EN, and the input capacitance cin_amp of the amplifying stage 120 may be compensated for, which varies depending on the adjustment of the gain of the radio frequency signal RF based on the application of the second control signal ENB.

In some example embodiments, the operation method may further include applying a third control signal Sel to individually operate one or more sub-capacitor banks 131 included in the compensation capacitor bank 130. The applying of the third control signal Sel may be performed together with operation S1030. The control circuits 133_1, 133_2 to 133—n to which the third control signal Sel is applied may turn on or off the compensation capacitor bank 130 and the capacitor adjusting circuits 132_1, 132_2 to 132—n included in the compensation capacitor bank 130 in consideration of the logic states of the second control signal ENB and the third control signal Sel.

Fig. 8A and 8B are diagrams showing amplifier input capacitances based on whether a compensation capacitor bank is present or absent. For convenience of description, in fig. 8A and 8B, the first control signal is illustrated as a 4-bit signal, but example embodiments are not limited thereto.

As can be seen from fig. 8A, in the absence of the compensation capacitor bank 130, as the number of logical "0" bits among the bits of the first control signal EN increases (e.g., the number of turned-off unit amplifiers 121 increases), the input capacitance on the Smith chart (Smith chart) decreases.

Meanwhile, as can be seen from fig. 8B, in the case where the compensation capacitor bank 130 is present, even when the state of the unit amplifier 121 varies depending on the first control signal EN, the input capacitance hardly varies and remains within a predetermined (or alternatively, desired, selected or determined) range, which means that the varying input capacitance cin_amp of the amplifying stage 120 is compensated by the compensation capacitor bank 130.

Fig. 9A and 9B are diagrams showing the channel flatness of the RF signal depending on whether the compensation capacitor bank exists or does not exist. In fig. 9A and 9B, a slice (slice) refers to the number of unit amplifiers 121 that are turned on among the plurality of unit amplifiers 121.

Referring to fig. 9A, in the absence of the compensation capacitor bank 130, when all the unit amplifiers 121 are in the on state, the radio frequency signal RF may be shifted so that the upper and lower sidebands are symmetrical with respect to the frequency (the point at which the offset frequency is zero) of the local oscillation signal. However, as the number of chips decreases, for example, the number of turned-off unit amplifiers 121 increases, the input capacitance cin_amp of the amplifying stage 120 may decrease, and thus, the tuning frequency may gradually shift to a high frequency (may be referred to as a high-shift). Eventually, this may result in poor channel flatness.

Meanwhile, in the case where the compensation capacitor bank 130 is present as in the present disclosure, as can be seen from fig. 9B, the tuning frequency is maintained because the varying input capacitance can be compensated even when the number of chips is reduced. When the tuning frequency is maintained, symmetry (or substantial symmetry) between the upper and lower sidebands can be maintained, and thus, channel flatness can also be maintained or improved.

The retention of the channel refers to a reduction in the power Pout bias in the channel, which means that the performance of the Error Vector Magnitude (EVM) is improved. In addition, the asymmetry between the upper and lower sidebands means that it is asymmetric depending on the Resource Block (RB) power. When the compensation capacitor bank 130 does not exist, calibration should be additionally performed to solve power asymmetry between RBs.

However, when the compensation capacitor bank 130 according to the example embodiment is provided, the asymmetry between RBs may be solved. Thus, there is no need to additionally perform frequency-based calibration.

Fig. 10 is a diagram illustrating an electronic device according to some example embodiments. Hereinafter, detailed descriptions of duplicate technical features will be omitted.

Referring to fig. 10, an electronic device 10 according to some example embodiments may include a processor 11, an RF chip 100, a Front End Module (FEM) 12, and an antenna 13.

The processor 11 may process the digital signal and then convert the digital signal into an analog signal. Alternatively, the processor 11 may convert the analog signal into a digital signal, and then process the digital signal. The converted analog signal or the analog signal to be converted may be a baseband signal BB having a baseband. The processor 11 may transmit the baseband signal BB to the RF chip 100. The processor 11 may be, for example, a modem, an Application Processor (AP), or a modem & application processor (ModAP) in which modem functions are integrated into the AP.

RF chip 100 may up-convert baseband signal BB received from processor 11 to output radio frequency signal RF to FEM 12. The RF chip 100 may be implemented according to some of the example embodiments described above.

In some example embodiments, the RF chip 100 may include a mixer 110, an amplification stage 120, and a compensation capacitor bank 130. The mixer 110 may convert the baseband signal BB transmitted from the processor 11 into an RF band. The gain of the amplifier stage 120 may be adjusted based on the first control signal EN. Each of the plurality of unit amplifiers 121 included in the amplifying stage 120 may be turned on or off based on the first control signal EN, resulting in a change in the input capacitance cin_amp of the amplifying stage 120.

When adjusting the gain of the amplifying stage 120 based on the first control signal EN, the capacitance of the compensation capacitor bank 130 may be adjusted based on the second control signal ENB complementary to the first control signal EN and/or the third control signal Sel for selecting a plurality of capacitors included in the compensation capacitor bank 130. In some example embodiments, the second control signal ENB and/or the third control signal Sel may be applied to the RF chip 100 through the processor 11.

Thus, the variation of the input capacitance cin_amp of the amplifying stage 120 can be compensated by the capacitance of the compensation capacitor bank 130. Then, the input capacitance may remain constant as seen from the output terminal of the mixer 110. As a result, the tuning frequency of the radio frequency signal RF can be maintained regardless of the operation of the amplifying stage 120, and thus, degradation of the channel flatness can be prevented or reduced.

FEM 12 may be configured to amplify a radio frequency signal RF output from RF chip 100 or to direct the amplified radio frequency signal RF to one or more signal paths. To this end, FEM 12 may include one or more power amplifiers Pa and one or more switches. FEM 12 may be connected to RF chip 100 through various connection interfaces (e.g., mobile Industrial Processor Interface (MIPI), etc.), and may operate under control of RF chip 100.

Antenna 13 may transmit radio frequency signals RF received from FEM 12 to another wireless communication device.

Although the electronic device 10 according to some example embodiments has been described in terms of a transmit chain, the electronic device 10 may include a receive chain (Rx chain). In this case, the electronic device 10 may perform operations to process the received radio frequency signal RF.

As described above, according to example embodiments, an RF chip that improves channel flatness may be provided.

As described herein, any electronic device and/or portion thereof according to any example embodiment may include, may be included in, and/or may be implemented by: one or more instances of processing circuitry, such as hardware including logic circuitry; a hardware/software combination such as a processor executing software; or any combination thereof. For example, the processing circuitry may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a Graphics Processing Unit (GPU), an Application Processor (AP), a Digital Signal Processor (DSP), a microcomputer, a Field Programmable Gate Array (FPGA) and programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), a neural Network Processing Unit (NPU), an Electronic Control Unit (ECU), an Image Signal Processor (ISP), and the like. In some example embodiments, the processing circuitry may include: a non-transitory computer readable storage device (e.g., a memory) storing a program of instructions, such as a DRAM device; and a processor (e.g., a CPU) configured to execute a program of instructions to implement functions and/or methods performed by any and/or any portion of the devices, systems, modules, units, controllers, circuits, architectures, and/or portions thereof in accordance with the example embodiments.

Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A Radio Frequency (RF) chip comprising:

a mixer configured to mix a local oscillation signal with a baseband signal to output an RF signal;

an amplifying stage configured to amplify the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and

a compensation capacitor bank is provided between the mixer and the amplification stage, the compensation capacitor bank being configured to adjust a capacitance of the compensation capacitor bank based on a second control signal, the second control signal being complementary to the first control signal.

2. The RF chip of claim 1 wherein

Each of the plurality of unit amplifiers is configured to be turned off or on by the first control signal.

3. The RF chip of claim 1 wherein

The compensation capacitor bank includes one or more sub-capacitor banks, each sub-capacitor bank including a plurality of capacitor adjustment circuits.

4. The RF chip of claim 3 wherein

Each of the plurality of capacitor adjustment circuits includes:

a switch configured to be turned on or off based on the second control signal; and

one or more unit capacitors connected to the switch.

5. The RF chip of claim 3 wherein

The number of the plurality of capacitor adjustment circuits is the same as the number of the plurality of unit amplifiers, wherein the number of the plurality of unit amplifiers is n, and n is a positive integer.

6. The RF chip of claim 5 wherein

Based on m unit amplifiers being turned on, m is less than or equal to n, n-m capacitor adjustment circuits of the plurality of capacitor adjustment circuits are configured to be turned on based on the second control signal.

7. The RF chip of claim 2 wherein

The capacitance increases based on an increase in the number of turned-off unit amplifiers among the plurality of unit amplifiers.

8. The RF chip of claim 3, further comprising:

a control circuit configured to control the compensation capacitor bank based on the second control signal and a third control signal for independently operating the one or more sub-capacitor banks.

9. The RF chip of claim 8 wherein

The one or more sub-capacitor banks are each configured to be turned on or off based on the third control signal, and

the plurality of capacitor adjustment circuits are each configured to be turned on or off based on the second control signal.

10. The RF chip of claim 1 wherein

The compensation capacitor bank is configured to adjust the capacitance to compensate for an input impedance of the amplification stage, the input impedance varying based on the first control signal.

11. The RF chip of claim 1 wherein

Based on the number of the plurality of unit amplifiers being n, each of the first control signal and the second control signal has an amplitude of n bits.

12. The RF chip of claim 1, further comprising:

a matching network between the mixer and the compensation capacitor bank.

13. A method of operation, comprising:

outputting a Radio Frequency (RF) signal by mixing the baseband signal with a local oscillation signal;

amplifying the RF signal by a plurality of unit amplifiers operating in response to a first control signal; and

the capacitance of the compensation capacitor bank provided at the input terminals of the plurality of unit amplifiers is adjusted based on a second control signal, which is complementary to the first control signal.

14. The method of operation of claim 13, further comprising:

a third control signal is applied to independently operate one or more sub-capacitor banks included in the compensation capacitor bank.

15. The method of operation of claim 13, wherein

16. An electronic device, comprising:

a processor;

a Radio Frequency (RF) chip configured to receive a baseband signal from the processor and output an RF signal from the baseband signal;

a Front End Module (FEM) configured to amplify the RF signal; and

an antenna configured to transmit the RF signal,

the RF chip may include a plurality of RF chips,

a mixer configured to mix a local oscillation signal with the baseband signal to output the RF signal;

17. The electronic device of claim 16, wherein

The compensation capacitor bank includes one or more sub-capacitor banks, each sub-capacitor bank including a plurality of capacitor adjustment circuits, and

providing as many of the plurality of capacitor adjustment circuits as the plurality of unit amplifiers.

18. The electronic device of claim 17, wherein

Based on m unit amplifiers being turned on, m being less than or equal to n, n being the number of the plurality of unit amplifiers, n-m capacitor adjustment circuits of the plurality of capacitor adjustment circuits are configured to be turned on based on the second control signal.

19. The electronic device of claim 17, further comprising:

the RF chip further includes a control circuit configured to control the compensation capacitor bank based on the second control signal and a third control signal for independently operating the one or more sub-capacitor banks.

20. The electronic device of claim 16, wherein

The compensation capacitor bank is configured to adjust the capacitance to compensate for an input impedance of the amplification stage, the input impedance varying in dependence on the first control signal.