KR20110064051A - Method of manufacturing of thin film transistor substrate - Google Patents

Abstract

PURPOSE: A method for manufacturing a thin film transistor is provided to form a dummy pad electrode on a data pad electrode to position an etching bottom on the same line as an electrode of the thin film transistor, thereby obtaining a process margin during an etching process. CONSTITUTION: A gate electrode(121) is formed in a TFT area(TFT) by using a first conductive material. A lower electrode(122) is formed on a capacitor area(Cst) of a device substrate(110). A crystallized silicon film(124a) is formed on a gate insulating layer(112) formed on the frontal surface of the device substrate. A source electrode(126) and a drain electrode(127) are formed on the crystallized silicon film by using a second conductive material. A data pad electrode(129) is formed on the device substrate.

Description

Method for manufacturing thin film transistor substrate {METHOD OF MANUFACTURING OF THIN FILM TRANSISTOR SUBSTRATE}

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate capable of improving device characteristics and securing process margins.

Recently, various display devices that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed. Such display devices include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic electroluminescent displays using electroluminescent devices. -luminescence Display Device (OLED).

As the switching element used in the aforementioned display device, a thin film transistor formed at an intersection point of a gate line and a data line is used. The thin film transistors are broadly classified into bottom gate and top gate structures according to the positions of the gate electrodes.

The thin film transistor is electrically connected to the gate line and the data line, receives a gate signal from a gate pad electrically connected to the gate line, and receives a data signal from a data pad electrically connected to the data line to drive the pixel. .

The gate pad electrode of the gate pad is formed at the same time as the gate electrode forming process in manufacturing the thin film transistor, and the data pad electrode of the data pad is formed at the same time in the source / drain electrode forming process in manufacturing the thin film transistor.

However, the etching rate of the gate electrode of the thin film transistor and the gate pad electrode of the gate pad or the source / drain electrode of the thin film transistor and the data pad electrode of the data pad are different from each other due to the step difference between the upper and lower insulating layers.

That is, since the etching process is performed based on the thickness of the thick insulating film, the gate pad electrode or the data pad electrode having the relatively thin insulating film is damaged during the etching process. The damaged gate pad electrode or data pad electrode may not properly supply a signal to the thin film transistor and may reduce the response speed, thereby reducing the reliability of the display device.

In order to solve the above problems, the present invention is to provide a method for manufacturing a thin film transistor substrate capable of improving device characteristics and process margins.

In the method of manufacturing a thin film transistor substrate according to the present invention, a gate electrode is formed in the thin film transistor region using a first conductive material on a device substrate defined as a thin film transistor region, a capacitor region, a gate pad region, and a data pad region. Forming a lower electrode in a capacitor region, forming a crystallized silicon film on the gate insulating film formed on the entire surface of the device substrate, the thin film transistor region, the capacitor region, and the data pad region, respectively; A source electrode and a drain electrode on the crystallized silicon film of the thin film transistor region and a first upper electrode and the crystallized silicon of the data pad region on the crystallized silicon film of the capacitor region using a second conductive material Data pad electrode on the film Forming a first contact hole exposing the gate electrode, a second contact hole exposing the drain electrode, a third contact hole exposing the lower electrode, and a fourth contact hole exposing the data pad electrode; Forming a first planarization film having a gate line, a gate line in the first contact hole, a drain dummy electrode in the second contact hole, a second upper electrode in the third contact hole, and the fourth using a third conductive material Forming a gate pad electrode on the data dummy pad electrode and the first planarization layer of the gate pad region in the contact hole, and a second planarization exposing the drain dummy electrode, the gate pad electrode, and the data dummy pad electrode. Forming a film.

Another method of manufacturing a thin film transistor substrate according to the present invention forms a thin film transistor including a drain electrode in a thin film transistor region on a device substrate defined as a thin film transistor region, a capacitor region, a gate pad region, and a data pad region, and the data pad Forming a data pad electrode in an area, forming a first planarization film exposing the drain electrode and the data pad electrode, and drain drain on the exposed drain electrode such that an upper surface of the electrode is on the same line Forming a gate pad electrode on an electrode, the data dummy pad electrode on the exposed data pad electrode, and the first planarization layer of the gate pad region, and the device such that the drain dummy electrode and the data dummy pad electrode are exposed. A second planarization film on the substrate And a step of sex.

In the forming of the second planarization layer, a hydrogenation path is formed through the drain dummy electrode and the data dummy pad electrode to the drain electrode and the data pad electrode.

An upper surface of the drain dummy electrode in the second contact hole and the data dummy pad electrode in the fourth contact hole may be disposed on the same line, or an etch bottom surface of the second planarization layer of the thin film transistor region and the data pad region may be disposed on the same line. It is located on the same line.

The first planarization film is formed of a silicon oxide film, and the second planarization film is formed of a silicon nitride film.

Mo is used as the first conductive material, a multilayer structure of Mo / AlNd / Mo is used as the second conductive material, and a multilayer structure of Mo / AlNd is used as the third conductive material.

The forming of the crystallized silicon film may include forming an amorphous silicon film on the gate insulating film, forming an insulating material layer on the amorphous silicon film, forming a thermal transfer layer on the insulating material layer; Generating heat in the thermal transfer layer using an infrared laser, and transferring the heat to the amorphous silicon film to crystallize the amorphous silicon film.

According to the present invention, by forming a dummy pad electrode on the data pad electrode without an additional process, an etching bottom surface is positioned on the same line as the electrode of the thin film transistor, thereby securing a process margin in the etching process.

In addition, the present invention can prevent damage to the electrode to improve the reliability of the display device.

In addition, since the hydrogenation path by the insulating layer is secured by the formation of the drain dummy electrode and the data dummy pad electrode, the device characteristics may be improved by improving the response speed of the device and lowering the driving voltage.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1, first, a first conductive layer is formed on a device substrate 110 defined as a thin film transistor region TFT, a capacitor region Cst, a gate pad region G-Pad, and a data pad region D-Pad. After depositing the material, the gate electrode 121 and the lower electrode 122 are formed by patterning the first conductive material by a photolithography process and an etching process.

The gate electrode 121 is formed on the device substrate 110 of the thin film transistor region TFT, and the lower electrode 122 is formed on the device substrate 110 of the capacitor region Cst.

As the first conductive material, a single layer or multilayer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), chromium (Cr), and alloys thereof is used. However, the present invention is not limited thereto, and it is preferable to use molybdenum as the first conductive material in terms of subsequent processes.

Meanwhile, before the gate electrode 121 and the lower electrode 122 are formed of the first conductive material, a sacrificial layer (not shown) may be formed on the device substrate 110.

Referring to FIG. 2, after the gate insulating layer 112 is formed on the entire surface of the device substrate 110 on which the gate electrode 121 and the lower electrode 122 are formed, the amorphous silicon film 124, the insulating material layer 114, and The thermal transfer layer 115 is sequentially deposited. Subsequently, the amorphous silicon film 124 under the thermal transfer layer 115 is crystallized by using an IR laser.

The gate insulating layer 112 may be formed of a single layer or multiple layers of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the entire surface of the device substrate 110 on which the gate electrode 121 and the lower electrode 122 are formed. It can be formed as. The amorphous silicon film 124 may be formed on the entire surface of the device substrate 110 on which the gate insulating film 112 is formed through a deposition method such as PECVD.

The insulating material layer 114 is a layer for preventing the silicide layer from being formed on the amorphous silicon film 124 in the crystallization process. The insulating material layer 114 may be formed of an inorganic insulating material such as a silicon nitride film or a silicon oxide film.

The thermal transfer layer 115 transfers heat to solidify the amorphous silicon film 124. The thermal transfer layer 115 is formed on the entire surface of the device substrate 110 on which the insulating material layer 114 is formed using a material having a high absorption rate of an infrared laser. . The thermal transfer layer 115 may be formed of a metal such as molybdenum (Mo), molybdenum / titanium alloy (Mo / Ti), or copper (Cu) to increase thermal conductivity. The thermal transfer layer 115 is preferably formed using molybdenum.

Referring to FIG. 3, after the crystallized silicon film 124a is formed, the thermal transfer layer 115 is etched and removed, and the insulating material layer 114 is patterned to form an etch stopper 114a. .

The etch stopper 114a is for preventing the channel region from being damaged in the etching process. The etch stopper 114a is formed on the silicon film 124a crystallized to overlap the gate electrode 121 and the lower electrode 122 of the capacitor with the gate insulating film 112 and the crystallized silicon film 124a therebetween. do.

Referring to FIG. 4, an n + layer 125 is formed on the entire surface of the device substrate 110 on which the etch stopper 114a is formed.

Referring to FIG. 5, after depositing a second conductive material over the device substrate 110, the source electrode 126, the drain electrode 127, and the capacitor region (TFT) may be formed in the thin film transistor region TFT through photolithography and etching processes. The first upper electrode 128 is formed at Cst and the data pad electrode 129 is formed at the data pad region D-Pad.

The source electrode 126 and the drain electrode 127 are formed with the gate insulating film 112, the crystallized silicon film 124a, and the n + layer 125 interposed therebetween so as to vertically overlap the gate electrode 121. It is spaced apart and formed to overlap both sides of the etch stopper (114a).

The first upper electrode 128 of the capacitor region Cst overlaps the lower electrode 122 with the gate insulating layer 112, the crystallized silicon film 124a, the etch stopper 114a, and the n + layer 125 interposed therebetween. It is formed to be.

The data pad electrode 129 is formed on the device substrate 110 with the gate insulating film 112, the crystallized silicon film 124a, and the n + layer 125 interposed therebetween.

As the second conductive material, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), chromium (Cr), or an alloy thereof may be used as a single layer or a multilayer structure. As the second conductive material, a multilayer structure of Mo / AlNd / Mo may be used.

Referring to FIG. 6, data of the source electrode 126 and the drain electrode 127 of the thin film transistor region TFT, the first upper electrode 128 of the capacitor region Cst, and the data pad region D-Pad Using the pad electrode 129 as a mask, the exposed n + layer 125 and the crystallized silicon film 124a below are etched.

As a result, the n + layer 125 and the crystallized silicon film 124a exist only under the source electrode 126, the drain electrode 127, the first upper electrode 128, and the data pad electrode 129, and partially. The gate insulating layer 112 is exposed. This completes the thin film transistor in the thin film transistor region TFT.

Referring to FIG. 7, after depositing the first planarization layer 116 on the entire surface of the device substrate 110, the first contact hole 151 and the drain electrode exposing the gate electrode 121 are exposed through a patterning process. A second contact hole 152, a third contact hole 153 exposing the lower electrode 122 of the capacitor region Cst, and a fourth contact hole 154 exposing the data pad electrode 129 are formed.

The first planarization layer 116 may be formed of a single layer of a silicon oxide layer (SiO ₂ ), a silicon nitride layer (SiNx), or a plurality of layers thereof by PECVD deposition. The first planarization layer 116 may be formed using a silicon oxide layer.

Referring to FIG. 8, after depositing a third conductive material on the device substrate 110 on which the first contact holes 151 to the fourth contact holes 154 are formed, the gate line 131 is formed through a photolithography process and an etching process. The drain dummy electrode 132, the second upper electrode 133, the gate pad electrode 134, and the data dummy pad electrode 136 are simultaneously formed.

As the third conductive material, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), chromium (Cr), or an alloy thereof may be used as a single layer or a multilayer structure. As the third conductive material, a multilayer structure of Mo / AlNd may be used.

The gate line 131 extends from the first contact hole 151 to the first planarization layer 116 to be electrically connected to the gate electrode 121 exposed through the first contact hole 151. Forming the gate line 131 using the third conductive material ensures resistance of the gate electrode 121 made of the first conductive material, and damages the lower gate electrode 121 in the crystallization step of the amorphous silicon film. This is to prevent.

The drain dummy electrode 132 is formed to fill the second contact hole 152 on the drain electrode 127 to be electrically connected to the drain electrode 127 exposed through the second contact hole 152.

The second upper electrode 133 of the capacitor region Cst is electrically connected to the lower electrode 122 exposed through the third contact hole 153, and from the inside of the third contact hole 153 the first upper electrode ( It extends to the first planarization film 116 overlapping with the 128.

The gate pad electrode 134 is formed on the first planarization layer 116 of the gate pad region G-Pad. The data dummy pad electrode 136 is formed to fill the fourth contact hole 154 on the data pad electrode 129 to be electrically connected to the data pad electrode 129 exposed through the fourth contact hole 154. .

9, the gate line 131, the drain dummy electrode 132, the second upper electrode 133, the gate pad electrode 134, and the data dummy pad electrode 136 are formed on the entire surface of the device substrate 110. After depositing the second planarization layer 118, the sixth contact hole 156, the seventh contact hole 157, and the eighth contact hole 158 are formed through a patterning process.

The second planarization layer 118 may be formed of a single layer or a plurality of layers of a silicon oxide layer (SiO ₂ ), a silicon nitride layer (SiNx) by PECVD deposition. The second planarization layer 118 may be formed using a silicon nitride layer.

The sixth contact hole 156 exposes the drain dummy electrode 132, the seventh contact hole 157 exposes the gate pad electrode 134, and the eighth contact hole 158 includes the data dummy pad electrode 136. ).

As described above, in the present invention, the drain dummy electrode is formed on the drain electrode and the dummy pad electrode is simultaneously formed on the data pad electrode without any additional process, so that the drain electrode and the upper surface of the pad electrode of the thin film transistor are on the same line. Can be located.

Alternatively, the process margin may be secured by having the etch bottom surface of the second planarization layer 118 of the thin film transistor region TFT and the data pad region D-Pad be positioned on the same line. In addition, damage to the drain electrode and the data pad electrode may be prevented to improve reliability of the display device.

In addition, the present invention forms a dummy electrode on the drain electrode and the data pad electrode, so that the hydrogenation path by the second planarization film Passi2 made of silicon nitride film SiNx drains through the dummy electrode as shown in FIG. 11. Since the electrode and the data pad electrode are secured to each other, the device characteristics may be improved, such as improving the response speed of the device and lowering the driving voltage.

Referring to FIG. 10, a thin film transistor substrate is completed by forming pixel electrode pattern groups 142, 144, and 146 electrically connected to the drain electrode 127, the gate pad electrode 134, and the data pad electrode 129. . The pixel electrode pattern groups 142, 144, and 146 may be formed on the drain dummy electrode 132, the gate pad electrode 134, and the data dummy pad electrode 134 using a-ITO.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 to 10 are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.

11 is a view for explaining a hydrogenation path by the dummy electrode according to the present invention.

<< Explanation of symbols for main part of drawing >>

110: device substrate 112: gate insulating film

116: first planarization film 118: second planarization film

127: drain electrode 129: data pad electrode

132: drain dummy electrode 136: data dummy pad electrode

Claims (9)

Forming a gate electrode on the thin film transistor region using a first conductive material on a device substrate defined as a thin film transistor region, a capacitor region, a gate pad region, and a data pad region, and forming a lower electrode on the capacitor region; Forming a crystallized silicon film on the gate insulating film formed on the entire surface of the device substrate, the thin film transistor region, the capacitor region, and the data pad region; A source electrode and a drain electrode on the crystallized silicon film of the thin film transistor region using the second conductive material, and the crystallization of the first upper electrode and the data pad region on the crystallized silicon film of the capacitor region. Forming a data pad electrode on the silicon film; A first planarization layer having a first contact hole exposing the gate electrode, a second contact hole exposing the drain electrode, a third contact hole exposing the lower electrode, and a fourth contact hole exposing the data pad electrode; Forming; A gate line in the first contact hole, a drain dummy electrode in the second contact hole, a second upper electrode in the third contact hole, a data dummy pad electrode in the fourth contact hole and the gate using a third conductive material Forming a gate pad electrode on the first planarization layer of the pad region; And And forming a second planarization layer exposing the drain dummy electrode, the gate pad electrode, and the data dummy pad electrode. The thin film transistor substrate of claim 1, wherein in the forming of the second planarization layer, a hydrogenation path is formed through the drain dummy electrode and the data dummy pad electrode to the drain electrode and the data pad electrode. Way. The method of claim 1, wherein an upper surface of the drain dummy electrode in the second contact hole and the data dummy pad electrode in the fourth contact hole are positioned on the same line, And the etch bottom surface of the second planarization layer of the thin film transistor region and the data pad region is on the same line. The method of claim 1, wherein the first planarization film is formed of a silicon oxide film, And the second planarization film is formed of a silicon nitride film. The method of claim 1, wherein Mo is used as the first conductive material, As the second conductive material, a multilayer structure of Mo / AlNd / Mo is used, The third conductive material is a thin film transistor substrate manufacturing method characterized in that a multi-layer structure of Mo / AlNd. The method of claim 1, wherein forming the crystallized silicon film Forming an amorphous silicon film on the gate insulating film; Forming an insulating material layer on the amorphous silicon film; Forming a thermal transfer layer on the insulating material layer; and And generating heat in the thermal transfer layer by using an infrared laser, and transferring the heat to the amorphous silicon film to crystallize the amorphous silicon film. Forming a thin film transistor including a drain electrode in a thin film transistor region on a device substrate defined as a thin film transistor region, a capacitor region, a gate pad region, and a data pad region, and forming a data pad electrode in the data pad region; Forming a first planarization layer exposing the drain electrode and the data pad electrode; A drain dummy electrode on the exposed drain electrode such that an upper surface of the electrode is on the same line, a data dummy pad electrode on the exposed data pad electrode, and a gate pad electrode on the first planarization layer of the gate pad area. Forming a; And Forming a second planarization layer on the device substrate such that the drain dummy electrode and the data dummy pad electrode are exposed. The method of claim 7, wherein the first planarization film is formed of a silicon oxide film, And the second planarization film is formed of a silicon nitride film. The thin film transistor substrate of claim 7, wherein in the forming of the second planarization layer, a hydrogenation path is formed through the drain dummy electrode and the data dummy pad electrode to the drain electrode and the data pad electrode. Way.

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