KR20110060607A - Buffer circuit - Google Patents

Abstract

PURPOSE: A buffer circuit is provided to be applied to a single ended type and differential type by controlling a selection signal. CONSTITUTION: In a buffer circuit, a first amplification unit(110) amplifies the difference between a single signal and a reference voltage. A first amplification unit amplifies the difference between differential signals and generates a first differential amplifier signal. A second amplification unit(120) amplifies the difference between a single signal and a reference voltage and generates a second differential amplifier signal. A switching unit(130) supplies a differential signal to the first amplification unit. The differential signal is inputted through a second pad.

Description

Buffer circuit {BUFFER CIRCUIT}

The present invention relates to a semiconductor circuit, and more particularly to a buffer circuit.

Buffer circuits are used in various fields in semiconductor circuits, and are typically used as circuit configurations for data input.

The signal transmission method between the semiconductor circuit and the external device may be classified into a single ended type and a differential type.

In the single-ended type, an independent signal is input for each input terminal, that is, a pad, and in the differential type, a differential signal having opposite phases is input through two pads.

The buffer circuit is configured to fit each of the single ended type and the differential type.

As shown in FIG. 1, a buffer circuit 10 according to a conventional single-ended type is provided for each pad DQ0, DQ1,...

At this time, independent signals are input for each pad DQ0, DQ1, ....

The buffer circuit 10 includes a first amplifier 11 and a second amplifier 12.

The first amplifier 11 of the buffer circuit 10 includes a plurality of transistors M1 to M3 and a plurality of resistors R1 and R2, and the second amplifier 12 includes a plurality of transistors M4 to M8. It consists of

The buffer circuit 10 is differential based on a result of comparing the voltage level of the signal input through the pad DQ0 with the reference voltage VREF during the period in which the enable signal EN is activated. Generate amplified signals A and B.

The second amplifier 12 of the buffer circuit 10 performs a current mirroring operation according to the differential amplification signals A and B to generate an output signal OUT0.

The buffer circuit 20 is configured in the same manner as the buffer circuit 10 and operates in the same manner as the buffer circuit 10 to generate the output signal OUT1.

As shown in FIG. 2, the buffer circuit 30 according to the differential type is provided one by one for two pads DQ0 + and DQ0-.

At this time, differential signals having opposite phases are inputted through the two pads DQ0 + and DQ0-.

The buffer circuit 30 includes a first amplifier 11 and a second amplifier 12.

The buffer circuit 30 is configured similarly to the buffer circuit 10 of FIG. 1. However, instead of applying the reference voltage VREF to the transistor M2, the pad DQ0- is connected.

The buffer circuit 30 has a voltage level of a signal input by the first amplifier 11 through the pad DQ0 + and a voltage of a signal input through the pad DQ0- during the period in which the enable signal EN is activated. According to the result of comparing the levels, differential amplified signals A and B are generated.

The second amplifier 12 of the buffer circuit 30 performs a current mirroring operation according to the differential amplification signals A and B to generate an output signal OUT0.

As described above, the buffer circuit according to the prior art should configure the buffer circuit in different forms according to the signal transmission method.

Therefore, the differential type signal cannot be transmitted using the buffer circuit configured for the single ended type, and the single ended type signal cannot be transmitted using the buffer circuit configured for the differential type.

An embodiment of the present invention amplifies the difference between the single signal input through the first pad and the reference voltage in response to the selection signal, or amplifies the difference between the differential signal input through the first pad and the second pad. A first amplifier configured to generate a differential amplified signal, and a second amplifier configured to amplify a difference between the single signal input through the second pad and the reference voltage in response to the selection signal to generate a second differential amplified signal And a switching unit configured to provide a differential signal input through the second pad to the first amplifier in response to the inverted selection signal.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 3, the buffer circuit 100 according to the embodiment of the present invention is an example of a two-stage buffer circuit, and includes a first amplifier 110 and a second amplifier 120. ), A switching unit 130, a third amplifier 140, and a fourth amplifier 150.

The first amplifier 110 and the second amplifier 120 are connected to the pair of pads DQ0 / DQ0 + and DQ1 / DQ0-.

In this case, the pair of pads DQ0 / DQ0 + and DQ1 / DQ0- receive signals independent of each other, that is, a single ended signal in the case of a single-ended type, and a differential signal in the case of a differential type. ) Input.

The embodiment of the present invention is an example designed to fit the case where the select signal SEL is high level in the single-ended method and low level in the differential method. In addition, a mode register set (MRS) signal or a test signal may be used as the selection signal SEL.

The first amplifier 110 amplifies the difference between the single signal input through the pads DQ0 / DQ0 + and the reference voltage VREF in response to the selection signal SEL, or the pair of pads DQ0 / DQ0 + and DQ1. / DQ0-) to amplify the difference between the differential signals inputted to generate the first differential amplified signals (C, D).

The first amplifier 110 includes a plurality of resistors R11 and R12 and a plurality of transistors M11 to M17. The pads DQ0 / DQ0 + are connected to the gate of the transistor M13, the selection signal SEL is input to the gates of the transistors M12 and M16, and the reference voltage VREF is applied to the gate of the transistor M14. .

The second amplifier 120 amplifies the difference between the single signal inputted through the pads DQ1 and DQ0- and the reference voltage VREF in response to the selection signal SEL to allow the second differential amplified signals E and F to be amplified. It is configured to generate.

The second amplifier 120 includes a plurality of resistors R21 and R22 and a plurality of transistors M21 to M27. The pads DQ1 / DQ0- are connected to the gate of the transistor M23, the select signal SEL is input to the gates of the transistors M21, M22, M25, and M26, and the reference voltage (M) is applied to the gate of the transistor M24. VREF) is applied.

The switching unit 130 is configured to provide the first amplifying unit 110 with a differential signal input through the pads DQ1 / DQ0- in response to the inverted selection signal SELB.

The switching unit 130 includes a plurality of transistors T1 and T2.

The transistor T1 has a drain connected to the drain of the transistor M12, a source connected to the drain of the transistor M23, and an inverted selection signal SELB is input to the gate.

The transistor T2 has a source connected to the source of the transistor M16, a drain connected to the source of the transistor M23, and an inverted selection signal SELB is input to the gate.

The third amplifier 140 is configured to amplify the difference between the first differential amplified signals C and D to generate the first output signal OUT0.

The third amplifier 140 includes a plurality of transistors M31 ˜ M34 forming a current mirror structure and a transistor M35 that opens a current path of the current mirror in response to the enable signal EN. .

The fourth amplifier 150 is configured to amplify the difference between the second differential amplified signals E and F in response to the selection signal SEL to generate the second output signal OUT1.

The fourth amplifier 150 may include a plurality of transistors M41 to M44 constituting the current mirror circuit, a transistor M45 for controlling whether the current mirror is opened or not in response to the enable signal EN, and an enable signal. And an AND gate AND11 that logically multiplies the signal EN and the selection signal SEL to provide the gate of the transistor M45.

The operation of the buffer circuit 100 according to the embodiment of the present invention configured as described above will be described with reference to FIGS. 4 and 5.

First, when the signal transmission method is a single-ended method, the operation of the buffer circuit 100 will be described with reference to FIG. 4.

As described above, in the single-ended mode, the selection signal SEL is at a high level, and the inverted selection signal SELL is provided at a low level. It is also assumed that the enable signal EN is activated to a high level.

Since the selection signal SEL is at a high level, the transistors M12, M16, M21, M22, M25, and M26 are turned on. On the other hand, since the inverted select signal SELB is at the low level, the transistors T1 and T2 constituting the circuit configuration, that is, the switching unit 130 shown in dotted lines in FIG. 4 are turned off.

Accordingly, the first amplifier 110 generates the first differential amplified signals C and D by amplifying a difference between the data D0 and the reference voltage VREF input through the pads DQ0 / DQ0 +.

The third amplifier 140 amplifies the difference between the first differential amplified signals C and D to generate a first output signal OUT0.

The second amplifier 120 generates second differential amplified signals E and F by amplifying a difference between the data D1 and the reference voltage VREF input through the pads DQ1 and DQ0-.

The fourth amplifier 140 amplifies the difference between the second differential amplified signals E and F to generate a second output signal OUT1.

As a result, the buffer circuit 100 performs independent data input operations with respect to the different single signals D0 and D1 input through the pads DQ0 / DQ0 + and the pads D1 / DQ0-.

Next, when the signal transmission method is the differential method, the operation of the buffer circuit 100 will be described with reference to FIG. 5.

In the differential method, the select signal SEL is at a low level, and the inverted select signal SELB is provided at a high level. It is also assumed that the enable signal EN is activated to a high level.

Since the select signal SEL is at a low level, the transistors M12, M16, M21, M22, M25, and M26 are turned off. Meanwhile, since the inverted select signal SELB is at a high level, the transistors T1 and T2 of the switching unit 130 are turned on.

Therefore, the first amplifier 110 inputs one of the two inputs through the pads DQ1 / DQ0- instead of the reference voltage VREF as the other one of the differential data D0 + input through the pads DQ0 / DQ0 +. Received differential data (D0-).

On the other hand, the circuit configuration shown by the dotted line in Figure 5, that is, the second amplifier 120 and the fourth amplifier 150 is a current path is cut off the operation is stopped. At this time, the fourth amplifier 150 is turned off according to the deactivated selection signal SEL, the operation is stopped.

Accordingly, the first amplifier 110 amplifies the difference between the differential signals D0 + and D0- input through the pair of pads DQ0 / DQ0 + and DQ1 / DQ0- so as to amplify the first differential amplified signals C and D. Create

The third amplifier 140 amplifies the difference between the first differential amplified signals C and D to generate a first output signal OUT0.

As a result, the data input operation for the differential signals D0 + and D0- input through the pads DQ0 / DQ0 + and the pads D1 / DQ0- is performed by the buffer circuit 100.

As described above, the buffer circuit 100 according to the embodiment of the present invention can be used for both the single-ended type and the differential type by controlling the selection signal SEL.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a single-ended type buffer circuit according to the prior art;

2 is a circuit diagram of a differential type buffer circuit according to the prior art;

3 is a circuit diagram of a buffer circuit according to an embodiment of the present invention;

4 and 5 are circuit diagrams for describing an operation of a buffer circuit according to an exemplary embodiment of the present invention.

Claims (4)

Amplifying a difference between a single signal input through the first pad and a reference voltage in response to the selection signal, or amplifying a difference between the differential signal input through the first pad and the second pad to generate a first differential amplified signal; A first amplifier configured; A second amplifier configured to amplify a difference between the single signal input through the second pad and the reference voltage in response to the selection signal to generate a second differential amplified signal; And And a switching unit configured to provide a differential signal input through the second pad to the first amplifier in response to an inverted selection signal. The method of claim 1, A third amplifier configured to amplify the difference between the first differentially amplified signal to generate a first output signal, and And a fourth amplifier configured to amplify the difference of the second differentially amplified signal to generate a second output signal. The method of claim 2, And the fourth amplifier is configured to stop an operation in response to the selection signal. The method of claim 2, The fourth amplification unit Current mirror circuit, A switching device for determining whether to open the current path of the current mirror; And a logic element controlling the switching element in accordance with the selection signal.

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