KR20110060416A - Semiconductor memory apparatus - Google Patents

Semiconductor memory apparatus Download PDF

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Publication number
KR20110060416A
KR20110060416A KR1020090116999A KR20090116999A KR20110060416A KR 20110060416 A KR20110060416 A KR 20110060416A KR 1020090116999 A KR1020090116999 A KR 1020090116999A KR 20090116999 A KR20090116999 A KR 20090116999A KR 20110060416 A KR20110060416 A KR 20110060416A
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KR
South Korea
Prior art keywords
pull
power
driving
bit line
voltage
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KR1020090116999A
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Korean (ko)
Inventor
김관언
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주식회사 하이닉스반도체
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Priority to KR1020090116999A priority Critical patent/KR20110060416A/en
Publication of KR20110060416A publication Critical patent/KR20110060416A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Abstract

PURPOSE: A semiconductor memory apparatus is provided to extend the time required for accessing a memory cell by extending a refresh period. CONSTITUTION: In a semiconductor memory apparatus, a bit line sense amp unit(10) senses and amplifies the data of the bit line pair by drive power. The bit line sense amp unit transfers amplified data to a memory cell. A power source generating unit(20) generates a pull-up and a pull-down power source driving signal. The pull-up and pull-down power source driving signal are activated when applying an active command. The pull-up and pull-down power source driving signal are deactivated when applying a precharge command. An over driving power driving signal generation unit generates a pull-up overdriving power source driving signal. A power control unit(40) drives a pull-up driving voltage by a pull-up power line. The power control unit drives a pull-down driving voltage by the pull-down power line. The power control unit drives an overdriving voltage by the pull-up power line.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY APPARATUS}

The present invention relates to a semiconductor memory device and to an overdriving technology.

Among the semiconductor memory devices, DRAM (Dynamic Random Access Memory, DRAM) is a typical volatile memory (Volatile Memory). The memory cell of the DRAM is composed of a cell transistor and a cell capacitor. The cell transistor serves to control access to the cell capacitor, which stores the charge corresponding to the data. That is, the data is divided into high level data or low level data according to the amount of charge stored in the cell capacitor.

On the other hand, since the charge flows into or out of the cell capacitor due to the leakage component of the DRAM, it is necessary to periodically store the corresponding data again. The operation performed periodically to maintain the data accurately is called a refresh operation.

In an active mode, access to a DRAM memory cell is activated, and the bit line sense amplifier circuit senses and amplifies the data transmitted from the memory cell and transfers the data back to the memory cell. In addition, in the precharge mode, access to the memory cell is deactivated and data is maintained. That is, the refresh operation may be described as repeatedly performing the active operation and the precharge operation at regular intervals.

On the other hand, as the operating voltage of the semiconductor memory device is lowered and the cell capacitor capacity is reduced, the operation characteristics and the refresh characteristics of the bit line sensing amplifier circuit are deteriorated.

1 is a view illustrating a voltage change inside according to an operation mode of a semiconductor memory device of the related art.

Referring to FIG. 1, a first diagram 110 illustrating an operation when an active command, a data write command, and a precharge command are sequentially applied, and a first diagram 110 illustrating an operation when the active command and the precharge command are sequentially applied. Two figures 120 are shown.

First, referring to the first drawing 110, when the data write command is applied and the high level write data is transferred, the voltage level of the positive bit line BL increases and the voltage level of the sub bit line BLB decreases. You can see that. At this time, if the time for transmitting the write data is delayed or the activation period of the word line is shortened due to noise or the like, the voltage level of the positive bit line BL may not reach the target value. Therefore, the amount of charge stored in the memory cell is reduced, so that the data holding time is shortened.

Next, referring to the second drawing 120, it can be seen that the voltage level of the positive bit line BL increases and the voltage level of the negative bit line BLB decreases after the active command. At this time, the high level data corresponding to the voltage level of the positive bit line BL is transferred to the memory cell. The positive bit line BL is applied to the cell capacitor due to the load value of the positive bit line BL and the cell transistor. Lower voltage is reached. Therefore, the amount of charge stored in the memory cell is reduced, so that the data holding time is shortened.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor memory device having an improved data retention time of a memory cell.

Another object of the present invention is to provide a semiconductor memory device having an improved time for transferring write data to a memory cell.

According to an aspect of the present invention for achieving the above technical problem, a bit line for sensing and amplifying the data of the pair of bit lines by the driving power supplied through the pull-up power line and pull-down power line to transfer the amplified data to the memory cell Sensing amplifier; A power drive signal generator configured to generate pull-up and pull-down power drive signals that are activated when an active command is applied and are deactivated when a precharge command is applied; An overdriving power driving signal generator configured to generate a pull-up overdriving power driving signal that is activated for a predetermined time in response to the precharge pulse signal; And driving a pull-up driving voltage to the pull-up power line in response to the pull-up power driving signal, driving a pull-down driving voltage to the pull-down power line in response to the pull-down power driving signal, and responding to the pull-up over driving power driving signal. And a power driver driving an overdriving voltage having a voltage level higher than the pull-up driving voltage to the pull-up power line.

In the semiconductor memory device to which the present invention is applied, the time at which a memory cell can reliably hold data, that is, a data retention time is improved.

In addition, since the refresh cycle can be made longer, the time for accessing the memory cell becomes longer, thereby improving the performance of the semiconductor memory device.

In addition, since the time tWR for applying a precharge command after the time of applying the data write command can be shortened, the data writing performance is improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

The semiconductor memory device according to the present embodiment includes only a brief configuration for clearly describing the technical idea to be proposed. For reference, data stored in the semiconductor memory device may be classified into high level (high level) or low level (low level) according to a voltage level, and may be expressed as '1' and '0', respectively. . In this case, data values are differentially classified according to voltage level and current size. In the case of binary data, a high level is defined as a high voltage and a low level is defined as a voltage lower than a high level.

Referring to FIG. 2, the semiconductor memory device includes a bit line detection amplifier 10, a power drive signal generator 20, an over-driving power drive signal generator 30, and a power driver 40.

The bit line detection amplifier 10 is a driving power supplied through the pull-up power line RTO and the pull-down power line SB. To MN10, C). The bit line sense amplifier 10 is a cross couple latch amplifier composed of a plurality of PMOS transistors MP16 and MP17 and a plurality of NMOS transistors MN16 and MN17. Accordingly, the voltage of the bit line pair BL-BLB connected to the differential input / output terminals N11 and N12 is sensed and amplified using the driving power source.

The power drive signal generator 20 generates pull-up and pull-down power drive signals SAP1 and SAN that are activated when an active command is applied and deactivated when a precharge command is applied. The power drive signal generator 20 may be configured to generate a first control pulse signal SASP and a second control pulse signal SASN by inputting an active signal ACT and a precharge signal PCG. 21, the pulse width adjusting unit 22 for inputting the first control pulse signal SASP, and the output signals of the first and second control pulse signals SASP and SASN and the pulse width adjusting unit 22. And a signal combiner 23 for generating pull-up and pull-down power supply drive signals SAP1 and SAN. The pulse width adjusting unit 22 is provided to adjust the pulse width of the pull-up power supply driving signal SAP1. The active signal ACT is a signal generated when the active command is applied, and the precharge signal PCG is a signal generated when the precharge command is applied. For reference, the pull-up and pull-down power supply driving signals SAP1 and SAN are activated after a predetermined time than when the active command is applied, and are deactivated after a predetermined time than when the precharge command is applied.

The overdriving power driving signal generator 30 generates a pull-up overdriving power driving signal SAP0 that is activated for a predetermined time in response to the precharge pulse signal PCG_P. The overdriving power drive signal generator 30 combines a delay unit 31 for delaying the precharge pulse signal PCG_P, a delay unit 31 by combining the signals output from the precharge pulse signal PCG_P and the delay unit 31. And pulse signal output units NAND3 and NAND4 for outputting pulse signals pulsed by the delay value of (31). The precharge pulse signal PCG_P is a signal generated when the precharge command is applied.

The power driver 40 drives the pull-up driving voltage VCORE to the pull-up power line RTO in response to the pull-up power driving signal SAP1 and to the pull-down power line SB in response to the pull-down power driving signal SAN. The pull-down driving voltage VSS is driven, and the over-up driving voltage VDD of a voltage level higher than the pull-up driving voltage VVC is driven to the pull-up power line RTO in response to the pull-up over driving power supply driving signal SAP0. .

The internal operation of each command input of the semiconductor memory device according to the present embodiment is performed as follows.

First, when an active command is applied, the word line WL is activated, and data stored in the memory cells MN10 and C is transferred to the positive bit line BL. Therefore, a voltage difference ΔV occurs between the positive bit line and the negative bit line, and the bit line sense amplifier 10 senses and amplifies the voltage difference ΔV to pull up the bit line pair BL · BLB. It is driven by (VCORE) and pull-down driving voltage (VSS).

Next, since the YI signal is activated when the write command is applied, the data transfer transistors MN14 and MN15 are turned on so that the write data WRITE DATA is transferred to the bit line pair BL-BLB. At this time, the bit line detection amplifier 10 detects and amplifies write data WRITE DATA of the bit line pair BBL to the memory cells MN10 and C. At this time, assuming that the high level write data WRITE DATA is transferred, the bit line sensing amplifier 10 transfers the write data WRITE DATA to the memory cells MN10 and C using the pull-up driving voltage VCORE. do.

Next, when the precharge command is applied, the word line WL is inactivated, and access to the memory cells MN10 and C is blocked. In addition, the pull-up power line RTO and the pull-down power line SB, the positive bit line BL, and the negative bit line BLB are precharged with the precharge voltage VBLP. Meanwhile, the word line WL is deactivated after a predetermined time after the precharge command is applied, and the power driver 40 moves to the pull-up power line RTO until the word line WL is deactivated. ). Accordingly, the bit line detection amplifier 10 drives the positive bit line BL to the overdriving voltage VDD. Therefore, the voltage of the cell capacitor C of the memory cell rises rapidly by the overdriving voltage VDD and stores a lot of charge until the access is blocked. Therefore, it is possible to shorten the time tWR at which the precharge command can be applied after the data write command is applied. In particular, the high-level data takes longer to write than the low-level data. This method reduces the writing time of the high-level data, thereby improving the data writing time. In addition, the time for which the memory cells MN10 and C can hold data is also improved.

For reference, when the precharge command command is applied after the active command to perform the same operation as the refresh operation, the data is transferred to the memory cells MN10 and C using the overdriving voltage VDD. The data holding time of C) is improved.

3 is a diagram illustrating a voltage change in an internal mode according to an operation mode of a semiconductor memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a first drawing 310 and an active command (ACTTIVE CMD) illustrating an operation when an active command (ACTTIVE CMD), a data write command (WRITE CMD), and a precharge command (PRECHARGE CMD) are sequentially applied. ), A second diagram 320 showing an operation when the precharge command PRECHARGE CMD is sequentially applied is shown.

3 and 2, the internal operation of the semiconductor memory device according to the present embodiment will be described.

First, referring to the first drawing 310, when an active command (ACTTIVE CMD) is applied, the word line WL is activated at a high level, and the data stored in the memory cells MN10 and C is transferred to the positive bit line BL. The voltage difference ΔV is generated between the bit line pairs BLBBL. The bit line sense amplifier 10 senses and amplifies the voltage difference ΔV to drive the positive bit line BL to the pull-down driving voltage VSS and to drive the sub bit line BLB to the pull-up driving voltage VCORE. . For reference, the bit line detection amplifier 10 receives a driving power after a predetermined time from a time point at which an active command (ACTTIVE CMD) is applied. That is, the time until sufficient voltage difference (DELTA) V arises between bit line pair BL * BLB is considered. Subsequently, when the data write command WRITE CMD is applied and the high level write data WRITE DATA is transmitted, the voltage level of the positive bit line BL is increased and the voltage level of the negative bit line BLB is decreased. . At this time, the bit line detection amplifier 10 drives the positive bit line BL to the pull-up driving voltage VCORE and drives the sub bit line BLB to the pull-down driving voltage VSS. Subsequently, when the precharge command PRECHARGE CMD is applied, the word line WL is deactivated to a low level after a predetermined time and access to the memory cells MN10 and C is blocked. At this time, after the precharge command PRECHARGE CMD is applied and the predetermined time is received, the bit line detection amplifier 10 receives an overdriving voltage VDD having a voltage level higher than the pull-up driving voltage VCORE and receives the positive bit line ( BL) is pulled up. Therefore, the voltage level of the positive bit line BL rises quickly. Therefore, even when the activation period of the word line is shortened due to noise or the like, the voltage level of the positive bit line BL reaches a target value or more. In addition, since the overdriving voltage VDD is transmitted to the memory cells MN10 and C, the amount of charge stored in the memory cell increases, thereby increasing the data holding time.

Next, referring to the second drawing 320, when the active command ACTTIVE CMD is applied, the word line WL is activated at a high level, and data stored in the memory cells MN10 and C is positive bit line BL. The voltage difference DELTA V occurs between the bit line pairs BLBBL. The bit line sense amplifier 10 senses and amplifies the voltage difference ΔV to drive the positive bit line BL to the pull-up driving voltage VCORE and to drive the sub bit line BLB to the pull-down driving voltage VSS. . For reference, the bit line detection amplifier 10 receives a driving power after a predetermined time from a time point at which an active command (ACTTIVE CMD) is applied. That is, the time until sufficient voltage difference (DELTA) V arises between bit line pair BL * BLB is considered. Subsequently, when the precharge command PRECHARGE CMD is applied, the word line WL is deactivated to a low level after a predetermined time and access to the memory cells MN10 and C is blocked. At this time, after the precharge command PRECHARGE CMD is applied and the predetermined time is received, the bit line detection amplifier 10 receives the overdriving voltage VDD having a voltage level higher than the pull-up driving voltage VCORE to receive the positive bit line BL. ) Will be pulled up. Therefore, the voltage level of the positive bit line BL rises quickly. Therefore, since the overdriving voltage VDD is transmitted to the memory cells MN10 and C, the amount of charge stored in the memory cell increases, thereby increasing the data holding time.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a view illustrating a voltage change inside according to an operation mode of a semiconductor memory device of the related art.

2 is a block diagram illustrating a semiconductor memory device in accordance with an embodiment of the present invention.

3 is a diagram illustrating a voltage change in an internal mode according to an operation mode of a semiconductor memory device according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10: bit line detection amplifier

20: power drive signal generator

30: over-driving power drive signal generator

40: power drive unit

In the figure, PMOS transistors and NMOS transistors are denoted by MPi and MNi (i = 0, 1, 2, ...), respectively.

Claims (4)

A bit line detection amplifier which senses and amplifies data of a pair of bit lines with a driving power supplied through a pull-up power line and a pull-down power line to transfer the amplified data to a memory cell; A power drive signal generator configured to generate pull-up and pull-down power drive signals that are activated when an active command is applied and are deactivated when a precharge command is applied; An overdriving power driving signal generator configured to generate a pull-up overdriving power driving signal that is activated for a predetermined time in response to the precharge pulse signal; And A pull-up driving voltage is driven to the pull-up power line in response to the pull-up power driving signal, a pull-down driving voltage is driven to the pull-down power line in response to the pull-down power driving signal, and in response to the pull-up over driving power driving signal A power driver for driving an overdriving voltage having a voltage level higher than the pull-up driving voltage to the pull-up power line; A semiconductor memory device having a. The method of claim 1, The pull-up and pull-down power supply driving signal, And is activated after a predetermined time from when the active command is applied, and is deactivated after a predetermined time than when the precharge command is applied. The method according to claim 1 or 2, The precharge pulse signal is, And a signal generated when the precharge command is applied. The method of claim 1, The over-driving power drive signal generator, A delay unit for delaying the precharge pulse signal; And And a pulse signal output unit configured to combine the precharge pulse signal and the signal output from the delay unit to output a pulse signal pulsed by the delay value of the delay unit.
KR1020090116999A 2009-11-30 2009-11-30 Semiconductor memory apparatus KR20110060416A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9460766B2 (en) 2014-09-05 2016-10-04 Samsung Electronics Co., Ltd. Memory device, and memory system including the same
CN113053439A (en) * 2019-12-26 2021-06-29 爱思开海力士有限公司 Semiconductor memory device and method of operating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9460766B2 (en) 2014-09-05 2016-10-04 Samsung Electronics Co., Ltd. Memory device, and memory system including the same
CN113053439A (en) * 2019-12-26 2021-06-29 爱思开海力士有限公司 Semiconductor memory device and method of operating the same

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