KR20110051124A - Low noise amplifier - Google Patents

Abstract

PURPOSE: A low noise amplifier is provided to reduce a noise and generation of heat in a state of expanding a bandwidth by forming a negative feedback which a resistance element is removed. CONSTITUTION: A common gate amplifier circuit(120) amplifies a signal of a first node(N1). The command gate amplifier circuit transmits the amplified signal to a second node(N2). The first node receives an AC(Alternating Current) element of an input signal. The common gate amplifier circuit includes an input capacitor(Cin), a bias inductor(Lb), and a first transistor(TR1). A negative feedback amplifier(140) amplifies a signal of a second node. The negative feedback amplifier circuit transmits the amplified signal to a third node(N3). The negative feedback amplifier circuit forms a second node and a third node.

Description

LOW NOISE AMPLIFIER

The present invention relates to a low noise amplifier.

The present invention is derived from a study conducted as part of the IT SoC core design manpower training project of the Ministry of Knowledge Economy. [Task management number: C1200-0901-0002, Task name: IT SoC core design manpower training project]

In general, a low noise amplifier is used to select and amplify only a desired frequency band while minimizing the influence of noise on a weak signal received through an antenna of a wireless device such as a portable TV. In particular, as the portable TV standards of various countries adopt various frequency bands, there is a demand for a low noise amplifier (LNA) that can be commonly used in various bands.

To improve the receiver's receive sensitivity, the noise must be designed as small as possible. Since the noise of the receiver is mostly determined by the low noise amplifier at the front end, it is the most important issue when designing a low noise amplifier to minimize the noise while maintaining proper linearity and gain.

In addition, most terminals must match to 50 Ω, so it is also necessary to select the size of the input CMOS device considering current consumption.

In general, CMOS low-noise amplifiers have an input impedance that is difficult to match inputs, and noise and power matching points are significantly separated from each other, so that the input impedance is designed to optimize these two points using a source inductor.

Since the noise characteristics of the low-noise amplifier dominate the performance of the receiver as a whole, it is common to suppress noise and signal distortion of the low-noise amplifier as much as possible, and use impedance matching between the input and output stages of the amplifier for maximum signal transmission.

An object of the present invention is to provide a low noise amplifier that can reduce noise and heat generation while extending the bandwidth.

The low noise amplifier according to the embodiment of the present invention, a common gate amplifier circuit for amplifying the signal of the input node provided with the AC component of the input signal to the amplification node, and amplifies the signal of the amplification node and delivers it to the output node And a negative feedback amplifying circuit having a feedback capacitor and a feedback inductor connected in series between the amplifying node and the output node to form a negative feedback.

The common gate amplifier circuit may include an input capacitor connected between an input terminal receiving the input signal and the input node, a bias inductor connected between the input node and a ground terminal, and a source connected to the input node. And a first transistor having a drain connected to the amplifying node, and a gate provided with a bias voltage, wherein the amplifying node is supplied with a first power source, and the AC component of the signal of the output node is an output signal.

The negative feedback amplifier circuit may include a second transistor having a source connected to the ground terminal, a drain connected to the output node, and a gate connected to the amplification node, an output capacitor connected between the output node and the output terminal, And a power terminal provided with a second power supply and a load terminal connected to the output node.

In an embodiment, the first and second transistors are MOS transistors.

In an embodiment, the first and second transistors are bipolar junction transistors.

In example embodiments, the first and second transistors are GaAs metal semiconductor field effect transistors.

In an embodiment, the second power source is higher than the first power source.

According to another embodiment of the present invention, a low noise amplifier includes a first transistor having a source connected to an input node, a drain connected to a first amplifying node, and a gate connected to a first bias terminal provided with a first bias voltage, and a ground terminal. A second transistor having a connected source, a drain connected to a second amplifying node, and a gate connected to the first amplifying node, an input capacitor connected between an input terminal receiving an input signal and the input node, and one end of the first amplifying node A feedback capacitor coupled to the first bias inductor coupled between the input node and the ground terminal, a second bias inductor coupled between the amplification node and a second bias terminal provided with a second bias voltage, and the other end of the feedback capacitor. A feedback inductor coupled between the second amplification node, the second amplification node and a third amplification A current reuse circuit connected between the circuit boards and performing amplification at or above the level of the current while reducing the amount of current flowing through the second transistor, and a source follower structure for outputting a signal of the third amplification node. A low noise amplifier comprising a buffer circuit.

The current reuse circuit may include a third transistor having a source connected to a ground node, a drain connected to the third amplification node, and a gate connected to a bias node, and a third transistor connected between the ground node and the ground terminal. A first current reused capacitor, a second current reused capacitor coupled between the ground node and the bias node, a third bias inductor coupled between the bias node and a third bias stage provided with a third bias voltage, and the second And a current reused inductor coupled to the amplifying node and the ground node.

The buffer circuit may include a fourth transistor having a source connected to an output node and a drain connected to the power supply terminal, a first load inductor connected between the third amplification node and a power supply terminal, and the third amplification node. And a second load inductor connected between the gate of the fourth transistor, a bias current source connected to the output node and the ground terminal, and an output capacitor connected between the output node and the output terminal.

The low noise amplifier according to the present invention implements negative feedback with no resistance component, thereby reducing noise and heat generation while extending the bandwidth.

1 is a diagram illustrating a general low noise amplifier.
2 is a view showing a first embodiment of a low noise amplifier according to the present invention.
3 is a view showing a second embodiment of a low noise amplifier according to the present invention.
4 is a diagram illustrating a gain of a low noise amplifier according to an exemplary embodiment of the present invention.
5 is a diagram illustrating noise characteristics of a low noise amplifier according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 shows a typical low noise amplifier 10. Referring to FIG. 1, the low noise amplifier 10 may include capacitors Cin, Cfb, and Cout, first and second MOS transistors M1 and M2, first and second inductors Lfb and Lb, It includes a feedback resistor Rfb and an output load Z.

The first MOS transistor M1 includes a drain connected to the second node N2 and a source connected to the second inductor Lb.

The second MOS transistor M2 includes a drain connected to the third node N3, a source connected to the second node, and a gate provided with a bias voltage Vb.

The first inductor Lfb is connected to the gate of the first node N1 and the first MOS transistor M1. The first inductor Lfb removes the imaginary part of the impedance with an inductance sum of the second inductor Lb connected to the source terminal of the first MOS transistor M1 with respect to the input signal Vin.

The parasitic capacitance Cgs appearing in the first MOS transistor M1 and the transconductance gm appearing in parallel with each other generate a real part of impedance by a combination of inductance components of the second inductor Lb.

The first inductor Lfb, the second inductor Lb, and the first MOS transistor M1 remove the imaginary part of the impedance and generate the impedance of the real part. In this regard, impedance matching is achieved.

Meanwhile, the second MOS transistor M2 provided with the bias voltage Vb at the gate amplifies the input signal Vin. In addition, a negative feedback including a feedback capacitor Cfb and a feedback resistor Rfb is formed at the drain of the second MOS transistor M2 for wideband characteristics.

Here, the feedback capacitor Cfb prevents leakage of the DC bias across the capacitor. In addition, the feedback resistor Rfb determines the amount of negative feedback signal having a value of several hundred ohms to several kiloohms. The general low noise amplifier 10 amplifies and outputs the input signal Vin through impedance matching and negative feedback using a common first inductor Lfb.

The general low noise amplifier 10 includes a feedback resistor Rfb on the path of the signal. However, such resistance components cause noise and heat generation problems. Therefore, in the chip using the general low noise amplifier 10, the performance may be degraded or the overall noise component may be increased.

On the other hand, the low noise amplifier according to the present invention can reduce noise and heat while having a matching effect of a wide frequency band by removing the feedback resistor from the negative feedback.

2 is a view showing a first embodiment of a low noise amplifier 100 according to the present invention. Referring to FIG. 2, the low noise amplifier 100 includes a common gate amplifier circuit 120 and a negative feedback amplifier circuit 140. The negative feedback amplifying circuit 140 of the present invention does not include a resistance component in the negative feedback.

The common gate amplifier circuit 120 amplifies the signal of the first node N1 and transfers the amplified signal to the second node N2. Here, the first node N1 is provided with an alternating current (AC) component of the input signal Vin. Here, the first node N1 is an input node and the second node N2 is an amplification node. The common gate amplifier circuit 120 includes an input capacitor Cin, a bias inductor Lb, and a first transistor TR1. The common gate amplifier circuit 120 is implemented with a common gate.

The input capacitor Cin is connected between the input terminal and the first node N1. The input capacitor Cin receives the input signal Vin. The input capacitor Cin transfers an AC component except for a DC (direct current) component of the input signal Vin to the first node N1.

The bias inductor Lb is connected between the first node N1 and the ground terminal GND. The bias inductor Lb is used for matching the input impedance and prevents the AC component of the input signal Vin from leaking to ground.

The first transistor TR1 includes a source connected to the first node N1, a drain connected to the second node N2, and a gate provided with a bias voltage Vb. Here, the first transistor TR1 may be a metal-oxide-semiconductor field effect transistor (MOSFET), a bipolar junction transistor (BJT), or a GaAs metal semiconductor field effect transistor (MESFET). It may be implemented in any one of these.

The input signal Vin is provided to the source of the first transistor TR1. At this time, the impedance value viewed from the source of the first transistor TR1 is 1 / gm. Here, gm is a transconductance value of the first transistor TR1.

The common gate amplifier circuit 120 provides an input signal Vin through a source, thereby minimizing wideband impedance matching and noise.

The negative feedback amplifying circuit 140 amplifies the signal of the second node N2, transfers the amplified signal to the third node N3, and adds the amplified signal to the second node N2 and the third node N3. To form a feedback. Here, the third node is an output node. Here, the negative feedback does not include the resistance component. The negative feedback amplifier circuit 140 includes a second transistor TR2, an output capacitor Cout feedback capacitor Cfb, a feedback inductor Lfb, and a load terminal 142. In particular, the negative feedback amplification circuit 140 includes a feedback capacitor Cfb and a feedback inductor Lfb connected in series to form a negative feedback.

The second transistor TR2 includes a source connected to the ground terminal GND, a drain connected to the third node N3, and a gate connected to the second node N2. The second transistor TR2 may be implemented as any one of a MOS transistor, a bipolar junction transistor, and a GaAs metal semiconductor field effect transistor. Here, the second node N2 is provided with the first power source VDD1 (for example, 1.0V). In another embodiment, the second node N2 may be provided with the first power source VDD1 via an inductor (not shown).

The output capacitor Cout is connected between the second node N3 and the output terminal and outputs only an AC component excluding a DC component among the signals of the third node N3. The output capacitor Cout prevents leakage of DC components to the output terminal.

The feedback capacitor Cfb and the feedback inductor Lfb are connected in series between the second node N2 and the third node N3 to form a negative feedback. That is, one end of the feedback capacitor Cfb is connected to the second node N2, the other end of the feedback capacitor Cfb is connected to one end of the feedback inductor Lfb, and the other end of the feedback inductor Lfb is connected to the third node. Is connected to N3.

The load stage 142 is connected between the power stage and the third node N3. Here, the power supply terminal is provided with a second power supply VDD2 (for example, 1.8V). The output signal Vout is excited at the load stage 142.

The negative feedback amplifying circuit 140 expands the bandwidth. The negative feedback amplifying circuit 140 improves the stability and widens the bandwidth in the broadband amplifier. In addition, the negative feedback amplifying circuit 140 forms a negative feedback that does not include the resistance component, thereby reducing noise and heat generation while extending the bandwidth.

The general low noise amplifier 10 (see FIG. 1) forms a negative feedback with a feedback resistor Rfb. However, the feedback resistor Rfb causes thermal noise (4kTRfb, T is absolute temperature). On the other hand, the low noise amplifier 100 according to the present invention forms a negative feedback from which the feedback resistor is removed, thereby reducing noise and heat generation while obtaining a wide frequency bandwidth.

The present invention may add current reused technology to improve low power characteristics. Current reuse technology is intended to improve conversion gain while reducing the current consumption of main amplification.

3 is a view showing a second embodiment of a low noise amplifier 200 according to the present invention. Referring to FIG. 3, the low noise amplifier 200 includes a common gate amplifier circuit 220, a negative feedback amplifier circuit 240, a current reuse circuit 260, and a buffer circuit 280.

The common gate amplifier circuit 220 is implemented in the same manner as the common gate amplifier circuit 120 shown in FIG. 2. The common gate amplifier circuit 220 includes an input capacitor Cin, a first bias inductor Lb1, and a first transistor TR1.

The input capacitor Cin is connected between the input terminal and the first node N1. Here, the first node N1 is an input node. The input capacitor Cin receives the input signal Vin. The input capacitor Cin prevents the DC component of the input signal Vin from flowing into the first node N1.

The first bias inductor Lb1 is connected between the first node N1 and the ground terminal GND. The first bias inductor Lb1 is used for input impedance matching and prevents leakage of the AC component of the input signal Vin to ground.

The first transistor TR1 includes a source connected to the first node N1, a drain connected to the second node N2, and a gate connected to the first bias terminal provided with the first bias voltage Vb1. Here, the second node N2 is the first amplifying node. The first transistor TR1 may be implemented as any one of a MOS transistor, a bipolar junction transistor, and a GaAs metal semiconductor field effect transistor.

The input signal Vin is provided to the source of the first transistor TR1. In this case, the impedance value viewed at the source of the first transistor TR1 may be approximated to 1 / gm1. Here, gm1 is a transconductance value of the first transistor TR1.

The common gate amplifier circuit 220 provides the input signal Vin as a source of the first transistor TR1, thereby minimizing wideband impedance matching and noise.

The negative feedback amplifier circuit 240 includes a second transistor TR2, a feedback capacitor Cfb, a feedback inductor Lfb, and a second bias inductor Lb2. In particular, the negative feedback amplifier circuit 240 includes a feedback capacitor Cfb and a feedback inductor Lfb connected in series to form a negative feedback.

The second transistor TR2 includes a source connected to the ground terminal GND, a drain connected to the third node N3, and a gate connected to the second node N2. Here, the third node N3 is a second amplifying node. The second transistor TR2 may be implemented as any one of a MOS transistor, a bipolar junction transistor, and a GaAs metal semiconductor field effect transistor.

The feedback capacitor Cfb and the feedback inductor Lfb are connected in series between the second node N2 and the third node N3 to form a negative feedback.

The second bias inductor Lb2 is connected between the second bias terminal provided with the second bias voltage Vb2 and the second node N2. The second bias inductor Lb2 prevents leakage of the AC component of the signal transmitted to the second node N2 to the second bias stage.

The negative feedback amplifier circuit 220 expands the bandwidth through the negative feedback of the output signal.

The current reused circuit 260 is connected between the third node N3 and the fifth node N5. The current reuse circuit 260 performs amplification similar to or higher than before while reducing current consumption required for main amplification. Here, the fifth node N5 is a third amplification node. The current required for the main amplification is a current flowing through the second transistor TR2 of the negative feedback amplifier circuit 240. That is, the current reused circuit 260 amplifies a level or more similar to the previous level while reducing the amount of current flowing through the second transistor TR2. The current reused circuit 260 includes a third transistor TR3, first and second current reused capacitors Cc1 and Cc2, a current reused inductor Lc, and a third bias inductor Lb3. .

The third transistor TR3 amplifies the signal of the third node N3 to the fifth node N5. The third transistor TR3 includes a source connected to the fourth node N4, a drain connected to the fifth node N5, and a gate connected to the sixth node N6. The fourth node N3 is a ground node, and the sixth node N6 is a bias node. The second transistor TR3 may be implemented as any one of a MOS transistor, a bipolar junction transistor, and a GaAs metal semiconductor field effect transistor.

The first current reused capacitor Cc1 is connected between the fourth node N4 and the ground terminal GND, and the second current reused capacitor Cc2 is connected to the third node N3 and the sixth node N6. The current reused inductor Lc is connected between the third node N3 and the fourth node N4.

The third bias inductor Lb3 is connected between the third bias terminal provided with the third bias voltage Vb3 and the sixth node N6. The third bias inductor Lb3 prevents the AC component of the signal of the sixth node N6 from leaking to the third bias stage.

The current reuse circuit 240 further amplifies the signal of the third node N3 by approximately 1 / gm2. Here, gm2 is a current conductance value of the third transistor TR3.

The buffer circuit 280 is connected between the fifth node N5 and the output terminal and is implemented in a source follower structure. The buffer circuit 280 includes a load terminal 282, a fourth transistor TR4, a bias current source Ib, and an output capacitor Cout.

The load stage 282 includes first and second load inductors Lz1 and Lz2. The first load inductor Lz1 is connected between the power supply terminal VDD and the fifth node N5. The second load inductor Lz2 is connected between the fifth node N5 and the gate of the fourth transistor TR4.

The fourth transistor TR4 includes a source connected to the seventh node N7 and a drain connected to the power supply terminal VDD. Here, the seventh node N7 is an output node. The fourth transistor TR4 may be implemented as any one of a MOS transistor, a bipolar junction transistor, and a GaAs metal semiconductor field effect transistor.

The bias current source Ib is connected between the seventh node N7 and the ground terminal GND.

The output capacitor Cout is connected between the seventh node N7 and the output terminal, and outputs only the AC component from which the DC component is removed among the signals transmitted to the seventh node N7 as the output signal Vout.

The buffer circuit 280 transfers the signal of the fifth node N5 to the seventh node N7 through the source follower as it is.

The low noise amplifier 200 according to the present invention may reduce current consumption while obtaining higher gain through the current reuse circuit 260.

Accordingly, the low noise amplifier 200 of the present invention can reduce noise and heat generation while extending high gain and bandwidth.

4 is a diagram illustrating a gain of a low noise amplifier according to an exemplary embodiment of the present invention. 4, the -3dB bandwidth of the gain is 18-25 GHz, which is the K-band region. Thus, the low noise amplifier of the present invention can obtain high gain and wide bandwidth.

5 is a diagram illustrating noise characteristics of a low noise amplifier according to an exemplary embodiment of the present invention. Referring to FIG. 5, the low noise amplifier has a small noise figure (4-10 dB) overall in the K-band region.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made therein without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

10,100,200; Low noise amplifier
120,220: common gate amplifier circuit
140,240: negative feedback amplifier circuit
142,282: Load end
260: current reused circuit
280: buffer circuit
TR1-TR4: Transistor
Cfb: feedback capacitor
Lfb: Feedback Inductor

Claims (10)

A common gate amplifier circuit for amplifying a signal of an input node provided with an AC component of the input signal and transferring the signal to an amplifying node; And
And a negative feedback amplifying circuit having a feedback capacitor and a feedback inductor connected in series between the amplifying node and the output node to amplify and transfer the signal of the amplifying node to an output node. The method of claim 1,
The common gate amplifier circuit,
An input capacitor connected between an input terminal receiving the input signal and the input node;
A bias inductor coupled between the input node and a ground terminal; And
A first transistor having a source coupled to the input node, a drain coupled to the amplification node, and a gate provided with a bias voltage,
The amplifying node is provided with a first power source,
A low noise amplifier in which the AC component of the signal of the output node becomes an output signal. The method of claim 2,
The negative feedback amplifier circuit,
A second transistor having a source connected to the ground terminal, a drain connected to the output node, and a gate connected to the amplifying node;
An output capacitor coupled between the output node and an output terminal; And
A low noise amplifier comprising a power stage provided with a second power source and a load stage coupled to the output node. The method of claim 3, wherein
And the first and second transistors are MOS transistors. The method of claim 3, wherein
And the first and second transistors are bipolar junction transistors. The method of claim 3, wherein
And the first and second transistors are GaAs metal semiconductor field effect transistors. The method of claim 3, wherein
And the second power supply is higher than the first power supply. A first transistor having a source connected to the input node, a drain connected to the first amplifying node, and a gate connected to the first bias terminal provided with the first bias voltage;
A second transistor having a source connected to a ground terminal, a drain connected to a second amplifying node, and a gate connected to the first amplifying node;
An input capacitor connected between an input terminal receiving an input signal and the input node;
A feedback capacitor, one end of which is connected to the first amplification node;
A first bias inductor coupled between the input node and the ground terminal;
A second bias inductor coupled between the amplifying node and a second bias stage provided with a second bias voltage;
A feedback inductor coupled between the other end of the feedback capacitor and the second amplifying node;
A current reuse circuit connected between the second amplification node and a third amplification node, the current reuse circuit performing amplification at a level equal to or higher than before while reducing the amount of current flowing through the second transistor; And
And a buffer circuit of a source follower structure to output a signal of the third amplifying node. The method of claim 8,
The current reused circuit,
A third transistor having a source coupled to a ground node, a drain coupled to the third amplification node, and a gate coupled to the bias node;
A first current reused capacitor coupled between the ground node and the ground terminal;
A second current reused capacitor coupled between the ground node and the bias node;
A third bias inductor coupled between the bias node and a third bias stage provided with a third bias voltage; And
And a current reused inductor coupled to the second amplification node and the ground node. The method of claim 9,
The buffer circuit includes a fourth transistor having a source connected to an output node and a drain connected to the power supply terminal;
A first load inductor connected between the third amplifying node and a power supply terminal;
A second load inductor coupled between the third amplifying node and the gate of the fourth transistor;
A bias current source coupled to the output node and the ground terminal; And
And an output capacitor coupled between the output node and the output stage.

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