KR20110049692A - Binary content addressable memory - Google Patents

Abstract

PURPOSE: A binary content address memory is provided to occupy small area by reducing the number of a device which is used in a memory. CONSTITUTION: In a binary content address memory, 0 is inputted to a first bit line. 0 is stored in a binary content addressed memory. 1 is inputted to the first bit line. 1 is stored in the binary content addressed memory. 0 is inputted to the first bit line. 1 is inputted to a second bit line. It is determined whether 0 is stored in binary content addressed memory 1 is inputted to the first bit line. 0 is inputted to the second bit line. It is determined whether 1 is stored in binary content addressed memory.

Description

Binary content addressable memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to binary content addressable memory (CAM). More specifically, the size of the content addressable memory is reduced by reducing the total number of transistors constituting the content addressable memory, thereby increasing integration density and power consumption. It is about the content addressable memory that can be improved.

Conventional memory needs to know exactly the address where the data is stored in order to access the stored data. However, a content addressable memory device (CAM) is a memory having a function of finding an address of a location where data of a corresponding content is stored even when the data is inputted even if the exact address where the data is stored is unknown. Therefore, when searching for a specific content in a large amount of data, IP address lookup methods using the content addressing memory are widely used and widely used in the data search engine because of the unique fast search feature that can find the data related to the data matching the given content. have.

Such content addressable memories can be broadly classified into binary content addressable memories (binary CAM) and ternary content addressable memories (ternary CAM). In the binary content addressing memory, 0 or 1 data is stored in a memory cell. The binary content addressing memory compares input data with stored data and searches an address of a location where data of the corresponding content is stored. In contrast, the ternary content addressing memory can store don't care in addition to 0 or 1 in memory cells, and input and input a combination of 0, 1, and amorphous values even when searching stored data. Compare the data with the stored value and search the address of the location where the data of the contents are saved.

1 is a view for explaining an example of retrieving data stored in the binary content addressing memory. FIG. 1A shows data to be searched, and FIG. 1B shows data stored in a binary content addressing memory. As shown in FIG. 1A, the data to be searched is 1, 1, 0, 1, 0, 0, 1. The content addressing memory compares the input data with the stored data, and searches the matching data for the data stored in the third row that matches the input data among the stored data. In this way, since the binary content addressing memory searches the stored data for the data that matches the input data as a whole, it is easy to search the data stored only with the content of the data without knowing the address where the data is stored. Can be.

2 is a schematic circuit diagram illustrating a conventional binary content addressing memory.

Referring to FIG. 2, the conventional binary content addressing memory includes a storage unit 10 for storing data of 0 and 1, and comparison data for inputting data to be stored in the storage unit 10 or determining stored data. A bit line unit including a first bit line BL and a second bit line BL / for input, a word line WL for controlling activation of the storage unit 10, and a bit line unit BL and BL /. And a comparison circuit 20 which compares the comparison data inputted through the stored data stored in the storage unit 10 and determines whether the stored data stored in the content addressing memory and the input comparison data match.

The storage unit 10 is connected to the first NMOS transistor M1 and the second NMOS transistor M2, which are source-connected to the bit line units BL and BL /, in a cyclic ring shape to connect the bit line units BL and BL /. It is provided with a pair of inverters I1 and I2 which store the data input via. Here, the first inverter I1 and the second inverter I2 are each composed of one PMOS transistor and one NMOS transistor.

On the other hand, the comparison circuit unit 20 has a gate connected to each of the matching line ML precharged to a high level by the precharge signal and the pair of inverters I1 and I2, and thus the pair of inverters I1 and I2. A third NMOS transistor M3, a fourth NMOS transistor M4, and a fifth NMOS transistor M5 having drains connected to the matching line ML are provided. The drain of the third NMOS transistor M3 and the source of the fourth NMOS transistor M4 are connected to each other, and are connected to a node A to which the third NMOS transistor M3 and the fourth NMOS transistor M4 are connected. 5 The gate of the NMOS transistor M5 is connected. Here, the source of the fifth NMOS transistor M5 is grounded. When determining the data stored in the storage unit 10, the word line WL is inactivated, and the comparison data inputted through the bit line units BL and BL / and the stored data stored in the storage unit 10 are stored. In case of a match, the matching line ML maintains a precharged state and outputs a high level comparison value. On the other hand, when the comparison data input through the bit line units BL and BL / and the stored data stored in the storage unit 10 are different, the matching line ML is discharged to output a low level comparison value.

In the conventional binary content addressing memory described above, data must be input to the first input line BL and the second input line BL / separately to input data to the storage unit 10. Furthermore, a plurality of transistors in the storage unit 10, that is, two NMOS transistors M1 and M2 connected to the input line units BL and BL / in the storage unit 10, and a pair of interferors I1 and I2. Four transistors (not shown) constituting the (6), a total of six transistors are provided. Therefore, the conventional binary content addressing memory includes six transistors used in the storage unit 10 and three transistors used in the comparison circuit unit 20, a total of nine transistors.

The most important factor to consider in the memory design is to increase the density by making the memory smaller, and also to reduce the power consumption by the high performance design. However, the conventional binary content addressing memory basically uses a total of nine transistors including the comparison circuit unit 20, and the first input line BL and the second input line to store data in the storage unit 10. You must enter each data separately in (BL /). Therefore, the conventional binary content addressable memory has a limitation in integration, and has a problem in that high performance is consumed due to high power consumption and complicated processes by using many transistors, first input lines, and second input lines.

Accordingly, the present invention is to solve the problems of the conventional binary content addressing memory, and an object of the present invention is to provide a binary content addressing memory that occupies a small area by reducing the number of devices used in the binary content addressing memory. It is.

Another object of the present invention is to provide a binary content addressable memory that can improve the degree of integration by reducing the size of the binary content addressable memory.

Another object of the present invention is to provide a binary content addressing memory that can reduce power consumption by reducing the number of transistors constituting the binary content addressing memory.

It is another object of the present invention to provide a binary content addressable memory that can exhibit high performance by reducing the number of constituent transistors and storing data with a single data input to enable data storage or comparison in a small process.

In order to achieve the above-mentioned object, a binary content addressing memory according to the present invention includes a first transistor having a gate connected to a word line WL and controlled to be activated, and a first bit line BL upon activation of the first transistor. Comparison between the second and third transistors storing the stored data input through the second data, the stored data stored in the second transistor and the third transistor, and the first and second bit lines BL and BL / And a comparison circuit section for comparing data and outputting a comparison value.

The comparison circuit unit is activated and controlled according to the match data prestored according to the comparison signal and the comparison data and stored data input through the first and second bit lines BL and BL / after the match line is precharged. And a fourth transistor for outputting a comparison value to the line.

Preferably, in the binary content addressing memory, the first transistor, the third transistor, and the fourth transistor are NMOS transistors, and the second transistor is a PMOS transistor.

The source of the first transistor is connected to the first bit line, the drain of the first transistor is connected to the gates of the second and third transistors, and the gate of the first transistor is connected to the word line.

Here, the source and the drain of the second PMOS transistor are respectively connected to the drain of the first bit line and the third NMOS transistor, the source of the third NMOS transistor is connected to the second bit line, and the drain of the fourth NMOS transistor is The fourth NMOS transistor is connected to the match line and the gate of the fourth NMOS transistor is connected to a connection node between the second PMOS transistor and the third NMOS transistor, and the source of the fourth NMOS transistor is grounded.

The binary content addressing memory according to the present invention has various effects as follows as compared to the conventional binary content addressing memory.

First, the binary content addressing memory according to the present invention has a smaller number of transistors compared to the conventional binary content addressing memory, so that the memory can be manufactured with a small size, thereby improving the integration, which is one of the most important factors in the memory design. .

Second, the binary content addressable memory according to the present invention helps to design a compact and lightweight product by increasing the density.

Third, the binary content addressing memory according to the present invention can reduce power consumption by performing a function of the binary content addressing memory using a small number of transistors.

Fourth, the binary content addressable memory according to the present invention can exhibit high performance by reducing the number of transistors, storing data as single data, and storing or comparing data in a small process.

1 is a view for explaining an example of retrieving data stored in the binary content addressing memory.
2 is a schematic circuit diagram illustrating a conventional binary content addressing memory.
3 shows a circuit diagram of a binary content addressable memory 100 in accordance with one embodiment of the present invention.
4 illustrates a first bit for comparing and searching data input to a first bit line BL and data stored in a binary memory cell in a binary content addressing memory according to an embodiment of the present invention. The data input to the line BL and the second bit line BL / is shown.

Hereinafter, a binary content addressing memory according to the present invention will be described in detail with reference to the accompanying drawings.

3 shows a circuit diagram of a binary content addressable memory 100 in accordance with one embodiment of the present invention.

Referring to FIG. 3, the binary content addressing memory according to the present invention may include a storage unit 110 for storing data of 0 or 1, input data to be stored in the storage unit 110, or input first comparison data. A bit line unit including a first bit line BL for input and a second bit line BL / for inputting second comparison data, a word line WL for controlling activation of the storage unit 110, Comparing circuitry 120 for comparing the data stored in the storage unit 110 and the comparison data to determine the data stored in the binary content addressing memory.

The storage unit 110 includes a first transistor M1, a second transistor M2, and a third transistor M3. The source, drain and gate of the first transistor M1 are connected to the first bit line BL, the gate of the second transistor M2 and the third transistor M3, and the word line WL, respectively. Meanwhile, the source and the drain of the second transistor are connected to the drains of the first bit line BL and the third transistor M3, respectively, and the source of the third transistor M3 is connected to the second bit line BL /. It is connected.

On the other hand, the comparison circuit unit 120 includes a matching line ML and a fourth transistor M4. The drain of the second transistor M2 and the drain of the third transistor M3 are connected to each other, and the gate of the fourth transistor M4 is connected to the drain of the second transistor M2 and the drain of the third transistor M3. It is connected to the connection node (A). The drain of the fourth transistor M4 is connected to the matching line ML, and the source of the fourth transistor M4 is grounded. The comparison circuit unit 120 compares the stored data stored in the storage unit 110 with the comparison data input through the bit line units BL and BL /, and outputs a comparison result as a matching line ML.

Preferably, the first transistor M1, the third transistor M3, and the fourth transistor M4 are NMOS transistors, and the second transistor M2 is a PMOS transistor.

FIG. 4 illustrates a comparison between data input to the first bit line BL and data stored in the binary content addressing memory to store 0 or 1 in the binary content addressing memory according to an embodiment of the present invention. The comparison data input to the one bit line BL and the second bit line BL / is shown.

As shown in Fig. 4A, 0 is input to the first bit line BL to store 0 in the binary content addressing memory, and the first bit is stored in the binary content addressing memory. Enter 1 on the line BL. Meanwhile, as illustrated in FIG. 4B, 0 is input to the first bit line BL and 0 to the second bit line BL / to determine whether the data stored in the binary content addressing memory is 0. 1 is input, and 1 is input to the first bit line BL and 0 is input to the second bit line BL / to determine whether the data stored in the binary content addressing memory is 1.

3 and 4 will be described in more detail the operation of storing the data in the binary content addressing memory and the operation of retrieving the stored data according to the present invention.

<Save operation>

To store 0 in the binary content addressing memory 100, a high signal is input to the word line WL to activate the first transistor M1 and 0 data is input to the first bit line BL. 0 data is stored in the second transistor M2 and the third transistor M3. When the data storage of 0 is completed, the low signal is maintained on the word line WL.

In the same manner, when a 1 is to be stored in the binary content addressing memory 100, a high signal is input to the word line WL to activate the first transistor M1, and data of 1 is input to the first bit line BL. To store the data of 1 in the second transistor M2 and the third transistor M3. When the data storage of 1 is completed, the low signal is maintained on the word line WL.

<Search behavior>

In order to search whether the data stored in the binary content addressing memory 100 is 0, 0 and 1 comparison data are input to the first bit line BL and the second bit line BL /, respectively. When 0 is stored in the binary content addressing memory 100, the second transistor M2, which is a PMOS transistor, is activated, and the third transistor M3, which is an NMOS transistor, is deactivated. Therefore, the comparison data 0 input to the first bit line BL is input to the gate of the fourth transistor M4 along the node A. Since the comparison data input to the gate of the fourth transistor M4 is a signal having a low value, the fourth transistor M4 is inactivated and the matching line ML remains in a precharged state to output a comparison value of the high signal. do. That is, the comparison value of the high signal indicates that the stored data is zero.

However, when 1 is stored in the binary content addressing memory 100, the second transistor M2, which is a PMOS transistor, is inactivated and the third transistor M3, which is an NMOS transistor, is activated. Therefore, the comparison data 1 input to the second bit line BL / is input to the gate of the fourth transistor M4 along the node A. Since the comparison data input to the gate of the fourth transistor M3 is a signal having a high value, the fourth transistor M4 is activated and the matching line ML is discharged to output a comparison value of the low signal. That is, the comparison value of the low signal indicates that the stored data is not zero.

Similarly, in order to search whether the data stored in the binary content addressing memory 100 is 1, comparison data of 1 and 0 is input to the first bit line BL and the second bit line BL /, respectively. When 1 is stored in the binary content addressing memory 100, the second transistor M2, which is a PMOS transistor, is inactivated and the third transistor M3, which is an NMOS transistor, is activated. Therefore, the comparison data 0 input to the second bit line BL / is input to the gate of the fourth transistor M4 along the node A. Since the comparison data input to the gate of the fourth transistor M4 is a signal having a low value, the fourth transistor M4 is inactivated and the matching line ML remains in a precharged state to output a comparison value of the high signal. do. That is, the comparison value of the high signal indicates that the stored data is one.

However, when 0 is stored in the binary content addressing memory 100, the second transistor M2, which is a PMOS transistor, is activated, and the third transistor M3, which is an NMOS transistor, is deactivated. Therefore, the comparison data 1 input to the first bit line BL is input to the gate of the fourth transistor M4 along the node A. Since the comparison data input to the gate of the fourth transistor M4 is a signal having a high value, the fourth transistor M3 is activated and the matching line ML is discharged to output a comparison value of the low signal. That is, the comparison of the low signal indicates that the stored data is not one.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Accordingly, the various embodiments of the present invention described above are only one reference in determining the scope of the present invention, and the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: Binary Content Addressing Memory
110: storage unit
120: comparison circuit

Claims (5)

In binary content addressable memory (CAM),
A first transistor having a gate connected to the word line WL and controlled to be activated;
A second transistor and a third transistor configured to store stored data input through a first bit line BL when the first transistor is activated; And
And a comparison circuit unit configured to compare the stored data stored in the second transistor and the third transistor, and compare data input through the first bit line BL and the second bit line BL / to output a comparison value. A binary content addressable memory. The method of claim 1, wherein the comparison circuit unit
A matchline precharged according to the comparison signal; And
A fourth transistor which is activated and controlled according to the comparison data and the stored data inputted through the first and second bit lines BL and BL / and outputs a comparison value to the match line after the match line is pre-autonomous. Binary content addressing memory comprising a. 2. The system of claim 1, wherein in the binary content addressing memory
The first transistor, the third transistor, and the fourth transistor are NMOS transistors,
And said second transistor is a PMOS transistor. The method of claim 3, wherein
Wherein the source of the first transistor is connected to the first bit line, the drain of the first transistor is connected to the gates of the second and third transistors, and the gate of the first transistor is connected to a word line. Addressing Memory. The method of claim 3, wherein
The source and the drain of the second PMOS transistor are respectively connected to the drain of the first bit line and the third NMOS transistor.
A source of the third NMOS transistor is connected to the second bit line;
The drain of the fourth NMOS transistor is connected to the matchline, the gate of the fourth NMOS transistor is connected to a connection node between the second PMOS transistor and the third NMOS transistor and the source of the fourth NMOS transistor is grounded. Binary content addressable memory.

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