KR20110047841A - Phase locked loop circuit - Google Patents

Phase locked loop circuit Download PDF

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Publication number
KR20110047841A
KR20110047841A KR1020090104623A KR20090104623A KR20110047841A KR 20110047841 A KR20110047841 A KR 20110047841A KR 1020090104623 A KR1020090104623 A KR 1020090104623A KR 20090104623 A KR20090104623 A KR 20090104623A KR 20110047841 A KR20110047841 A KR 20110047841A
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KR
South Korea
Prior art keywords
voltage
phase
capacitor
driving voltage
supply terminal
Prior art date
Application number
KR1020090104623A
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Korean (ko)
Inventor
김명진
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090104623A priority Critical patent/KR20110047841A/en
Publication of KR20110047841A publication Critical patent/KR20110047841A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The present invention relates to a phase locked loop circuit having improved jitter characteristics. The present invention is a phase fixing unit for generating a phase-locked clock by receiving a driving voltage through the driving voltage supply stage; A regulator for providing a predetermined level of voltage to the driving voltage supply terminal of the phase fixing unit using a power supply voltage; A capacitor unit including a capacitor selectively connected to the driving voltage supply terminal; And a voltage detector controlling the capacitor unit so that the capacitor can be selectively connected to the driving voltage supply terminal according to the voltage level of the power supply voltage.

Description

Phase Locked Loop Circuitry {PHASE LOCKED LOOP CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits and, more particularly, to a phase locked loop circuit.

As semiconductor integrated circuits become faster and faster, the frequency of the external clock is increasing, and so is the frequency of the internal clock. Accordingly, in order to improve adaptability to high frequency clocks, semiconductor integrated circuits using a phase locked loop circuit instead of a delay locked loop (DLL) circuit are increasing.

The phase locked loop circuit can be applied to various fields such as wired and wireless communication systems including RF, and is used as a phase adjuster, a frequency synthesizer and a time division system. Typically, a PLL circuit has a phase detector, a charge pump, a loop filter, a voltage controlled oscillator and a clock divider. At this time, the voltage output from the loop filter and input to the voltage controlled oscillator is called a control voltage.

In recent years, jitter of a phase locked clock in a phase locked loop circuit has become a problem for use in semiconductor devices.

Accordingly, an object of the present invention is to provide a phase locked loop circuit having improved jitter characteristics.

According to an aspect of the present invention, there is provided a phase locked loop circuit comprising: a phase fixing part configured to receive a driving voltage through a driving voltage supply terminal to generate a phase locked clock; A regulator for providing a predetermined level of voltage to the driving voltage supply terminal of the phase fixing unit using a power supply voltage; A capacitor unit including a capacitor selectively connected to the driving voltage supply terminal; And a voltage detector controlling the capacitor unit so that the capacitor can be selectively connected to the driving voltage supply terminal according to the voltage level of the power supply voltage.

In addition, the capacitor unit; And a switch MOS transistor for selectively connecting the capacitor to the driving voltage supply terminal. The capacitor may be implemented as an NMOS transistor.

In addition, the switch morph transistor is characterized in that the NMOS transistor.

The phase fixing unit may include a reference frequency generator for generating a reference clock; A phase frequency detector for comparing a phase and a frequency of the reference clock and the oscillated clock; A charge pump for pumping charges according to the comparison information provided by the phase frequency detector; A loop filter for maintaining a voltage corresponding to the amount of charge pumped by the charge pump; And a voltage controlled oscillator for generating a clock corresponding to the voltage held by the loop filter.

The regulator may include an enable signal generator configured to generate an enable signal by comparing a reference voltage and a comparison voltage; A driving voltage supply unit for connecting the power supply voltage to the driving voltage supply terminal in response to the enable signal; And a feedback unit for providing the comparison voltage corresponding to the voltage level of the driving voltage as the enable signal.

The enable signal generation unit may include a differential amplifier.

In addition, the voltage detector is characterized by detecting when the voltage level of the power supply voltage is less than 1.47V or more than 1.53V.

According to the present invention, it is possible to prevent deterioration of the jitter characteristic of the phase locked loop circuit caused by the change in the power supply voltage. In particular, since the phase-locked loop circuit according to the present invention can selectively connect capacitors, the PSRR characteristics can be improved without deteriorating frequency stability and delaying response time.

Hereinafter, an embodiment of an internal voltage generation circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a phase locked loop circuit for explaining the present invention.

Referring to FIG. 1, the phase locked loop circuit includes a reference frequency generator 10, a phase frequency detector 20, a charge pump 30, a loop filter 40, and a voltage controlled oscillator 50.

The reference frequency generator 10 generates a reference clock. The phase frequency detector 20 compares the phase and frequency of the reference clock and the comparison clock generated by the voltage controlled oscillator 50. The charge pump 30 pumps the charge according to the signal provided by the phase frequency detector 20. The loop filter 40 induces a voltage corresponding to the amount of charge pumped by the charge pump 30. The voltage controlled oscillator 50 generates a comparison clock having a frequency corresponding to the voltage induced in the loop filter 40. The reference clock used in the memory device can be used without providing the reference frequency generator 10 of the phase locked loop circuit.

When the clock signal is input from the outside and used immediately inside the memory device to access the data, there are many differences in the load of the line through which various signals are transmitted and the timing of the signal output according to the operation situation inside the memory device. Done.

The phase locked loop circuit receives an external clock to generate an internal clock signal having a fixed phase, and the generated clock signal is used for data access. The state of the clock signal generated by the phase locked loop circuit can be confirmed by measuring jitter of the clock.

As the performance of a memory device is increasingly integrated and speeded up, it is difficult to generate a desired clock due to the jitter characteristic of a conventional phase locked loop circuit. Since other blocks are used together, noise generated inside the memory device degrades the jitter characteristic of the phase locked loop circuit.

The present invention includes a regulator circuit in the phase locked loop circuit in order to overcome the above problems. The regulator can improve the jitter characteristic of the phase-locked loop circuit by providing the noise-free driving voltage to the phase-locked loop circuit. The regulator generates a driving voltage that minimizes the noise of the power supply voltage provided by the memory device. It serves to provide status to the government.

The regulator has characteristics related to response time, frequency stability, and PSRR, among which PSRR is related to noise characteristics. However, the characteristics related to response time, frequency stability, PSRR, etc. are all influenced by the RC characteristics of the regulator circuit and are not characteristics that can be independently improved. If you try to improve the PSRR, there is a trade-off relationship between response time and frequency stability. In this situation, the regulator is modified to improve the jitter characteristics, causing the problem of degrading other characteristics.

In order to improve the PRSS characteristic of the present invention, the output stage resistance or capacitance of the regulator may be increased or the transconductance of the MOS transistor at the input terminal of the phase locked loop circuit to which the driving voltage is applied may be increased. However, increasing the transconductance results in an increase in the regulator's RC constant, resulting in a smaller dominant pole, which causes the regulator itself to peak or near 3 dB of operating frequency. Rash occurs. In this case, the jitter characteristic of the phase-locked loop circuit is not improved, but the stability problem prevents the phase-locked loop PLL from operating normally.

The present invention proposes a method that can simultaneously improve the PSRR characteristics and the frequency stability characteristics of the regulator provided in the phase locked loop circuit.

In the present invention, a target range (for example, A-30mV to A + 30mV) in which the power supply voltage is moved is set using the power supply voltage detector to detect when it is out of the set range and generate an enable signal. In response to the enable signal, the capacitor is temporarily connected to the output of the drive voltage that the regulator provides for phase correction. Therefore, the PSRR characteristic of the regulator is selectively enhanced when the external power supply changes excessively.

2 is a block diagram of a phase locked loop circuit according to a preferred embodiment of the present invention.

As shown in FIG. 2, the phase locked loop circuit according to the present embodiment includes a voltage detector 100, a regulator 200, a capacitor unit 300, and a phase fixing unit 400. The phase fixing unit 400 receives the driving voltage VCORE through the driving voltage supply terminal A to generate a phase locked clock. The regulator 200 is to provide a voltage of a predetermined level to the driving voltage supply terminal A of the phase fixing unit 400 using the power supply voltage VDD. The capacitor unit 300 includes a capacitor that is selectively connected to the driving voltage supply terminal (A). The voltage detector 100 generates a control signal DVDD so that the capacitor can be selectively connected to the driving voltage supply terminal A according to the voltage level of the power supply voltage VDD, and controls the capacitor unit 300.

The phase fixing unit includes a reference frequency generator, a phase frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator provided in the phase locked loop circuit shown in FIG.

FIG. 3 is a circuit diagram of the regulator shown in FIG. 2.

Referring to FIG. 3, the regulator 200 includes an enable signal generator 210 and an enable signal E that generate an enable signal E by comparing a reference voltage VREFC and a comparison voltage VB. In response, the driving voltage supply unit 220 for connecting the power supply voltage VDD to the driving voltage supply terminal A, and the comparison voltage VB corresponding to the voltage level of the driving voltage VCORE of the driving voltage supply unit A. ) Includes a feedback unit 230 for providing the enable signal 210. The enable signal generator 210 includes a differential amplifier.

When the enable signal generator 210 senses the levels of the reference voltage VREFC and the comparison voltage VB and the voltage level of the comparison voltage VB is higher than the reference voltage VREFC, the level of the node D is increased. As a result, the MOS transistor M1 is turned on, and as a result, the MOS transistors M2 and M3 are turned off, so that the voltage of the driving voltage supply unit A drops. If the voltage level of the comparison voltage VB is lower than the reference voltage VREFC, the voltage level of the node D is increased so that the MOS transistor M! Is turned off and the enable signal E becomes a low level. As the MOS transistors M2 and M3 are turned on, the voltage of the driving voltage supply unit A increases. The driving voltage VCORE of a constant level is output while repeating the above operation.

4 is a circuit diagram illustrating a capacitor unit illustrated in FIG. 3.

As shown in FIG. 4, the capacitor unit 300 includes a capacitor C1; And a switch MOS transistor M7 for selectively connecting the capacitor C1 to the driving voltage supply terminal A. FIG. Capacitor C1 is implemented as an NMOS transistor. The morph transistor M7 for the switch is implemented by an NMOS transistor.

As described above, the phase-locked loop circuit according to the present embodiment is characterized in that the regulator circuit can be stably provided with the driving voltage. In addition, the capacitor 300 is provided with a voltage detector 100. The voltage detector 100 senses the level of the power supply voltage VDD and accordingly allows the capacitor C1 of the capacitor unit 300 to be selectively connected to the driving voltage supply unit A. FIG.

By doing so, it is possible to overcome the problem of increasing the frequency stability and response time of the regulator and to improve the PSRR characteristics of the regulator. When the voltage detector senses the level of the power supply voltage VDD and the range of the power supply voltage is out of a predetermined target range, the voltage detector detects this and the capacitor C1 of the capacitor unit 300 may be connected to the driving voltage supply unit A. FIG. Make sure That is, when noise occurs in the power supply voltage, the capacitor C1 of the capacitor unit 300 may be connected to the driving voltage supply unit A. In other cases, the capacitor C1 of the capacitor unit 300 is driven. Do not connect to the voltage supply (A).

Therefore, it is possible to prevent the power supply voltage VDD from being deteriorated due to noise to the jitter characteristic of the phase locked loop circuit. By connecting the capacitor C1 of the capacitor unit 300 to the driving voltage supply unit A when the power supply voltage VDD is noisy, the PSRR characteristic can be prevented from deteriorating, and the power supply voltage VDD has no noise. In this state, the capacitor C1 of the capacitor unit 300 is not connected to the driving voltage supply unit A, thereby preventing the frequency stability from deteriorating and increasing the reaction time.

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and the present invention may be improved by those skilled in the art and further various other embodiments within the technical scope of the present invention disclosed in the appended claims. Changes, substitutions or additions will be possible.

For example, although one capacitor is provided in the capacitor unit, a plurality of capacitors may be provided, and the capacitor unit may be implemented as a switch and a capacitor by using a PMOS transistor instead of the an-mo transistor.

1 is a block diagram of a phase locked loop circuit for explaining the present invention.

2 is a block diagram of a phase locked loop circuit according to a preferred embodiment of the present invention.

3 is a circuit diagram of the regulator shown in FIG.

4 is a circuit diagram illustrating a capacitor unit shown in FIG. 3.

Explanation of symbols on the main parts of the drawings

100: voltage detector 200: regulator

300: capacitor 400: phase fixing

Claims (7)

A phase fixing unit configured to receive a driving voltage through a driving voltage supply terminal to generate a phase locked clock; A regulator for providing a predetermined level of voltage to the driving voltage supply terminal of the phase fixing unit using a power supply voltage; A capacitor unit including a capacitor selectively connected to the driving voltage supply terminal; And A voltage detector controlling the capacitor unit so that the capacitor can be selectively connected to the driving voltage supply terminal according to the voltage level of the power supply voltage; Phase locked loop circuit comprising a. The method of claim 1, Capacitor part Capacitors; And And a shunt transistor for selectively connecting said capacitor to said drive voltage supply terminal. The method of claim 2, The capacitor is a phase-locked loop, characterized in that implemented by the NMOS transistor. The method of claim 3, wherein And said switch MOS transistor is an NMOS transistor. The method of claim 1, The phase fixing part A reference frequency generator for generating a reference clock; A phase frequency detector for comparing a phase and a frequency of the reference clock and the oscillated clock; A charge pump for pumping charges according to the comparison information provided by the phase frequency detector; A loop filter for maintaining a voltage corresponding to the amount of charge pumped by the charge pump; And And a voltage controlled oscillator for generating a clock corresponding to the voltage held by the loop filter. The method of claim 1, The regulator An enable signal generator configured to generate an enable signal by comparing a reference voltage and a comparison voltage; A driving voltage supply unit for connecting the power supply voltage to the driving voltage supply terminal in response to the enable signal; And And a feedback unit for providing the comparison voltage corresponding to the voltage level of the driving voltage as the enable signal. The method of claim 6, And said enable signal generator comprises a differential amplifier.
KR1020090104623A 2009-10-30 2009-10-30 Phase locked loop circuit KR20110047841A (en)

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Application Number Priority Date Filing Date Title
KR1020090104623A KR20110047841A (en) 2009-10-30 2009-10-30 Phase locked loop circuit

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Application Number Priority Date Filing Date Title
KR1020090104623A KR20110047841A (en) 2009-10-30 2009-10-30 Phase locked loop circuit

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KR20110047841A true KR20110047841A (en) 2011-05-09

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