KR20110047837A - Method for manufacturing one side contact in semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a single sidewall contact of a semiconductor device is provided to uniformly form an etching depth on a wafer by using a spacer as a barrier when a sacrificial layer is etched. CONSTITUTION: A plurality of active areas(201) separated by a trench(36) is formed. A recessed sacrificial layer is formed in the trench to form a protrusion on the upper side of the active area. A spacer(41A) is formed on both sides of the protrusion. A spacer is removed from the sidewall by using a photosensitive pattern. One sidewall of the active area is exposed by etching the sacrificial layer using the remaining spacer as a barrier. A sidewall contact is connected to one sidewall of the active area.

Description

METHODS FOR MANUFACTURING ONE SIDE CONTACT IN SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a single sidewall contact of a semiconductor device.

MOSFET devices with horizontal channels have reached physical limits in terms of leakage current, on current, and short channel effects due to the miniaturization of semiconductor devices. ought. In order to solve this problem, transistors using a vertical channel have been actively studied.

Transistors using vertical channels form a round type gate electrode (called a 'vertical gate') that surrounds an active pillar extending vertically on a semiconductor substrate, and is formed around the gate electrode. Thus, the source and drain regions are formed on the upper and lower portions of the active pillar, respectively, so that the channel is formed in the vertical direction.

When forming a cell by using a transistor having a vertical channel, a buried bitline BBL is applied.

Recently, in order to use the buried bit line BBL as a metal film in a semiconductor device having a vertical channel, a one side contact process connected to one side of an active region has been proposed.

1A to 1D illustrate a method of forming a single sidewall contact of a semiconductor device according to the prior art.

As shown in FIG. 1A, after the pad film 12 is formed on the semiconductor substrate 11, the hard mask film 13 is formed on the pad film 12. The hard mask layer 13 and the pad layer 12 are etched by using a photoresist pattern (not shown) patterned in a line-space type. The photoresist pattern is removed through the photoresist strip process.

Next, the trench 16 is formed by etching the semiconductor substrate 11 at a predetermined depth using the hard mask layer 13 as an etch barrier. A plurality of active regions 101 separated from each other by the trench 16 are formed.

Subsequently, a sidewall oxide layer 17 is formed on the surface of the active region 101 and the semiconductor substrate 11A through a wall oxidation process.

Subsequently, a liner nitride film 18 is deposited on the entire surface of the structure in which the sidewall oxide film 17 is formed.

Subsequently, a sacrificial layer 19 is formed on the liner nitride layer 18 so as to gap fill the trench 16 between the active regions 101.

Subsequently, the sacrificial film 19 is planarized by the chemical mechanical polishing (CMP) method until the surface of the hard mask film 13 is exposed, followed by further etch back to recess the predetermined height.

As shown in FIG. 1B, an etch barrier 20 is formed on the entire surface of the hard mask layer 13 to cover the protrusion of the hard mask layer 13.

As shown in FIG. 1C, a dopant such as Boron or the like is implanted at a predetermined angle to implant a dopant such as Boron. Accordingly, a dopant is injected into a portion of the etch barrier film 20.

Thus, part 20A of the etch barrier is doped but the remainder 20B remains undoped. The doped portion of the etch barrier is cured. Hereinafter, the doped portion is referred to as a hardened etch barrier film 20A, and the undoped portion is referred to as an uncured etch barrier film 20B.

As shown in FIG. 1D, the uncured etch barrier film 20B is removed through wet etching.

Accordingly, the cured etch barrier film 20A remains, and the cured etch barrier film 20A covers a part of the sacrificial film 19 while covering the left sidewall and the top surface of the hard mask film 13. .

Subsequently, the sacrificial film 19 adjacent to one sidewall of the active region 101 is partially etched through the etch back using the remaining hardened etch barrier film 20A as a barrier. At this time, the etching depth of the sacrificial film 19A is adjusted to the position where the single sidewall contact is to be formed.

When the sacrificial layer is etched as described above, the sacrificial layer 19A that provides the sidewall trench 21 for opening only one sidewall of the neighboring active region 101 remains.

However, there are some problems in the method of forming the hardened etching barrier film by tilt ion implantation.

First, the degree of hardening depends on the uniformity of doping and the thickness uniformity of the etch barrier, and the open ratio of the etch barrier is changed. The depth of 21 will be different.

In the case of tilt ion implantation, there is a difficulty in uniformly doping the entire wafer in order to form a uniform film and a difficulty in controlling the thickness and shape of the etch barrier film uniformly.

Second, it is difficult to remove the doped etch barrier and it is impossible to predict how impurities such as boron will affect the device characteristics.

Materials such as boron are very small in atomic weight and can easily diffuse into the atomic lattice when a certain energy is applied.

Due to this problem, there is a need for a method of forming one side contact without using tilt ion implantation.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems in the prior art, and provides a method for forming a single sidewall contact of a semiconductor device capable of forming a sidewall trench for a single sidewall contact at a desired position and uniform depth.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of active regions separated by a trench; Forming a sacrificial layer recessed in the trench to form a protrusion on the active region; Forming spacers on both side walls of the protrusion; Removing spacers on one sidewall of the spacers using a photoresist pattern; Etching the sacrificial layer with the remaining spacer as a barrier to expose one sidewall of the active region; And forming a sidewall contact connected to one sidewall of the active region.

According to the present invention, by using a spacer as a barrier when forming a sacrificial layer for forming a single sidewall contact, the etching depth can be made uniform throughout the wafer, and thus, a semiconductor device having a uniform characteristic can be obtained.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

2A to 2R are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, a pad film 32 is formed on the semiconductor substrate 31. Here, the pad film may include an oxide film.

A hard mask film is formed on the pad film 32. Here, the hard mask film may have a multilayer structure including an oxide film and a nitride film. For example, the hard mask nitride layer 33 may be stacked in the order of the hard mask nitride layer 33 and the hard mask oxide layer 34. In addition, a hard mask silicon oxynitride layer (HM SiON) and a hard mask carbon layer (HM Carbon) may be further stacked on the hard mask oxide layer 34.

The first photoresist layer pattern 35 is formed on the hard mask oxide layer 34. The first photoresist pattern 35 is patterned in a line-space type and is also referred to as a BBL mask (Buried BitLine Mask).

After etching the multi-layered hard mask film using the first photoresist film pattern 35 as an etch barrier, the pad film 32 is etched. Here, since the shape of the first photoresist layer pattern 35 is transferred when the hard mask layer is etched, it is patterned in a line-space form.

As shown in FIG. 2B, the first photoresist layer pattern 35 is removed through the photoresist strip process.

Next, trench etching is performed using the multilayer hard mask layer as an etch barrier. That is, the trench 36 is formed by etching the semiconductor substrate 31 by a predetermined depth using the hard mask oxide layer 34 as an etch barrier. A plurality of active regions 201 are formed which are separated from each other by the trench 36.

This trench etching process is abbreviated as 'BBL (Buried BitLine) trench etching'. The hard mask layer remaining after the BBL trench etching includes a hard mask nitride layer 33 and a hard mask oxide layer 34.

The active region 201 is also patterned in a line-space form because the first photoresist pattern is formed by the transferred hard mask oxide film 34. Accordingly, the active region 201 is in the form of a line, and neighboring active regions are separated by the trench 36 in the form of a line.

BBL trench etching uses anisotropic etching. In the case where the semiconductor substrate 31 is a silicon substrate, anisotropic etching proceeds by mixing chlorine gas such as Cl ₂ , CCl ₂ , bromide gas such as HBr, and oxygen (O ₂ ) gas.

By the above-described BBL trench etching process, a plurality of active regions 201 separated from each other by the trench 36 and extending in the first direction are formed on the semiconductor substrate 31A.

As shown in FIG. 2C, a sidewall oxide layer 37 is formed on the surface of the active region 201 and the semiconductor substrate 31A through a wall oxidation process. The sidewall oxidation process for forming the sidewall oxide film 37 proceeds at a temperature of 700 to 900 占 폚 in an O ₂ or O ₂ / H ₂ atmosphere. Meanwhile, in addition to the method of forming the sidewall oxide film 37 by the sidewall oxidation process, a sidewall of the active region 201 may be protected by depositing a liner oxide on the entire surface.

Subsequently, a first liner nitride layer 38 is deposited on the entire surface of the structure in which the sidewall oxide layer 37 is formed. The first liner nitride film 38 may be formed at a temperature of 600 to 800 ° C. and a pressure of 0.1 to 6 Torr in an atmosphere of DCS (Dichlorosilane) and NH ₃ .

Subsequently, a first sacrificial film 39 is formed on the first liner nitride film 38 so as to gap fill the trench 36 between the active regions 201. Here, the first sacrificial layer 39 may be a material removed after the subsequent process is performed, and may include, for example, a polysilicon layer. Preferably, it may include an undoped polysilicon film.

As shown in FIG. 2D, the first sacrificial film is planarized by CMP (Chmiecal Mechanical Polishing) method until the surface of the hard mask nitride film 33 is exposed, and then further etched back to recess a predetermined height. In this case, the height of the recessed first sacrificial layer 39A may be higher than the contact surface between the pad layer 32 and the active region 201. The recess amount of the first sacrificial film 39A may be in the range of 100 to 300 kPa. The etch back process of the first sacrificial film 39A proceeds by mixing chlorine gas such as Cl ₂ , CCl ₂ , bromide gas such as HBr, and oxygen (O ₂ ) gas.

As described above, when the first sacrificial film 39A is formed to the etch back, the hard mask nitride film 33 protrudes in the form of a protrusion. The hard mask oxide film 34 is removed during the CMP process, and the first liner nitride film on the upper surface and sidewalls of the hard mask oxide film is also polished. Accordingly, the remaining first liner nitride film 38A has a height covering the sidewall of the hard mask nitride film 33.

As shown in FIG. 2E, an etch stop layer 40 is formed on the entire surface of the hard mask nitride layer 33 to cover the protrusion of the hard mask nitride layer 33. Here, the etch stop layer 40 may include a nitride layer. The etch stop layer 40 serves to prevent attack of the first sacrificial layer during the subsequent spacer etching process.

Subsequently, a spacer film 41 is formed on the etch stop film 40. Here, the spacer film 41 may include an oxide film and is formed to have a thickness of 50 to 300 kHz. The thickness of the spacer film 41 is adjusted in consideration of the overlay margin of the subsequent photo process.

As shown in Fig. 2F, spacer etching, that is, etch back, is performed to form the spacers 41A and 41B. The spacers 41A and 41B have a form covering both sidewalls of the protrusions of the hard mask nitride film 33. For convenience of description, the first spacer 41A covering the left sidewall of the protrusion and the second spacer 41B covering the right sidewall will be divided.

As shown in FIG. 2G, a second photosensitive film pattern 42 is formed. Before forming the second photoresist pattern 42, an anti-reflection film may be formed in advance to facilitate the photo process.

The second photoresist pattern 42 is formed to cover either spacer. For example, the first spacer 41A is covered and the second spacer 41B is exposed.

As shown in FIG. 2H, the exposed second spacer is removed using the second photoresist pattern 42 as a barrier. When removing the second spacer, the etch stop layer 40 prevents the attack of the first sacrificial layer 39A. The process of removing the second spacer is performed using the etch stop film 40 and a gas having a selectivity. For example, when the etch stop film 40 is a nitride film and the second spacer is an oxide film, a mixture of a florin-based gas, a helium (He) gas, an oxygen (O ₂ ) gas, and an argon (Ar) gas is mixed. Use gas. The florin-based gas may include a C _x H _y F _z gas such as CHF ₃ and a C _x F _y gas such as C ₄ F ₈ .

As shown in FIG. 2I, the photosensitive film strip process and the cleaning process are sequentially performed to remove the second photosensitive film pattern 42. When the anti-reflection film is formed, the anti-reflection film is removed along with the second photoresist pattern during the strip process.

As a result, the first spacer 41A remains on only one sidewall of the protrusion of the hard mask nitride film 33. An etch stop film 40 remains between the first spacer 41A and the hard mask nitride film 33.

As shown in FIG. 2J, the first sacrificial film 39A is partially etched through the etch back using the first spacer 41A as a barrier. At this time, the etching depth of the first sacrificial film 39A is adjusted to a position where a subsequent sidewall contact is to be formed, and the etching of the first sacrificial film 39A is self-aligned and etched in the first spacer 41A. The partial etching process of the first sacrificial film 39A is performed by mixing a chlorine gas such as Cl ₂ , CCl ₂ , a bromide gas such as HBr, and an oxygen (O ₂ ) gas.

As described above, when the first sacrificial layer is etched, only the first sacrificial layer 39B that provides the sidewall trench 39C exposing one sidewall of each active region 201 remains.

In addition, the uniformity of the etching depth is excellent by self-aligned etching to expose one sidewall of the active region 201 using the first spacer 41A. Thus, the formation position of the subsequent single sidewall contact is uniform.

In the above-described embodiment, the etch barrier film for etching the first sacrificial film is not formed through the curing process by tilt ion implantation, but the first spacer 41A is formed through the deposition of the spacer film and the spacer etching. As such, since the spacer film for the first spacer 41A is formed by vapor deposition, the thickness uniformity is high. Accordingly, when the first sacrificial film 39A is etched using the first spacer 41A, the etching depth is uniform throughout the wafer. As a result, a semiconductor device with uniform characteristics can be obtained.

As shown in FIG. 2K, after removing the first spacer 41A, the first liner nitride film is removed through a cleaning process. As a result, the first liner nitride film exposed by the first sacrificial film 39B is removed. Accordingly, the remaining first liner nitride film 38B remains only in contact with the first sacrificial film 39B. When the first liner nitride film is removed to leave the sidewall oxide film 37 on the sidewall of the active region 201, wet cleaning may be applied or dry cleaning having a selectivity with respect to the oxide film may be applied.

As shown in FIG. 2L, after the first sacrificial film is removed, the second sacrificial film 43 is gap-filled on the entire surface. Here, the second sacrificial layer 43 may include an undoped polysilicon layer.

As shown in FIG. 2M, the second sacrificial film 43 is planarized until the surface of the hard mask nitride film 33 is exposed using a method such as CMP, and subsequently etched back so that a certain height remains. As a result, the second sacrificial film 43A remains with a certain height, and in particular, the remaining height of the second sacrificial film 43A becomes a height defining a space in which subsequent sidewall contacts are to be formed. That is, when the second sacrificial film is etched back, both sidewall portions of the hard mask nitride film 33 and the active region 201 are exposed. Of course, the sidewall oxide film 37 still remains on the sidewall of the active region 201.

As shown in FIG. 2N, the second liner nitride film 44 is formed on the entire surface, and then selectively etched to expose the surface of the second sacrificial film 43A. Accordingly, a double insulating film structure of the sidewall oxide film 37 and the second liner nitride film 44 is formed on the sidewall of the active region 201. In the region where the second sacrificial film 43A is located, only the sidewall oxide film 37 exists between the active region 201 and the second sacrificial film 43A. On the sidewall of the hard mask nitride film 33, a single insulating film structure of the second liner nitride film 44 is formed. The second liner nitride film 44 is formed at a temperature of 600 to 800 ° C. and a pressure of 0.1 to 6 Torr in an atmosphere of DCS (Dichlorosilane) and NH ₃ .

As shown in FIG. 2O, the second sacrificial film is removed. Accordingly, a line type opening 45 is opened to a part of one side of the active region 201.

Here, the opening 45 is a space in which the second sacrificial film between the first liner nitride film 38B and the second liner nitride film 44 is removed.

As shown in Fig. 2P, the sidewall oxide film 37 exposed by the opening is selectively removed. Accordingly, a contact region 45A exposing a portion of one sidewall of the active region 201 in a line form is formed. The sidewall oxide film may be removed by cleaning to form the contact region 45A. For example, wet cleaning using HF, BOE, etc. may selectively remove the sidewall oxide layer without damaging the surrounding liner nitride layers. After the contact region 45A is formed, the sidewall oxide film 37A exposes one side wall of the active region 201.

As shown in FIG. 2Q, the sidewall contact 202 is buried in the contact region 45A. Here, the single sidewall contact 202 may comprise a metal silicide. For example, the metal silicide includes titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ), nickel silicide (NiSi), and the like. It is preferable to select cobalt silicide (CoSi ₂ ) with stronger thermal stability in order to prevent deterioration by subsequent high temperature thermal processes.

As described above, the sidewall contact 202 is a single side contact structure formed only at one sidewall of the active region 201. The sidewall contact 202 may include an metal silicide to form an ohmic contact.

As shown in FIG. 2R, a bit line conductive film is deposited on the entire surface of the structure in which the sidewall contacts 202 are formed. At this time, the bit line conductive film is deposited on the entire surface to gap fill the trench between the active regions 201. The bit line conductive film includes a metal film such as a titanium nitride film (TiN) or a tungsten film (W). For example, the bit line conductive film may be formed by stacking a titanium nitride film and a tungsten film (TiN / W).

Next, the bit line conductive film is removed to a height in contact with the sidewall contact 202. As a result, a metal bit line 203 is formed in contact with the sidewall contact 202. Here, the metal bit line 203 is arranged side by side with the active region 201, and the active region 201 and the metal bit line 203 are electrically connected through the sidewall contact 202. It is assumed that the active region 201 and the metal bit line 203 extend in the first direction.

As described above, since the metal bit line 203 is formed of a metal film, the resistance is low, and since the metal bit line 203 is formed to partially fill the inside of the trench 36 between the active regions 201, it becomes a buried bit line. In addition, the present invention does not require a trench process for separating the metal bit line 103.

In the above-described embodiment, the uniformity of the etching depth is excellent by self-aligned etching so as to expose one sidewall of the active region 201 using the first spacer 41A. Accordingly, the formation position of the subsequent contact region is more uniform than that of the first embodiment.

Since the buried bit line is formed of a metal film, it is possible to realize a device without deteriorating operation characteristics even if the semiconductor device is miniaturized by lowering the resistance.

In addition, the present invention may form an ohmic-like contact by applying one side contact in the contact region where the buried bit line formed of the metal film and the active region contact each other.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1D illustrate a method of forming a single sidewall contact of a semiconductor device according to the prior art.

2A to 2R are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31A: semiconductor substrate 32: pad film

33: hard mask nitride film 36: trench

37: sidewall oxide film 38, 38A, 38B: first liner nitride film

39, 39A, 39B: first sacrificial membrane 40: etching barrier

41A, 41B: spacer 42: second photosensitive film pattern

44: second liner nitride film 45A: contact region

101: active area 102: sidewall contact

103: metal bit line

Claims (8)

Forming a plurality of active regions separated by trenches; Forming a sacrificial layer recessed in the trench to form a protrusion on the active region; Forming spacers on both side walls of the protrusion; Removing spacers on one sidewall of the spacers using a photoresist pattern; Etching the sacrificial layer with the remaining spacer as a barrier to expose one sidewall of the active region; And Forming a sidewall contact connected to one sidewall of the active region A semiconductor device manufacturing method comprising a. The method of claim 1, And the spacer comprises an oxide film. The method of claim 1, Before forming the spacer, And forming an etch stop layer on the entire surface of the recessed sacrificial layer. The method of claim 3, Forming the spacers, Forming a spacer film used as the spacer on the etch stop film; And Etching the spacer layer entirely using the gas having a selectivity with the etch stop layer A semiconductor device manufacturing method comprising a. The method of claim 4, wherein The etch stop film includes a nitride film and the spacer film comprises an oxide film. The method of claim 5, The front etching is, A method of manufacturing a semiconductor device, comprising a gas obtained by mixing a florin series gas, helium gas, oxygen gas, and argon gas. The method of claim 1, The trench is formed by etching a semiconductor substrate using a hard mask film. The method of claim 1, The sacrificial film includes a undoped polysilicon film.

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