KR20110036631A - Method and apparatus for receiver with dual mode automatic gain control (agc) - Google Patents

Abstract

Comparing the gain state of the receiver to at least one gain state threshold; Determining the presence of jammers; And switching the current mode of the receiver to a new mode based on a comparison of the presence and gain states of the jammers, and a method and apparatus for toggling between the first and second modes of the receiver based on the input signal level. . In one aspect, the apparatus includes two LNAs operating in different modes; A jammer detector providing a jammer interrupt bit indicative of the presence of a jammer; And an automatic gain control (AGC) circuit coupled to the jammer detector to receive the jammer interrupt bit, wherein the AGC circuit selects between the two LNAs based on the jammer interrupt bit and the gain state comparison.

Description

METHOD AND APPARATUS FOR RECEIVER WITH DUAL MODE AUTOMATIC GAIN CONTROL (AGC)}

Claims of Priority under 35 U.S.C. §119

This patent application is filed on July 31, 2008 and is assigned to the assignee of this patent application and is hereby expressly incorporated by reference, entitled "Method And Apparatus For Receiver With Dual Mode Automatic Gain Control (AGC)". US Provisional Application No. 61 / 085,321.

The present disclosure generally relates to apparatus and methods for a communication receiver. More specifically, the present disclosure relates to a dual mode AGC receiver with automatic gain control.

In conventional communication receivers, there are two conflicting requirements: high sensitivity and high linearity. High sensitivity refers to receiver characteristics of low noise figure with high gain such that the receiver is sensitive to weak signals. Low noise figure LNA provides the receiver with better sensitivity and better SNR for weak signals. However, low noise figure LNAs with high gains fail to provide adequate SNR in the presence of strong interference (e.g. jammers) because of the increased intermodulation level. The intermodulation level increase is due to the low third order intercept point (IP3) and low P1dB (1dB compression point) for the high sensitivity receiver. Another effect is the low second order intercept point (IP2), which exhibits and affects IF noise in ZIF (zero IF) and VLF (very low IF) receivers as well as in superheterodyne receivers. An example of the cause of this phenomenon may be a mixer.

High linearity refers to receiver characteristics of high IP3 and high P1dB. High linear receivers have improved immunity to strong signals and to strong interference (eg jammers). That is, high linear receivers have less distortion (eg, intermodulation product level, gain compression, phase nonlinearity, AM-PM conversion, etc.) than high sensitivity receivers when there is strong signal or strong interference. However, a high linear receiver (eg its LNA) has a higher noise figure and lower gain and therefore cannot provide optimal sensitivity and SNR when there is a weak jammer or no jammer at all.

There is a system design tradeoff between receiver design for weak signals versus receiver design for strong signals. Therefore, high sensitivity receivers are optimal for weak signals and high linear receivers are optimal for strong signals.

However, in many cases there is a combination of a weak desired signal and a strong undesired jammer appearing at the receiver input. In one example, a weak desired signal and a strong undesired jammer are received at the same time. In this case, the high sensitivity receiver may degrade signal-to-noise ratio (SNR) performance due to gain compression and intermodulation distortion due to the presence of strong jammers at the receiver input. On the other hand, high linearity receivers may also degrade SNR performance due to higher noise-values resulting in higher noise levels and reduced sensitivity to weak desired signals. Therefore, either of the receiver designs (high sensitivity or high linearity) is a compromise, the choice of noise figure, IP3 and P1dB performance.

Disclosed is a method and apparatus for providing a dual-mode AGC receiver design capable of toggling between a high sensitivity low noise amplifier (LNA) and a high linearity LNA depending on the input signal environment. In one aspect, the dual mode AGC receiver includes jammer sensing.

Other aspects will be readily apparent to those skilled in the art from the following detailed description, shown and described in various aspects by the method of description. The drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.

1A shows an exemplary overview of an ultra wideband dual mode AGC receiver system for multi-radio system management.
Figure 1b shows a jammer-free carrier-to-noise (C / N) compared to the characteristic of jammer-carrier-to-noise plus third-order intermodulation level (C / (N + IM)) for a conventional receiver. The characteristic is shown.
2 shows an example for optimizing SNR (eg, C / N) by combining high linearity characteristics and high sensitivity characteristics at the receiver.
3 shows an example of a dual mode AGC receiver front-end.
4 shows an example of a state transition diagram for dual mode in terms of switch point (SP) and gain states.
5A shows an example of the resulting dual mode AGC receiver gain state as a function of input RF level for both high sensitivity mode (mode 1) and high linear mode (mode 2).
5B shows an example of the resulting dual mode AGC receiver noise figure state as a function of input RF level for both high sensitivity mode (mode 1) and high linear mode (mode 2).
6 shows an example of an operation mode and state diagram.
7 shows an example of voltage requirements at the ADC input for different gain states for a receiver with AGC, which may or may not be dual mode.
8 shows an example of carrier to noise ratio (C / N) with increased intermodulation product level for different gain states.
9 shows an example of a dual mode AGC receiver.
9A, 9B and 9C show three other examples of a dual mode AGC receiver.
10A shows an example of a block diagram of a jammer detector JD coupled to an automatic gain control (AGC) circuit.
10B shows an example of an ultra wideband dual AGC receiver block diagram.
FIG. 11 shows an example with frequency as the ratio between RF noise to ADC noise at the analog output of a mixer / low pass filter (LPF).
12 shows an example flow diagram for toggling between dual modes based on an input signal environment.
13 shows an example of a device 1300 suitable for toggling between dual modes based on an input signal environment.

The detailed description set forth below in connection with the appended drawings is intended as a description of various aspects of the present disclosure and is not intended to represent the only aspects in which the present disclosure may be practiced. Each aspect described in this disclosure is provided merely as an example or description of the disclosure and should not necessarily be construed as preferred or advantageous over other aspects. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the present disclosure. Acronyms and other technical terms may be used for convenience and clarity only and are not intended to limit the scope of the present disclosure.

While methodologies are shown and described as a series of acts for the purpose of simplicity of description, some acts may occur concurrently with a different order and / or other act than that shown and described herein with respect to one or more aspects. As such, methodologies are not limited by the order of action. For example, those skilled in the art will understand that the methodology may alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all urban acts may be required to implement a methodology involving one or more aspects.

1A shows an exemplary overview of an ultra wideband dual mode AGC receiver system for multi-radio system management. The system includes, for example, a hardware jammer detector for detecting near and far jammers, a coexistence management subsystem, and a dual mode AGC receiver. The dual mode AGC receiver includes a first mode for providing high sensitivity and a second mode for providing high linearity. For the case of low jammers, the receiver operates in the first mode to provide high linearity but high sensitivity. In the case of high jammers above the threshold, the AGC receiver is switched to the second mode to provide medium sensitivity but high linearity.

Figure 1b shows the jammer-free carrier-to-noise (C / N) characteristics of the conventional receiver plus the jammer-carrier-to-noise and third-order intermodulation levels (C / (N + IM)) for a conventional receiver. Shown in comparison with the characteristics of the. This conventional receiver design is based on a compromise between having high linearity characteristics and high sensitivity characteristics. Ideally, the conventional receiver of FIG. 1B should operate and receive a weak signal with minimal degradation in the presence of jammers. One technique for optimizing the performance of a conventional receiver is to create two extremes of the curve, less than any value, for example 3 dB shown in FIG. However, this optimization process is a balance between noise figure (NF) and input third order intercept point (IIP3), where IIP3 yields P1dB, which also affects the level of intermodulation products and, for example, IP3 or higher order IP. define. The optimization process results in a high linearity receiver. Penalties when using a high linearity receiver are degraded noise figure (eg higher noise figure value) and degraded LNA gain for higher IIP3. And the sensitivity is sacrificed due to the reduced SNR by attempting to "balance" the conventional receiver.

Using a high sensitivity receiver (eg, a high sensitivity LNA) over a wide dynamic range with weak or no jammer results in improved sensitivity compared to using a high linearity receiver. However, when strong jammers are present, the SNR (eg, C / N) degrades due to gain compression and intermodulation distortion.

2 shows an example for optimizing SNR (eg, C / N) in a jammer environment by combining high linearity characteristics and high sensitivity characteristics in a single dual-mode AGC receiver. By combining two characteristics of high linearity and high sensitivity for different input signal environments in a single dual-mode AGC receiver, the optimization of SNR (eg, C / N) is made as shown in FIG. For example, when a weak jammer is present or when no jammer is present, the dual mode AGC receiver operates with high linearity LNA characteristics and even with high input desired signal levels. On the other hand, when there is a strong jammer, the dual mode AGC receiver operates with a high linearity LNA feature to optimize the SNR (eg, C / N replaced by C / (N + I)).

3 shows an example of a dual mode AGC receiver front-end. In one example, an automatic gain control (AGC) signal from an AGC circuit (not shown) is applied to the dual mode AGC receiver front-end shown in FIG. The AGC circuitry increases the dynamic range of the dual-mode AGC receiver and limits the receiver output power at levels not greater than the maximum allowed at the analog-to-digital converter (ADC) input. The AGC acts as a power or voltage limiter at the dual mode AGC receiver output, which limits the desired signal level at the ADC input. In one aspect, the margin for component tolerance and power leakage of unwanted signals is included in the AGC circuit. In a jammer-free environment, the AGC circuit is optimized for the receiver to meet linearity and sensitivity requirements.

In one example, a jammer detector is included within the dual mode AGC receiver to identify undesired signals and to trigger a switch between the dual mode—high linearity mode and high sensitivity mode. For example, the dual mode is: 1) high sensitivity mode for low power signals and no weak jammer or jammer and 2) high linearity mode with moderate sensitivity to strong jammer (shown in dash line). 3 shows some example gain state values for dual mode. For example, the high sensitivity mode includes a gain state G0 at 20 dB with a noise figure of 1.4 dB. The high linearity mode has five gain states, for example, at G1 at 14.5 dB (with NF of 1.7 dB), G2 at 9.5 dB, G3 at 3 dB, G4 at -8.5 dB and -22 dB. Includes G5. In one aspect, a dual mode AGC receiver (eg, dual mode LNA) is implemented in a parallel path. In another aspect, a dual mode AGC receiver (eg, dual mode LNA) is implemented in a single path.

In one example, two AGC tables are included in a process in a dual mode AGC receiver. The first AGC table is used for the high sensitivity mode where low noise figure LNA is used. The second AGC table is used for the high linearity mode in which a high IP3 LNA is used. The two AGC tables use the use of a high sensitivity LNA to improve the system sensitivity in the wider signal area and switch to a high linearity LNA based on the response of the jammer detector when the sensed jammer crosses a predetermined threshold. Allow to maximize In one aspect, the values of the AGC table are based on one or more of the following: gain compression point; Mixer protection; ADC protection from saturation; And intermodulation product level per CNR degradation. Another example may be several tables for mode 1 with optimized switch point and set versus operating frequency and one table for mode 2 with optimized switch point and set versus operating frequency. Another example is an adaptive switch point table based on, for example, frequency, modulation scheme or a combination of all parameters.

4 shows an example of a state transition diagram for dual mode in terms of switch point (SP) and gain states. The switch point is represented by SPxy with an x value representing the mode and a y value representing the switch point. In FIG. 4, each mode (mode 1 and mode 2) has six switch points. The gain state is indicated by G0 through G6 for mode 1 and G1 through G6 for mode 2. G0 is bypassed in mode 2. The top line shows the state transition for the high sensitivity mode (mode 1) and the bottom line shows the state transition for the high linearity mode (mode 2). As shown in FIG. 4, at each switch point, a different gain state is selected.

5A shows an example of the resulting dual mode AGC receiver gain state as a function of input RF level for both high sensitivity mode (mode 1) and high linearity mode (mode 2). As shown in FIG. 5A, in mode 1, the dual mode AGC receiver starts in the highest gain state G0 for the low input power level Pin and corresponds to the corresponding noise figure NF as the input power level Pin increases. _G1 , Transition from the switch points SP11, SP12, SP13 ... with NF _G2 , NF _G3 ...) to the continuous gain states (G1, G2, G3, ...). As shown in FIG. 5A, in mode 2, the dual mode AGC receiver starts in a gain state G1 for a low input power level (Pin) and corresponding switch points (SP22, SP23) as the input power level (Pin) increases. Transitions to successive gain states (G2, G3, ...) with corresponding noise figures (NF _G2 , NF _G3 ...). Switch point SP21 for mode 2 is set at a very low input power level, for example 200 dBm, to bypass the gain state G0 in mode 2.

5B shows an example of the resulting dual mode AGC receiver noise figure state as a function of input RF level for both high sensitivity mode (mode 1) and high linear mode (mode 2). As shown in FIG. 5B, in mode 1, the dual mode AGC receiver starts at the highest gain state G0 and the lowest noise figure NF _G0 for the low input power level (Pin), and the input power level (Pin) is increased. Increasingly, it transitions from the corresponding switch points (SP11, SP12, SP13 ...) to successive gain states (G1, G2, G3, ...). As shown in FIG. 5B, in mode 2, the dual mode AGC receiver starts at a gain state G1 and a corresponding noise figure NF _G1 for a low input power level (Pin), and responds as the input power level (Pin) increases. Transitions to a continuous gain state (G2, G3, ...) with corresponding noise figures (NF _G2 , NF _G3 ...) at the switch points (SP22, SP23 ...). Switch point SP21 for mode 2 is set at a very low input power level of 200 dBm, for example, to bypass the gain state G0 in mode 2.

Based on the state of the jammer detector, the AGC switch points are improved or inferior to each other as shown in FIG. 4. The AGC switch point affects the LNA gain state and noise figure for RF input power as shown in FIG. 5A. In the high gain state, AGC switch points may or may not be merged. The merging characteristic is dependent on the output voltage level with respect to the input power, where the output voltage level is limited so as not to exceed the ADC full scale reference to prevent ADC saturation. In one aspect, the value of the switch point is modified to switch earlier when jammers are present. In one aspect, the value of the switch point between the gain states (not the G0 state) is adaptive based on the jammer level.

In one aspect, the switch point (SP) defined above is updated when switching between modes. In addition, the switching logic includes hysteresis to prevent toggling between modes. In another example, each jammer detector (JD) has its own switch point register to store its threshold. In another aspect, for higher gain states (eg, gain states above G3), JD may optionally be ignored. In another example, in the high gain state, the AGC SPs merge to become identical.

In another aspect, the AGC switch point table may be adaptive based on the received jammer level. The AGC switch point table is based on several parameters such as receiver compression point, ADC saturation point, IMR3 level that degrades the carrier / noise ratio, and operating frequency that affects the gain response as well as the parameters mentioned. In a jammer-free environment, the AGC switch point is optimized for the receiver to meet linearity and sensitivity requirements. In one example, the AGC switch point may be modified to transition earlier based on the presence of jammers. The modification may be adaptive based on the received jammer power level.

6 shows an example of an operation mode and state diagram. FIG. 6 shows that the transition between various operating states includes mode 1 for high sensitivity receiver state and mode 2 for high linearity receiver state, as well as debug mode and fixed mode.

7 shows an example of voltage requirements at the ADC input for different gain states for a receiver with AGC, which may or may not be dual mode. FIG. 7 is a graph of the output voltage (eg, input voltage to the ADC) from the RF section of the dual mode AGC receiver shown in FIG. 9 as a function of the input RF power to the mixer shown in FIG. 9. As the input RF power increases, the AGC circuit shown in FIG. 10A shows gain states (denoted by GS1, GS2, GS3, GS4 ... and also denoted by G1, G2, G3, G4 ...), Set the output voltage from the RF section (eg, the input voltage to the ADC) to stay below the ADC level maximum limit. The ADC level maximum limit is the margin for the ADC full scale maximum voltage as shown in FIG. The margin is intended to prevent ADC saturation from interfering with signal leakage and signal peak to average ratio (PAR), and to facilitate AGC accuracy tolerances.

8 shows an example of carrier to noise ratio (C / N) with increased intermodulation product levels for different gain states for the input RF power level to the mixer shown in FIG. As shown in FIG. 8, the carrier-to-noise ratio (C / N) degrades due to the increased intermodulation product level as the input level increases. In one example, such increase occurs due to the presence of strong jammers. Hysteresis between increased and reduced power is introduced into the AGC circuit to prevent toggling at the switch point. In the high sensitivity mode (mode 1), the RF chain has higher gain and lower noise figure, which increases dual mode AGC receiver sensitivity. On the other hand, in high linearity mode (mode 2), dual mode AGC receivers operate at lower gain and higher noise figure. In one example, the nominal gain (G0) state in high linearity mode provides a first mode 2 switch point (SP21) to protect the dual mode AGC receiver against C / N degradation due to the presence of strong jammers. Bypass is set to -200 dBm (as shown in FIG. 4).

The dual mode AGC receiver toggles between two modes. In one aspect, the two modes include a high sensitivity mode (mode 1) and a high linearity mode (mode 2), and the dual mode AGC receiver toggles between these two modes according to the input signal environment. If the dual-mode AGC receiver is in high sensitivity mode, it may need immediate protection when a strong jammer appears. In one example, this protection is implemented using a fast attack automatic gain control (AGC) circuit or algorithm or both. Fast attack refers to the characteristics of an AGC circuit or algorithm or both, which is a rapid gain reduction after the appearance of a strong input signal level (eg, jammer). Then, when the strong jammer disappears, the dual mode AGC receiver may need a slow release AGC circuit to avoid fast toggling between the two modes. Slow release refers to the characteristics of an AGC circuit or algorithm or both, which is a slow gain increase after the appearance of a strong input signal level (eg, a strong jammer). Fast Attack Slow Release or Slow Decay JD is a term derived from AGC that describes a rapid gain reduction when receiving a strong signal and a slow convergence to the final gain value. In this invention, there are two systems. AGC and jammer detectors. The jammer detector operates in fast attack slow release mode for the following reasons. The first priority is to protect the receiver and maintain the quality of service. Therefore, the jammer detector operates in fast attack mode and transfers the receiver to the protected mode. This mode is defined as "mode 2" which is high linearity normal sensitivity. Second, it is speculated that the incoming environment changes slowly (jammers appear or do not appear quickly). Therefore, in order to avoid toggling between the two modes and thereby reduce the performance of the receiver, there is a slow release process. In addition, the slow release process protects the system from fading and prevents signal distortion. Jammer detector signaling in the attack informs the BB (eg, AGC circuit or algorithm or both) to switch from the mode 1 AGC table to the mode 2 AGC table. Note that the AGC table is a table of other settings such as gain state switch point to input power, and current settings. The mode 1 switch point table is used for the high sensitivity low linearity mode. Therefore, this includes the G0 gain state. Mode 2 AGC tables are used for high linearity moderate sensitivity. Therefore it bypasses the G0 gain state by having its switch point setting intentionally set to, for example, -200 dBm. As a result, mode 2 starts in the G1 gain state, which is also a traditional receiver mode whose design is a tradeoff between sensitivity and linearity. As a result of the jammer detector interrupt, the gain of the system is reduced. The system maintains a low gain and mode 2 switch point AGC table for a given release time. The AGC manages the gain of the receiver with the lower gain mode 2 table and switches back to mode 1 only after the release time shows that there is no jammer during that release period. Therefore, slow release refers to AGC and JD operation, which means that the slow gain increases after the jammer disappears.

In conventional receiver designs, the AGC circuit is triggered by a single jammer detector (JD) designed for narrowband operation over a single radio frequency (RF) band. However, in many wireless scenarios, there are several interfering transmitters that operate in various frequency bands, transmit power levels, and modulation schemes. Single jammer detectors are not optimal for detecting a variety of jammers over very wide bandwidths. Nevertheless, there is a need to protect the receiver against all jammers appearing in a broadband environment.

In conventional receiver designs, there is a single AGC switch point table, and the design is a compromise between linearity and sensitivity. Therefore, the traditional design is similar to the mode 2 design, which is a protected mode. There is no sensitivity improvement when the jammer is below a certain predetermined threshold. Conventional receivers sacrifice sensitivity and protect against jammers by increasing the current in the LNA and mixer. Moreover, conventional receivers do not have a fast attack slow release JD process to operate in burst mode. This invention includes two types of jammer detectors. The receiver includes, for example, a narrowband jammer detector that monitors in-band close to jammers, such as alternative jammers appearing up to N + 4 (eg, the fourth adjacent band). Narrowband JD is implemented at the analog baseband of the receiver prior to the baseband filter for sensing jammers, or at the IF frequency of the superheterodyne receiver or any other frequency that receives a block at the receiver. Additionally, the receiver has a wideband jammer detector to protect the receiver from within the band far from the jammer.

9 shows an example of a dual mode AGC receiver 900. In one example, a dual mode AGC receiver with automatic gain control (AGC) has two modes for AGC with two switch point tables for gain states. Moreover, the dual mode AGC receiver has two LNA paths, one with high sensitivity low current (mode 1) and the other with high linearity moderate sensitivity (mode 2).

For dual mode AGC receivers, Mode 1 has high sensitivity and low linearity characteristics. Mode 2 has high linearity and moderate sensitivity characteristics. Mode 1 uses an LNA with low noise figure, high gain, and low current consumption. Mode 1 is used when there is a low level jammer at the receiver input or when there is no jammer. Mode 2 uses LNA with lower gain, higher IP3, and higher current consumption. Mode 2 is used when there is a strong jammer at the dual mode AGC receiver input. The transition between the two modes is implemented by an automatic gain control (AGC) circuit triggered by a jammer detector (JD) not shown in FIG. The AGC switch switches between mode 1 switch point table (high sensitivity, low NF) to mode 2 switch point table (high linearity normal sensitivity) when a strong jammer is detected.

In one example, the input RF signal is captured by a receive antenna (not shown) connected to a dual mode AGC receiver, and inputs (910, 920 respectively) and mode 1 of both mode 1 LNA and mode 2 LNA for low noise amplification. The output RF signal and the mode 2 output RF signal are respectively sent to the production. As shown in FIG. 9, the mode 1 LNA has an input 910 and the mode 2 LNA has an input 920. The AGC circuit provides a mechanism (not shown) for selecting between the mode 1 output RF signal and the mode 2 output RF signal to produce a selected output RF signal. Those skilled in the art will appreciate that various mechanisms known in the art can be used to select modes without affecting the spirit and scope of the present disclosure.

The selected output RF signal is sent to a mixer / low pass filter (LPF) 930 for frequency downconversion and production of the input baseband signal. The input baseband signal is sent to an analog-to-digital converter (ADC) 940 for conversion to an input digital signal. The input digital signal is then sent to the digital variable gain amplifier (DVGA) 950 as an example for gain adjustment and production of the output digital signal. The output digital signal is then taken as an example to a sample server (SS) module 960 for capturing digital symbols and sending them for subsequent demodulation processes, and also the energy of the output digital signal (eg, receiver output energy). Is sent to an energy estimator (EE) 970 for the estimation of.

In one aspect, the dual mode AGC receiver toggles between the first mode and the second mode based on the input RF signal level. As shown in FIG. 9, a dual mode AGC receiver includes a first LNA operating in a first mode, a second LNA operating in a second mode, a jammer detector providing jammer interrupt bits to indicate the presence of jammers, and An automatic gain control (AGC) circuit or algorithm or both coupled to the jammer detector for receiving the jammer interrupt bits, wherein the AGC circuitry is between the first LNA and the second LNA based on the jammer interrupt bits and the gain state comparison. Choose. The dual mode AGC receiver further includes a mixer coupled to one of the two LNAs and downconverts the input RF signal to a downconverted signal. The dual mode AGC receiver includes a low pass filter (LPF) coupled to the mixer for filtering the downconverted signal to produce a filtered downconverted signal. The filtered downconverted signal is input to an analog-to-digital converter (ADC) that digitizes the filtered downconverted signal to produce a digitized signal. The digitized signal is then input to a digital variable gain amplifier (DVGA), which DVGA scales the digitized signal. An energy estimator coupled to the DVGA receives the scaled digitized signal and uses it to estimate the receiver output energy. Receiver output energy is then input to the jammer detector and used to set the jammer detector threshold. The value of the jammer interrupt bit, indicating the presence of the jammer, is based on a comparison of the level of the RF input signal against the jammer detector threshold. In one aspect, the dual mode AGC receiver includes a processor for obtaining a normalized receiver input energy at an input to one of the two LNAs based on the receiver input energy at baseband. As shown in FIG. 9, the receiver input energy at baseband can be tapped at any of the outputs of the ADC or DVGA, or at the input to the ADC. The processor sets the new gain and normalized receiver input energy of the dual mode AGC receiver to reflect the new mode, where the processor instructs the jammer detector to update the jammer detector threshold. In one example, the processor is part of the AGC circuit.

9A, 9B, and 9C show three examples of a dual mode AGC receiver. 9A shows an example of a dual mode AGC receiver with two LNA paths, each path using a full gain chain. Mode 2 LNA includes six gain states (G1 through G6) with all six gain states operating at high currents. Mode 1 LNA includes seven gain states (G0 to G6) with all seven gain states operating at low current. 9B shows a second example of a dual mode AGC receiver with a single LNA path including gain states G0 through G6. In the example of FIG. 9B, the gain state G0 is part of the gain chain, but G0 is skipped when the dual mode AGC receiver is operating in mode two. 9C shows an example of a dual mode AGC receiver with two LNA paths, each using a full gain chain and a dedicated mixer / low pass filter. Mode 2 LNA includes six gain states (G1 to G6) and a mixer / low pass filter with all six gain states operating at high currents. Mode 1 LNA includes seven gain states (G0 to G6) and a mixer / low pass filter with all seven gain states operating at low currents. It will be understood that it implies a relative value for.

10A shows an example of a block diagram of a jammer detector (JD) 1010 coupled to an automatic gain control (AGC) circuit 1020. A jammer detector (JD) 1010 and an automatic gain controller (AGC) circuit 1020 are connected to the dual mode AGC receiver 900 shown in FIG. In one aspect, the jammer detector (JD) 1010 and automatic gain control (AGC) circuit 1020 are part of the dual mode AGC receiver 900. A jammer detector input signal comprising both a jammer and a desired signal is sent to a jammer detector (JD) 1010 for detection of a strong jammer. In one example, the jammer detector input signal is the output of an energy estimator (EE) 970 (shown in FIG. 9). If the level of the jammer detector input signal exceeds a predetermined jammer detector threshold TH _j , the jammer detector interrupt bit is set by the jammer detector JD 1010 and sent to the AGC circuit 1020. In one example, jammer detector interrupt bit = 1 means that a jammer level above TH _j has been detected. And jammer detector interrupt bit = 0 means that there is no jammer level above TH _j . In one example, the jammer detector threshold TH _j is applied to a comparator in the jammer detector. In one aspect, the jammer detector 1010 is a combination of a plurality of jammer detectors, each set to a predetermined jammer detector threshold TH _j . In one aspect, jammer detector 101 is based on several complementary jammer detectors, based on both hardware and software. Jammer detector 1010 includes a narrowband jammer detector (NB JD) for detecting in-band jammers, a wideband jammer detector (WB JD) for detecting out-of-band jammers and distant jammers, and a concurrent operating jammer A software jammer detector (SW JD). Each of NB JD, WB JD, and SW JD has its own optimized jammer detector threshold TH _j . Those skilled in the art will appreciate that, in accordance with the spirit and scope of the present disclosure, the jammer detector 1010 may be a plurality of jammer detectors, each set to a predetermined jammer detector threshold TH _j .

The AGC circuit 1020 accepts jammer detector interrupt bits or interrupt status bits, as well as current LNA gain states, current DVGA gain states, and current EE values, as inputs to the AGC circuit or algorithm or both. . The output of the AGC circuit is an updated LNA gain state and an updated DVGA gain state based on various AGC inputs. The AGC circuit selects one of the two LNAs based on a jammer interrupt bit and a gain state comparison of the series of current LNA gain states and gain state thresholds. In one example, the output of the AGC circuit or algorithm or both represents the output of two LNA and DVGA 950 (shown in FIG. 9). The AGC circuit or algorithm or both 1020 include two AGC tables that govern the selection of gain states in the high sensitivity mode (mode 1) and high linearity mode (mode 2). In one example, to indicate the presence of a strong jammer, when the dual mode AGC receiver is set to mode 1 (high sensitivity mode) and the jammer detector interrupt bit is asserted to HIGH (eg, bit = 1) The AGC circuit 1020 responds by setting the updated LNA gain state and the updated DVGA gain state to appropriate values of mode 2 (high linearity mode). In one aspect, two AGC tables are combined into one AGC table. In another example, if the dual mode AGC receiver is set to mode 2 (high linearity mode) and the jammer detector interrupt bit remains LW (ie, bit = 0) for a predetermined time period, the absence of strong jammers for the predetermined time period To indicate, AGC circuit 1020 sets the updated LNA gain state and the updated DVGA gain state to the appropriate values of mode 1.

10B shows an example of an ultra wideband dual AGC receiver block diagram. The jammer detector 1010 of FIG. 10A includes three separate detectors: a narrowband jammer detector, a wideband jammer detector, and a software-based jammer detector, as shown in more detail in FIG. 10B. Interrupts from these three detectors are sent to the JD read block which sends the synthesized interrupt signal to the AGC algorithm block for control of the gain state described above. The serial bus interface (SBI) controller also provides several control signals (counter, interrupt mask, threshold set, and interrupt clear) to the jammer detector based on the status of the JD and AGC algorithms.

In one aspect, the mode 2 (high linearity mode) LNA has a plurality of gain states. In one example, the mode 2 LNA has three gain states (G1, G2, and G3) in order of decreasing gain and increasing noise figure. Additionally, mode 2 may have other higher gain states G4, G5, and G6. In one aspect, in an AGC circuit, the mode 2 LNA gain state depends on the intersection of the AGC switch points. In one example, the mode 1 LNA has a plurality of gain states. Those skilled in the art will appreciate that the amount of gain state for Mode 1 and / or Mode 2 may be selected depending on the particular application and design parameters without affecting the spirit or scope of the present disclosure.

Each of the two AGC tables includes one set of AGC switch points (SP) corresponding to each of the two modes of the dual mode AGC receiver. In one example, for mode 1, the AGC switch point SP for transition from gain state G0 to G1 is approximately -80 dBm. Gain state G0 corresponds to the low noise figure, high gain LNA path in mode 1. In one example, for mode 2, the AGC switch point SP for transition from gain state G0 to G1 is set very low, for example approximately -200 dBm, so that gain state G0 is skipped and lower In the input signal level condition, the gain state G1 is active. In one aspect, the setting of the AGC switch point SP is updated when there is a switching between the two modes. Hysteresis is added to prevent toggling between the two modes.

Dual mode AGC receivers improve the sensitivity of the receiver in the presence of jammers compared to conventional single mode receivers. In addition, the dual-mode AGC receiver provides buffering for analog-to-digital converter (ADC) noise so that the overall system noise figure is minimal. For example, in a digital receiver, the analog signal of the receiver is sampled by an analog-to-digital converter (ADC). The ADC generates ADC noise, denoted as N _ADC . The design of the digital receiver is governed by the desired carrier to noise ratio (C / N). The design parameters of the LNA are selected to optimize C / N. The effect of the noise figure of the LNA on the total RF noise figure is described by equation (1).

(One)

Equation (1) shows that LNAs with low noise figure F ₁ and high gain G ₁ have lower F _eq .

It compensates for the noise figure of the rest of the resulting RF chain. Furthermore, the LNA also compensates for ADC noise. The RF section at the ADC input has a noise figure F _T and a gain G _T. The ADC may be modeled as a cascaded block with a noise figure F _ADC . Therefore, the ADC noise at that input port is given by equation (2). ADC noise includes quantization noise, thermal noise and other noise components.

(2)

The total RF noise referenced at the ADC input is given by equation (3).

(3)

The cascaded noise figure is given by equation (4).

(4)

Equation (4) is a cascaded noise figure when G _T is increased due to a larger nominal (G0) gain state compared to the G1 gain state and a reduced total RF noise figure F _T when at nominal (G0) gain state. Indicates improved.

Equation (5) defines the noise ratio (NR).

(5)

Such that the expression N _ADC is the ADC noise density given by equation (2) (5), k is Boltzmann (Boltzmann) constant, T is the room temperature in degrees Kelvin, GT is the total RF gain, F _T is the total RF noise figure and F _ADC is the ADC noise figure.

Equation (5) indicates that the low noise figure LNA with high gain results in higher RF noise N _RF than the ADC noise N _ADC . This relationship indicates that the ADC noise contribution to the overall system noise figure is negligible.

Equation (6) defines the takeover gain (TOG).

(6)

As shown by equation (6), higher takeover gain (TOG) implies lower ADC noise contribution. In addition, the NR is improved and the cascaded noise figure F _{T_Rx} approaches F _T. 11 is a spectral plot of noise versus frequency (measured in dBm). FIG. 11 is an exemplary ratio between RF noise ( N _RF ) to ADC noise ( N _ADC ) at the analog output of mixer / low pass filter (LPF) 930 (shown in FIG. 9) along the frequency axis. Is shown for frequency. ΔN = N _RF -N _ADCs represent the ratio between logarithmic (dB) RF noise (N _RF ) and ADC noise (N _ADC ).

The dual mode AGC receiver uses a nominal (G0) gain state with improved noise figure and higher gain to improve the cascaded noise figure F _{T _ Rx} compared to the cascaded noise figure under the G1 gain state. Performance improvement is possible because under the G0 gain state, G _T is higher compared to the G1 gain state. Therefore, the cascaded noise figure F _{T _ Rx} is further improved and approaches F _T as shown in equation (4), and the takeover gain is improved.

Equation (7) represents the cascaded noise figure (NF) ratio between the G1 gain state and the G0 gain state. Equation (8) represents the TOG ratio between the G1 gain state and the G0 gain state.

(7)

(8)

AGC circuit interaction with a jammer detector (JD) is shown in FIG. 10A, and the gain state and noise figure state for the operating modes are provided in FIGS. 4 to 6. Inputs to the processor algorithm are LNA-mixer gain state, DVGA (digital variable gain amplifier) state, jammer detector interrupt status, and EE (energy estimator) values. Based on this input and energy estimate, a new AGC state, a new LNA state and a new DVGA state are calculated. In one aspect, the processor 905 (not shown) of the dual mode AGC receiver performs the calculation. In one example, the processor 905 is part of the AGC circuit 1020.

12 shows an example flow diagram for toggling between dual modes (such as high sensitivity mode and high linearity mode) based on an input signal environment (eg, input signal level). In block 1210, estimate the receiver input energy of the dual mode AGC receiver. In one aspect, the receiver input energy is measured at baseband, eg, input to the ADC, output of the ADC or output of the DVGA. Receiver input energy includes jammer energy, desired signal level, and noise level. In block 1220, the normalized receiver input energy at the receiver front end (eg, at a dual mode AGC receiver input to one of the LNAs shown in FIG. 9) by dividing the receiver input energy at baseband by an aggregate gain. Acquire. In one aspect, the processor 905 obtains normalized receiver input energy. The aggregate gain includes the gain of one or more of one or more DVGA 950, ADC 940, mixer / LPF 930 and two LNAs (shown in FIG. 9), depending on the mode of the dual mode AGC receiver. In block 1230, determine the current mode of the dual mode AGC receiver. If the dual mode AGC receiver is in mode 1 (high sensitivity mode), proceed to block 1240. In block 1240, for example, use the Mode 1 AGC SP table (with switch points S11 through S16). If the dual mode AGC receiver is in mode 2 (high linearity mode), proceed to block 1250. In block 1250, for example, use a Mode 2 AGC SP table (with switch points S 21 through S26). In block 1241 subsequent to block 1240, it is determined whether the gain state GS is greater than or equal to G0 and less than or equal to G1 (eg, G0 ≦ GS ≦ G1). In one example, determine whether the mode 1 comparator threshold is for G0 or G1. If the gain state GS is greater than or equal to G0 and less than or equal to G1, proceed to block 1243. If the gain state GS is not greater than or equal to G0 and less than or equal to G1, proceed to block 1242. In block 1242, determine whether the gain state GS is greater than G2. In one example, determine if the mode 1 comparator threshold is for G2. If the gain state GS is greater than G 2, proceed to block 1280. If the gain state GS is not greater than G2, go to block 1243. In block 1243, determine the value of the jammer detector interrupt bit. The value of the jammer detector interrupt bit is based on the input signal level and the jammer detector threshold TH _j . The value of the jammer detector interrupt bit is used to determine whether to switch the current mode to the new mode. If the jammer detector interrupt bit is 1, proceed to block 1245 to switch the dual mode AGC receiver to mode 2 (high linearity mode) and use the mode 2 AGC SP table (with switch points S21 to S26). If the jammer detector interrupt bit is zero, go to block 1280. In one example, the state of the jammer detector is based on the status of the input to the jammer detector and the jammer detector interrupt bit.

In block 1251, following block 1250, determine whether the gain state GS is greater than or equal to G1 and less than or equal to G2 (eg, G1 ≦ GS ≦ G2). In one example, determine whether the mode 2 comparator threshold is for G1 or G2. If the gain state GS is greater than or equal to G1 and less than or equal to G2, proceed to block 1253. If the gain state GS is not greater than or equal to G1 and less than or equal to G2, proceed to block 1252. In block 1252, determine whether the gain state GS is greater than G3. In one example, determine if the mode 2 comparator threshold is for G3. If the gain state GS is greater than G3, go to block 1280. If the gain state GS is not greater than G3, go to block 1253. In block 1253, determine a value of the jammer detector interrupt status bit. The value of the jammer detector interrupt status bit is based on the input signal level and the jammer detector threshold TH _j . The jammer detector interrupt status bit is used to determine whether to switch the current mode to the new mode. If the jammer detector interrupt status bit is zero, proceed to block 1255 to switch the dual mode AGC receiver to mode 1 (high sensitivity mode) and use the mode 1 AGC SP table (with switch points S11 to S16). If the jammer detector interrupt status bit is 1, proceed to block 1280.

Subsequent to block 1245 or block 1255, proceed to block 1260. In block 1260, update the jammer detector threshold. In one aspect, the jammer detector threshold at the jammer counter (not shown) is updated. In another aspect, the jammer detector threshold in the jammer comparator (not shown) is updated. Following block 1260, flow proceeds to block 1270. At block 1270, set a new gain state that reflects the mode (eg, new mode) of the dual mode AGC receiver after switching and reflects the normalized receiver input energy. At block 1270, the jammer detector threshold is updated in the jammer comparator based on the new gain state. At block 1280, set a new gain state that reflects the current mode of the dual mode AGC receiver and reflects the normalized receiver input energy. At block 1280, the jammer detector threshold is updated in the jammer comparator based on the new gain state. In one aspect, the new gain state may be the same as the gain state GS. In one example, the new gain state at block 1270 or block 1280 includes an LNA gain and / or a post-LNA gain. In one aspect, following block 1270 or 1280, return to block 1210. Those skilled in the art will appreciate that the algorithm or portion shown in FIG. 12 may be repeated without affecting the spirit or scope of the present disclosure. In one aspect, the portion of the algorithm shown in FIG. 12 is performed by a processor 905 (not shown) in the dual mode AGC receiver 900. In another aspect, the processor 905 is part of the AGC circuit 1020.

Those skilled in the art will appreciate that various descriptive components, logic blocks, modules, circuits, and / or algorithm steps described in connection with the examples described herein may be implemented as electrical hardware, firmware, computer software, or a combination thereof. To clearly illustrate this, the interchangeability of hardware, firmware, and software, various illustrative components, blocks, modules, circuits, and / or algorithm steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope or spirit of the present disclosure.

For example, for a hardware implementation, the processor (s) may include one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays ( FPGA), a processor, a controller, a micro-controller, a microprocessor, another electronic unit for performing the functions described herein, or a combination thereof. With software, implementations may be through modules (eg, procedures, functions, etc.) that perform the functions described herein. Software codes may be stored in a memory unit and executed by a processor. In addition, the various illustrative flow diagrams, logic blocks, modules, and / or algorithm steps described herein may also be coded as computer-readable instructions executed on any computer-readable medium known in the art.

13 shows an example of a device 1300 suitable for toggling between dual modes (such as high sensitivity mode and high linearity mode) based on an input signal environment. In one aspect, the device 1300 is input at blocks 1310, 1320, 1330, 1340, 1341, 1342, 1343, 1345, 1350, 1351, 1352, 1353, 1355, 1360, 1370, and 1380 as described herein. Based on the signal environment, it is implemented by at least one processor including one or more modules configured to provide different aspects of toggling between dual modes (such as high sensitivity mode and high linearity mode). For example, each module includes hardware, firmware, software, or any combination thereof. In one aspect, the device 1300 is also implemented by at least one memory in communication with at least one processor.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the disclosure.

Claims (22)

A receiver having a first mode and a second mode, the receiver toggles between the first mode and the second mode based on a level of an input RF signal,
The receiver includes:
A first low noise amplifier (LNA) operating in the first mode;
A second LNA operating in said second mode;
A jammer detector providing a jammer interrupt bit indicative of the presence of a jammer; And
An automatic gain control (AGC) circuit coupled to the jammer detector to receive the jammer interrupt bit;
The AGC circuit selects between the first LNA and the second LNA based on the jammer interrupt bit and gain state comparison. The method of claim 1,
A mixer coupled to one of the first LNA and the second LNA to downconvert the input RF signal to a downconverted signal; And
And a low pass filter (LPF) coupled to the mixer to filter the downconverted signal to produce a filtered downconverted signal. The method of claim 2,
An analog-to-digital converter (ADC) coupled to the LPF to digitize the filtered downconverted signal to generate a digital signal and input the digital signal to a digital variable gain amplifier (DVGA);
The DVGA scales the digital signal. The method of claim 3, wherein
An energy estimator coupled to the DVGA, the energy estimator estimating a receiver output energy based on the scaled digital signal,
And the receiver output energy is input to the jammer detector for use in setting a jammer detector threshold. The method of claim 4, wherein
And the value of the jammer interrupt bit is based on a comparison of the level of the input RF signal to the jammer detector threshold. The method of claim 1,
And a processor for obtaining a normalized receiver input energy at an input to one of the first LNA and the second LNA based on receiver input energy at baseband. The method according to claim 6,
The processor sets a new gain of the receiver to reflect the new mode and the normalized receiver input energy. The method of claim 7, wherein
The processor instructing the jammer detector to update a jammer detector threshold. A receiver having a first mode and a second mode, the receiver toggles between the first mode and the second mode based on an input signal level,
The receiver includes:
A first low noise amplifier (LNA) operating in the first mode;
A second LNA operating in said second mode;
A jammer detector providing a jammer interrupt bit indicative of the presence of a jammer;
Means for receiving the jammer interrupt bit and selecting between the first LNA and the second LNA based on the jammer interrupt bit and gain state comparison. The method of claim 9,
Means for setting a new gain of the receiver to reflect a selection between the first LNA and the second LNA. A method of toggling between a first mode and a second mode of a receiver based on an input signal level, the method comprising:
The method of toggling,
Comparing the gain state of the receiver to at least one gain state threshold;
Determining the presence of jammers; And
Switching the current mode of the receiver to a new mode based on a comparison of the presence of the jammer and the gain state. The method of claim 11,
Determining the current mode of the receiver;
And the current mode is one of high linearity mode or high sensitivity mode. The method of claim 12,
Estimating the receiver output energy. The method of claim 13,
And obtaining a normalized receiver input energy based on the receiver output energy. The method of claim 14,
Setting a new gain of the receiver to reflect the new mode and the normalized receiver input energy. The method of claim 15,
Updating the jammer detector threshold. The method of claim 11,
Estimating the receiver output energy. The method of claim 17,
And obtaining a normalized receiver input energy based on the receiver output energy. The method of claim 18,
And making a decision not to switch from the current mode to the new mode. The method of claim 19,
Setting a new gain of the receiver to reflect the current mode and the normalized receiver input energy. A computer-readable medium for storing a computer program, comprising:
Execution of the computer program,
Compare the gain state of the receiver with one or more gain state thresholds;
Determine a value of the jammer detector interrupt bit based on the input signal level and the jammer detector threshold; And
And for determining whether to switch a current mode to a new mode based on a comparison of the value of the jammer detector interrupt bit and the gain state. The method of claim 21,
Execution of the computer program is also to determine the current mode of the receiver, the current mode being either a high linearity mode or a high sensitivity mode.

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