KR20110035575A

KR20110035575A - Semiconductor memory device

Info

Publication number: KR20110035575A
Application number: KR1020090093360A
Authority: KR
Inventors: 이재영; 이중화
Original assignee: 삼성전자주식회사
Priority date: 2009-09-30
Filing date: 2009-09-30
Publication date: 2011-04-06

Abstract

PURPOSE: A semiconductor memory device is provided to improve sensing sensitivity by forming first and second column selectors. CONSTITUTION: In a semiconductor memory device, a first cell array region, first and second sense regions(200_1,200_2), and a second cell array are defines in a substrate. The first and second bit line are coupled with a plurality of memory cells. A plurality of memory cells are formed in the first cell array region. First and second complementary bit lines are coupled with plural memory cells. A plurality of memory cells are formed in the second cell array region. A first column selector(140 1) is formed within a first sense circuit area. The first column selector is coupled with the first bit line and the first complementary bit line. A second column selector(140 2) is formed within a second sense circuit area. The second column selector is coupled with the second bit line and the second complementary bit line. The first column selector and the second selector are adjacent to each other.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a layout structure of a semiconductor memory device.

Conventional semiconductor memory devices have been developed based on folded bit line structures. In the folded bit line structure, since both the bit line and the complementary bit line are located in the same memory cell array, coupling noise with the word line occurs in the same amount in the bit line and the complementary bit line. Such common mode noise is advantageously eliminated by the differential amplification operation of the sense amplifier. However, there is a limit in reducing the size of a memory cell in a folded bit line structure. Recently, research on an open bit line structure has been conducted to improve the degree of integration.

An object of the present invention is to provide a semiconductor memory device with improved sensing sensitivity.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of a semiconductor memory device of the present invention for achieving the above technical problem is a first cell array region, a first sense circuit region, a second sense circuit region, a second in order from a first side to a second side. A substrate having a cell array region defined therein, first and second bit lines coupled with a plurality of memory cells formed in the first cell array region, and first and second coupled with a plurality of memory cells formed in the second cell array region A second complementary bit line, a first column selector formed in the first sense circuit region and coupled with the first bit line and the first complementary bit line, and a second bit line and the second complementary bit formed in the second sense circuit region A second column selector coupled with the line, wherein the first column selector and the second column selector are formed immediately adjacent.

Here, the first complementary bit line extends across the second sense circuit region to the first sense circuit region, and the second bit line extends across the first sense circuit region to the second sense circuit region. Can be.

The memory device may further include a first conductive first sense amplifier and a second conductive second sense amplifier formed in the first sense circuit region, and further include a first formed in the second sense circuit region. The apparatus may further include a second conductivity type third sense amplifier and a first conductivity type fourth sense amplifier.

In particular, in a memory device according to some embodiments of the present disclosure, a first column selector may include a first column select transistor coupled between a first bit line and a first input / output line, a first complementary bit line, and a first complementary input / output line. And a second column select transistor coupled between the first conductive first sense amplifier, the first sensing transistor coupled with the first bit line, and the second sensing transistor coupled with the first complementary bit line. And a distance between the first column selection transistor and the first sensing transistor and a distance between the second column selection transistor and the second sensing transistor may be substantially the same.

In a memory device according to some embodiments of the present disclosure, a first conductive first sense amplifier, a first equalizer, and a second conductive second sense amplifier in a first sense circuit area in order from a first side to a second side. And a first column selector disposed in the second sense circuit region, in order from the first side to the second side, the second column selector, the second conductivity type third sense amplifier, the second equalizer, and the first conductivity type. A fourth sense amplifier can be arranged.

In a memory device according to some embodiments of the present disclosure, a first conductive type first sense amplifier, a second conductive type second sense amplifier, and a first equalizer may be provided in a first sense circuit area in order from a first side to a second side. And a first column selector disposed in the second sense circuit region, in order from the first side to the second side, the second column selector, the second equalizer, the second conductive type third sense amplifier, and the first conductive type. A fourth sense amplifier can be arranged.

In a memory device according to some embodiments of the present disclosure, a first equalizer, a first conductive type first sense amplifier, and a second conductive type second sense amplifier may be disposed in a first sense circuit area in order from a first side to a second side. And a first column selector, the second column selector, the second conductivity type third sense amplifier, the first conductivity type fourth sense amplifier, in the second sense circuit region in order from the first side to the second side; The second equalizer may be arranged.

In the memory device according to some example embodiments of the inventive concepts, the first conductivity type may be P type and the second conductivity type may be N type.

Another aspect of the semiconductor memory device of the present invention for achieving the technical problem is a first bit line and a first complementary bit line arranged in an open bitline type, the second bit line arranged in an open bit line type And a second complementary bit line, a first conductive type first sense amplifier, a first equalizer, a second conductive type second sense amplifier, a first column selector, and a second column selector, which are sequentially disposed from the first side to the second side. And a second conductive third sense amplifier, a second equalizer, and a first conductive fourth sense amplifier, wherein the first conductive first sense amplifier, the first equalizer, the second conductive second sense amplifier, The first column selector is connected to the first bit line and the first complementary bit line, and the second column selector, the second conductive third sense amplifier, the second equalizer, and the first conductive fourth sense amplifier are connected to the second bit line. And a second complementary bit line.

Here, the first conductivity type may be P type and the second conductivity type may be N type.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

A semiconductor memory device according to embodiments of the present invention may be well understood by referring to FIGS. 1 to 12.

1 is a conceptual diagram illustrating a semiconductor memory device in accordance with example embodiments of the inventive concept.

Referring to FIG. 1, a semiconductor memory device according to example embodiments includes first and second memory cell arrays 10_1 and 10_2 and first to fourth sense circuit regions 20_1 to 20_4. Although only four sense circuit regions are shown in the drawings for convenience of description, the semiconductor memory device may have a larger number of sense circuit regions as necessary.

In particular, the semiconductor memory device according to the embodiments of the present invention has an open bit line structure. Therefore, as shown in FIG. 1, the bit lines BL0 to BL3 and the complementary bit lines BLB0 to BLB3 are disposed in different memory cell arrays 10_1 and 10_2. That is, the bit lines BL0 to BL3 are coupled to a plurality of memory cells (not shown) disposed in the first memory cell array 10_1, and the complementary bit lines BLB0 to BLB3 are connected to the second memory cell array ( And coupled to a plurality of memory cells (not shown) disposed within 10_2.

In addition, as shown, the bit line BL1 extends across the first sense circuit region 20_1 to the second sense circuit region 20_2, and the bit line BL3 is formed in the third sense circuit region ( And extends to the fourth sense circuit region 20_4 across 20_3. The complementary bit line BLB0 extends across the second sense circuit region 20_2 to the first sense circuit region 20_1, and the complementary bit line BLB2 crosses the fourth sense circuit region 20_4. Extends to the third sense circuit region 20_3,

In addition, the first to fourth sense circuits 20_1 to 20_4 are circuits for sensing data stored in a plurality of memory cells disposed in the first and second cell arrays 10_1 and 10_2, respectively. Each sense circuit 20_1 to 20_4 may include a P-type sense amplifier, an N-type sense amplifier, an equalizer, a column selector, and the like. In detail, the first sense circuit 20_1 is coupled with the bit line BL0 and the complementary bit line BLB0 to store data stored in the bit line BL0 or the memory cell coupled with the complementary bit line BLB0. Sensing. The second sense circuit 20_2 is coupled with the bit line BL1 and the complementary bit line BLB1 to sense data stored in the bit line BL1 or the memory cell coupled with the complementary bit line BLB1. The third sense circuit 20_3 is coupled with the bit line BL2 and the complementary bit line BLB2 to sense data stored in the bit line BL2 or the memory cell coupled with the complementary bit line BLB2. The fourth sense circuit 20_4 is coupled with the bit line BL3 and the complementary bit line BLB3 to sense data stored in the bit line BL3 or the memory cell coupled with the complementary bit line BLB3.

However, the first memory cell array 10_1 is disposed on the first side (eg, left side) S1, and the second memory cell array 10_2 is on the second side (eg, right side) S2. When disposed in the first to fourth sense circuits 20_1 to 20_4, the first to fourth sense circuits 20_1 are disposed between the first memory cell array 10_1 and the second memory cell array 10_2. , 20_3 is disposed on the first side S1, and the second and fourth sense circuits 20_2 and 20_4 are disposed on the second side S2. That is, the second sense circuit 20_2 is located on the second side S2 of the first sense circuit 20_1, the third sense circuit 20_3 is located under the first sense circuit 20_1, and the fourth sense circuit is located on the second sense circuit 20_1. 20_4 is located on the second side S2 of the third sense circuit 20_3. Thus, such a structure may be referred to as an altered bit line sense amplifier (BLSA) structure.

In a conventional folded bit line structure, as the size of a memory cell becomes smaller, the pitch between the bit lines (for example, BL0 and BLB0) also becomes smaller. Since the size of the memory cell is very small but the sense circuit is relatively large, it is difficult to implement the sense circuit between the pitches between the smaller bit lines (eg, BL0 and BLB0). However, the crossed bit line sense circuit structure forms sense circuits (eg, 20_1 and 20_2) in regions corresponding to two bit lines (eg, BL0 and BL1) (ie, first sense circuits). 20_1, the second sense circuit 20_2 is disposed adjacent to the side). Thus, the crossed bit line sense circuit structure can implement a sense circuit in a wider area than the folded bit line structure, so the crossed bit line sense circuit structure is advantageous for the integration / high performance of the semiconductor memory device.

2 is a circuit diagram illustrating a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention.

Referring to FIG. 2, each sense circuit 20_1 to 20_4 includes a P-type sense amplifier 110_1 to 110_4, an N-type sense amplifier 120_1 to 120_4, an equalizer 130_1 to 130_4, a column selector 140_1 to 140_4, and the like. It includes.

The bit line sense amplifiers 110_1 to 110_4 and 120_1 to 120_4 include the P-type sense amplifiers 110_1 to 110_4 and the N-type sense amplifiers 120_1 to 120_4, and the bit lines BL0 to BL3 and the complementary bit lines BLB0. Amplify the voltage difference of ~ BLB3).

Specifically, the P-type sense amplifier (for example, 110_1) disposed on the first side S1 is coupled between the bit line BL0 and the voltage line LA and is connected to the voltage level of the complementary bit line BLB0. And coupled between the sensing transistor MP1 of the first conductivity type (for example, P-type) and the complementary bit line BLB0 and the voltage line LA and turned on according to the voltage level of the bit line BL0. The first conductive sensing transistor MP2 is turned on. An N-type sense amplifier (for example, 120_1) disposed on the first side S1 is coupled between the bit line BL0 and the voltage line LAB and turned on according to the voltage level of the complementary bit line BLB0. A second conductive type (eg, N-type) sensing transistor MN1 coupled between the complementary bit line BLB0 and the voltage line LAB and turned on according to the voltage level of the bit line BL0. And a two-conducting sensing transistor MN2. Similarly, the P-type sense amplifier (eg, 110_2) disposed on the second side S2 includes sensing transistors MP11 and MP12 of the first conductivity type. The N-type sense amplifier (eg, 120_2) disposed on the second side S2 includes sensing transistors MN11 and MN12 of the second conductivity type.

The equalizers 130_1 to 130_4 precharge the bit lines BL0 to BL3 and the complementary bit lines BLB0 to BLB3 to a predetermined voltage level.

Specifically, the equalizer (for example, 130_1) disposed on the first side (S1) is of the second conductivity type (for example, N type) coupled between the bit line (BL0) and the voltage line (VBL). Between the equalizing transistor MN3, the second conductive type equalizing transistor MN4 coupled between the complementary bit line BLB0 and the voltage line VBL, and between the bit line BL0 and the complementary bit line BLB0. Coupled equalizing transistor MN5. The equalizing transistors MN3, MN4, and MN5 are all turned on in response to the equalizing signal PEQijB. Similarly, the equalizer (eg, 130_2) disposed on the second side S2 includes the equalizing transistors MN13, MN14, and MN15 of the second conductivity type.

The column selectors 140_1 to 140_4 selectively couple the bit lines BL0 to BL3 and the complementary bit lines BLB0 to BLB3 with the input / output lines IO0 and IO1 and the complementary input / output lines IOB0 and IOB1, respectively.

Specifically, the column selector (for example, 140_1) disposed on the first side S1 may be a second conductivity type (for example, N type) coupled between the bit line BL0 and the input / output line IO0. The column select transistor MN6 and the second conductive type column select transistor MN7 coupled between the complementary bit line BLB0 and the input / output line IOB0 may be included. Similarly, the column selector (eg, 140_2) disposed on the second side S2 includes column select transistors MN16 and MN17 of the second conductivity type.

Here, the column selectors 140_1 and 140_2 disposed on the first side S1 and the second side S2 may operate by receiving the same column selection signal CSL0. That is, the sense circuit (for example, 30_1) disposed on the first side S1 and the sense circuit (for example, 30_2) disposed on the second side S2 may operate simultaneously to output data simultaneously. .

Hereinafter, a layout of a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 3 to 7C. Here, for convenience of description, the first and second sense circuits will be mainly described, but those skilled in the art to which the present invention pertains will clearly understand the third and fourth sense circuits through the drawings.

3 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a first embodiment of the present invention. 4A and 4B are views for explaining the effect of the sense circuit used in the semiconductor memory device according to the first embodiment of the present invention.

2 and 3, first and second cell array regions (not shown in FIG. 1) and first to fourth sense circuit regions 200_1 to 200_4 are defined on a substrate. Specifically, the first memory cell array region is disposed on the first side (eg, left side) S1, and the second memory cell array region is disposed on the second side (eg, right side) S2. The first to fourth sense circuit regions 200_1 to 200_4 may be disposed between the first memory cell array region and the second memory cell array region, and the first and third sense circuit regions 200_1 and 200_3 may be formed of the first to fourth sense circuit regions 200_1 to 200_4. It is disposed on the first side S1, and the second and fourth sense circuit regions 200_2 and 200_4 are disposed on the second side S2. That is, the first cell array region, the first sense circuit region 200_1, the second sense circuit region 200_2, and the second cell array region are defined in order from the first side S1 to the second side S2. Can be.

Each sense circuit region 200_1 to 200_4 includes a P-type sense amplifier region 210_1 to 210_4, an N-type sense amplifier region 220_1 to 220_4, an equalizer region 230_1 to 230_4, and a column selector region 240_1 to 240_4. do.

For example, in the first sense circuit region 200_1, the P-type first sense amplifier 110_1, the first equalizer 130_1, and the N-type in order from the first side S1 to the second side S2. The second sense amplifier 120_1 and the first column selector 140_1 are disposed, and in the second sense circuit region 200_2, in order from the first side S1 to the second side S2, the second column. The selector 140_2, the N-type third sense amplifier 120_2, the second equalizer 130_2, and the P-type fourth sense amplifier 110_2 are disposed.

Each of the regions 210_1 to 210_4, 220_1 to 220_4, 230_1 to 230_4, and 240_1 to 240_4 referred to in FIG. 3 means an area in which each functional block is formed, and the actives in which the respective functional blocks are formed are separated from each other. It does not mean. That is, each of the regions 210_1 to 210_4, 220_1 to 220_4, 230_1 to 230_4, and 240_1 to 240_4 referred to in FIG. 3 is only a division in a functional sense but is not a division in a physical sense. Specifically, as illustrated in FIGS. 7 to 7C, different functional blocks may be formed in the same active, and different functional blocks may be formed in different actives.

As shown, since the column selector regions 240_1 to 240_2 are disposed in the middle of the sense circuit region, the first column selector 140_1 and the second column selector 140_2 are disposed in the middle of the sense circuit region. The first column selector 140_1 is formed to be biased toward the second side S2 in the first sense circuit region 200_1, and the second column selector 140_2 is formed on the first side in the second sense circuit region 200_2. It is formed inclined to S1. Specifically, the first column selector 140_1 is formed in the first sense circuit region 200_1, the second column selector 140_2 is formed in the second sense circuit region 200_2, and the first column selector 140_1. And second column selector 140_2 are immediately adjacent. Here, "is formed immediately adjacent" means that a circuit such as a P-type sense amplifier, an N-type sense amplifier, an equalizer, or the like is not disposed between the first column selector 140_1 and the second column selector 140_2. to be.

As such, when the first column selector 140_1 and the second column selector 140_2 are disposed in the middle of the sense circuit area, the first column selector 140_1 and the second column selector 140_2 may be disposed between the column selector (eg, 140_1) and the sense amplifier (eg, 1). Minimizing possible line loading mismatches. Line loading mismatch is one of the factors that reduces the sensitivity of sensing.

Specifically, for example, as shown in FIG. 4, the column select transistors MN6 and MN7 of the first column selector 140_1 may be formed in the first column selector region 240_1 and the P-type sense. In the amplifier region 210_1, the sensing transistors MP1 and MP2 of the P-type first sense amplifier 110_1 may be formed, and in the N-type sense amplifier region 220_1, the sensing transistors MP1 and MP2 may be formed. The sensing transistors MN1 and MN2 may be formed.

The distance a1 between the column select transistor MN6 and the sensing transistor MN1 is substantially equal to the distance a2 between the column select transistor MN7 and the sensing transistor MN2. That is, the length of the bit line BL from the P-type first sense amplifier 110_1 to the first column selector 140_1 and the complementary bit from the P-type first sense amplifier 110_1 to the first column selector 140_1. The length of the line BLB0 is substantially the same. Thus, line loading mismatches due to bit lines can be reduced.

The distance b1 between the column select transistor MN6 and the sensing transistor MP1 is substantially the same as the distance b2 between the column select transistor MN7 and the sensing transistor MP2. That is, the length of the bit line BL from the N-type second sense amplifier 120_1 to the first column selector 140_1 and the complementary bit from the N-type second sense amplifier 120_1 to the first column selector 140_1. The length of the line BLB0 is substantially the same. Thus, line loading mismatches due to bit lines can be reduced.

Similarly, the column select transistors MN16 and MN17 of the second column selector 140_2 may be formed in the second column selector region 240_2, and the P-type fourth sense amplifier may be formed in the P-type sense amplifier region 210_2. The sensing transistors MP11 and MP12 of 110_2 may be formed, and the sensing transistors MN11 and MN12 of the N-type third sense amplifier 120_2 may be formed in the N-type sense amplifier region 220_1. have. The distance c2 between the column select transistor MN16 and the sensing transistor MN11 is substantially the same as the distance c1 between the column select transistor MN17 and the sensing transistor MN12. The distance d2 between the column select transistor MN16 and the sensing transistor MP11 is substantially the same as the distance d1 between the column select transistor MN17 and the sensing transistor MP12.

Meanwhile, as shown in FIG. 3, one of the first side S1 and the second side S2 (eg, the first side S1) around the equalizer region (eg, 230_1). The P-type sense amplifier region 210_1 is disposed on the N-side, and the N-type sense amplifier region 220_1 and the column selector region 240_1 are disposed on the other side (for example, S2). Accordingly, the P-type first sense amplifier 110_1 is disposed on one of the first side S1 and the second side S2 (for example, the first side S1) around the equalizer 130_1. On the other side (for example, S2), an N-type second sense amplifier 120_1 and a first column selector 140_1 are disposed.

The P-type first sense amplifier 110_1 is formed in the N-type well W. The N-type well W is mainly formed by using an implant process. Due to the characteristics of the implant process, N-type impurities are gradually injected into the peripheral region of the implant target region. Therefore, the circuit block formed around the P-type first sense amplifier 110_1 is affected by the N-type impurity. This is called WPE (Well Proximity Effect). For example, in the case of a WPE, when a pair of transistors such as an N-type second sense amplifier 120_1 and a first column selector 140_1 are disposed around an N-well, a pair of transistors may be used. Threshold voltages Vth may be different from each other. Therefore, WPE is one of the factors that lower the sensing sensitivity.

However, when the semiconductor memory device according to the first embodiment of the present invention has the same arrangement, the P-type first sense amplifier 110_1, the N-type second sense amplifier 120_1, and the first column selector 140_1 Spaced apart. Therefore, the N-type second sense amplifier 120_1 and the first column selector 140_1 are not affected by the N-type well W. That is, the threshold voltages of the sensing transistors MN1 and MN2 of the N-type second sense amplifier 120_1 may be substantially the same. Threshold voltages of the column selection transistors MN6 and MN7 of the first column selector 140_1 may be substantially the same.

Similarly, the P-type fourth sense amplifier 110_2, the N-type third sense amplifier 120_2, and the second column selector 140_2 are spaced apart from each other, and the N-type third sense amplifier 120_2 and the second column selector ( 140_2) is not affected by the N-type well (W).

FIG. 5 illustrates only active and wells in a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention. FIG. 6 illustrates only active, wells, and gates in a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention. FIGS. 7A to 7C show parts of FIG. 5 in detail for convenience of description. One drawing. 5 to 7C are exemplary diagrams of implementing the sense circuit described with reference to FIG. 3.

First, referring to FIG. 5, first to seventh actives ACT1 to ACT7 and eleventh to seventeenth actives ACT11 to ACT17 are defined in a first conductivity type (eg, P-type) substrate. Here, the first and second actives ACT1 and ACT2 are formed in the second conductivity type (eg, N-type) well W1, and the eleventh and twelfth actives ACT11 and ACT12 are also second conductive type. It may be formed in the well W2.

As illustrated, the first to seventh actives ACT1 to ACT7 and the eleventh to seventeenth actives ACT11 to ACT17 may be symmetrically formed. However, the scope of the present invention is not limited thereto.

2, 6, and 7A to 7C, the first to fourth sense circuit regions 200_1 to 200_4 may be divided as shown in FIG. 6.

In addition, a plurality of sensing transistors are formed in the first to fourth actives ACT1 to ACT4, respectively. In detail, the first conductive sensing transistors MP1 and MP2 constituting the P-type sense amplifier 110_1 are formed in the first and second actives ACT1 and ACT2, respectively. Second and second sensing transistors MN1 and MN2 constituting the N-type sense amplifier 120_1 are formed in the third and fourth actives ACT3 and ACT4, respectively.

A plurality of sensing transistors are formed in the eleventh to fourteenth actives ACT11 to ACT14, respectively. Specifically, the first conductive sensing transistors MP11 and MP12 constituting the P-type sense amplifier 110_2 are formed in the eleventh and twelfth actives ACT11 and ACT12, respectively. Second and second sensing transistors MN11 and MN12 constituting the N-type sense amplifier 120_2 are formed in the thirteenth and fourteenth actives ACT13 and ACT14, respectively.

In the drawing, actives ACT1 to ACT4, ACT11, and ACT14 in which the sensing transistors MP1, MP2, MN1, MN2, MP11, MP12, MN11, and MN12 are formed are separated from each other, but are not limited thereto. In the drawing, the shapes of the gates G1 G2, G4, G5, G11 G12, G14, and G15 of the sensing transistors MP1, MP2, MN1, MN2, MP11, MP12, MN11, and MN12 are H-shaped, but are not limited thereto. It doesn't happen.

The column select transistors MN6 and MN7 constituting the first column selector 120_1 may be formed in the fifth and sixth actives ACT5 and ACT6, and the second and second active portions ACT15 and ACT16 may be formed. Column select transistors MN6 and MN7 constituting the column selector 120_2 may be formed. As illustrated, one gate G6 may be formed to cross the fifth and sixth actives ACT5 and ACT6 and the fifteenth and sixteenth actives ACT15 and ACT16. Since the column select transistors MN6, MN7, MN16, and MN17 are coupled to one gate G6, the layout area can be reduced.

Equalizing transistors MN3 to MN5 constituting the first equalizer 130_1 are formed in the seventh active ACT7, and equalizing transistors MN13 to MN15 constituting the second equalizer 130_2 are formed in the seventeenth active ACT17. Can be formed. In the drawing, the shapes of the gates G3 and G13 of the equalizing transistors MN3 to MN5 and MN13 to MN15 are H-shaped, but the shape is not limited thereto.

8 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a second embodiment of the present invention.

Referring to FIG. 8, in the semiconductor memory device according to the second embodiment of the present invention, the positions of the equalizer regions 230_1 and 230_2 and the N-type sense amplifier regions 220_1 and 220_2 are different from those of the first embodiment.

That is, in the first sense circuit region 200_1, the P-type first sense amplifier 110_1, the N-type second sense amplifier 120_1, and the first, in order, from the first side S1 to the second side S2. The first equalizer 130_1 and the first column selector 140_1 are disposed, and in the second sense circuit region 200_2, in order from the first side S1 to the second side S2, the second column. The selector 140_2, the second equalizer 130_2, the N-type third sense amplifier 120_2, and the P-type fourth sense amplifier 110_2 are disposed.

Even in such a case, since the first and second column selectors 240_1 and 240_2 are formed immediately adjacent to each other, the line loading mismatch can be reduced.

9 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a third embodiment of the present invention.

Referring to FIG. 9, in the semiconductor memory device according to the third exemplary embodiment, the positions of the equalizer regions 230_1 and 230_2 and the P-type sense amplifier regions 210_1 and 210_2 are different from those of the first embodiment.

That is, in the first sense circuit region 200_1, the first equalizer 130_1, the P-type first sense amplifier 110_1, and the N-type second in order from the first side S1 to the second side S2. The sense amplifier 120_1 and the first column selector 140_1 are disposed, and in the second sense circuit region 200_2, in order from the first side S1 to the second side S2, the second column selector ( 140_2), the N-type third sense amplifier 120_2, the P-type fourth sense amplifier 110_2, and the second equalizer 130_2 are disposed.

FIG. 10 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a fourth embodiment of the present invention.

Referring to FIG. 10, in the semiconductor memory device according to the fourth exemplary embodiment, the positions of the N-type sense amplifier regions 220_1 and 220_2 and the column selectors 240_1 and 240_2 are different from those of the first embodiment.

That is, in the first sense circuit region 200_1, the P-type first sense amplifier 110_1, the first equalizer 130_1, and the first column selector are sequentially arranged from the first side S1 to the second side S2. 140_1, an N-type second sense amplifier 120_1 is disposed, and in the second sense circuit region 200_2, an N-type third sense amplifier in order from the first side S1 to the second side S2. 120_2, the second column selector 140_2, the second equalizer 130_2, and the P-type fourth sense amplifier 110_2 are disposed.

Even in this case, the P-type first sense amplifier 110_1 is separated from the first column selector 140_1 and the N-type second sense amplifier 120_1, and the P-type fourth sense amplifier 110_2 is connected to the second column selector. 140_2, since the N-type third sense amplifier 120_2 is separated, the WPE can be reduced.

FIG. 11 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a fifth embodiment of the present invention.

Referring to FIG. 11, the semiconductor memory device according to the fifth embodiment of the present invention is different from the first embodiment in that the P-type sense amplifier regions 210_1 and 210_2 are disposed in the middle of the sense circuit region. Here, since the P-type sense amplifier regions 210_1 and 210_2 are immediately adjacent to each other, the two P-type sense amplifiers 110_1 and 110_2 may be formed in the same well.

That is, in the first sense circuit region 200_1, the first column selector 140_1, the N-type second sense amplifier 120_1, and the first equalizer in order from the first side S1 to the second side S2. 130_1 and the P-type first sense amplifier 110_1 are disposed in the second sense circuit region 200_2 in order from the first side S1 to the second side S2 in order. The amplifier 110_2, the second equalizer 130_2, the N-type third sense amplifier 120_2, and the second column selector 140_2 are disposed.

12 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a sixth embodiment of the present invention.

12, the semiconductor memory device according to the sixth embodiment of the present invention is different from the first embodiment in that the P-type sense amplifier regions 210_1 and 210_2 are disposed in the middle of the sense circuit region. Here, since the P-type sense amplifier regions 210_1 and 210_2 are immediately adjacent to each other, the two P-type sense amplifiers 110_1 and 110_2 may be formed in the same well.

That is, in the first sense circuit region 200_1, the N-type second sense amplifier 120_1, the first column selector 140_1, and the first equalizer are sequentially disposed from the first side S1 to the second side S2. 130_1 and the P-type first sense amplifier 110_1 are disposed, and the P-type fourth sense amplifier is sequentially disposed from the first side S1 to the second side S2 in the second sense circuit region 200_2. 110_2, the second equalizer 130_2, the second column selector 140_2, and the N-type third sense amplifier 120_2 are disposed.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

3 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a first embodiment of the present invention.

4A and 4B are views for explaining the effect of the sense circuit used in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 illustrates only active and wells in a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 illustrates only active, wells and gates in a sense circuit used in the semiconductor memory device according to the first embodiment of the present invention.

7A to 7C are detailed views of portions of FIG. 6, respectively.

10 is a conceptual layout view illustrating a sense circuit used in a semiconductor memory device according to a fourth embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

10_1 and 10_2: first and second memory cell arrays

20_1 to 20_4: first to fourth sense circuit regions

110_1 ~ 110_4: P type sense amplifier 120_1 ~ 120_4: N type sense amplifier

130_1 ~ 130_4: Equalizer 140_1 ~ 140_4: Column selector

Claims

A substrate in which a first cell array region, a first sense circuit region, a second sense circuit region, and a second cell array region are defined in order from a first side to a second side;

First and second bit lines coupled to a plurality of memory cells formed in the first cell array region;

First and second complementary bit lines coupled to a plurality of memory cells formed in the second cell array region;

A first column selector formed in the first sense circuitry region and coupled with the first bit line and the first complementary bit line; And

A second column selector formed in said second sense circuit region and coupled with said second bit line and said second complementary bit line,

And the first column selector and the second column selector are immediately adjacent to each other.

The method of claim 1,

The first complementary bit line extends across the second sense circuit region to the first sense circuit region,

And the second bit line extends across the first sense circuit region to the second sense circuit region.

The method of claim 1,

And a first conductivity type first sense amplifier and a second conductivity type second sense amplifier formed in the first sense circuit region,

And a second conductivity type third sense amplifier and a first conductivity type fourth sense amplifier formed in the second sense circuit region.

3. The method of claim 2,

The first column selector includes a first column select transistor coupled between the first bit line and the first input / output line, and a second column select transistor coupled between the first complementary bit line and the first complementary input / output line. Including,

The first conductive first sense amplifier includes a first sensing transistor coupled with the first bit line, and a second sensing transistor coupled with the first complementary bit line.

And a distance between the first column select transistor and the first sensing transistor and a distance between the second column select transistor and the second sensing transistor are substantially the same.

The method of claim 1,

A first conductive type first sense amplifier, a first equalizer, a second conductive type second sense amplifier, and the first column selector are disposed in the first sense circuit region in order from a first side to a second side,

A semiconductor in which the second column selector, the second conductivity type third sense amplifier, the second equalizer, and the first conductivity type fourth sense amplifier are disposed in the second sense circuit region in order from the first side to the second side. Memory device.

The method of claim 1,

A first conductive type first sense amplifier, a second conductive type second sense amplifier, a first equalizer, and the first column selector are disposed in the first sense circuit region in order from a first side to a second side,

A semiconductor in which the second column selector, the second equalizer, the second conductive third sense amplifier, and the first conductive fourth sense amplifier are disposed in the second sense circuit region in order from the first side to the second side. Memory device.

The method of claim 1,

A first equalizer, a first conductivity type first sense amplifier, a second conductivity type second sense amplifier, and the first column selector are disposed in the first sense circuit region in order from a first side to a second side,

In the second sense circuit region, the second column selector, the second conductivity type third sense amplifier, the first conductivity type fourth sense amplifier, and the second equalizer are disposed in order from the first side to the second side. Semiconductor memory device.

The method according to any one of claims 4 to 6,

Wherein the first conductivity type is a P type and the second conductivity type is an N type.

A first bit line and a first complementary bit line arranged in an open bitline type;

A second bit line and a second complementary bit line arranged in an open bit line type;

A first conductive type first sense amplifier, a first equalizer, a second conductive type second sense amplifier, a first column selector, a second column selector, and a second conductive type third arranged in order from the first side to the second side. A sense amplifier, a second equalizer, and a first conductive type fourth sense amplifier,

The first conductive first sense amplifier, the first equalizer, the second conductive second sense amplifier, and the first column selector are connected to the first bit line and the first complementary bit line,

The second column selector, the second conductive third sense amplifier, the second equalizer, and the first conductive fourth sense amplifier are connected to the second bit line and the second complementary bit line. .

The semiconductor memory device of claim 9, wherein the first conductivity type is a P type and the second conductivity type is an N type.