KR20110125417A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for fabricating the same are provided to improve the electrical characteristic of transistors by increase a process margin for forming a pattern. CONSTITUTION: In a semiconductor device and a method for fabricating the same, a plurality of sense amplifiers are composed of a plurality of transistors. A plurality of transistors is classified into classification. A plurality of transistors is formed on one active areas(310 1,310 2). Various kinds of transistors include a plurality of NMOS transistors and a plurality of PMOS transistors. A plurality of sense amplifiers are included in a core region. Each transistor comprises a gate pattern(320) of a ring type. A plurality of channel regions are formed in the lower part of the gate pattern.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a transistor capable of operating stably while increasing the degree of integration by reducing the area occupied by a semiconductor device in a highly integrated semiconductor device and a method of manufacturing a semiconductor device including the same.

Dynamic random access memory (DRAM) devices in a semiconductor memory device sense and amplify data stored in a memory cell using a sense amplifier. The sense amplifier is connected to the bit line of the memory cell to determine memory cell data by comparing a bit level precharge voltage with a voltage level charged and shared by the bit line. The sense amplifier block may be connected to one memory block including a plurality of unit cells to sense data output from the unit cells in the memory block, or may be connected to two memory blocks and optionally one of the memory blocks. Data output from the unit cells in the cell may be sensed. Such a sense amplifier is composed of a plurality of transistors.

A transistor is composed of three regions: a gate, a source, and a drain. Charge occurs between a source and a drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region. When conventional transistors are made in a semiconductor substrate, a gate is formed on the semiconductor substrate and doped with impurities on both sides of the gate to form a source and a drain. As the data storage capacity of semiconductor memory devices increases and the degree of integration increases, the size of each unit cell is required to be made smaller and smaller.

1 is a circuit diagram illustrating a sense amplifier having a latch structure included in a general semiconductor device.

Referring to FIG. 1, a semiconductor device includes a sense amplifier 110 including four transistors P1, P2, N1, and N2 in bit lines BL and / BL connected to a plurality of unit cells. Similarly, the neighboring sense amplifier 120 also includes four transistors P3, P4, N3, and N4 connected to the bit lines BL and / BL. A cell array composed of a plurality of unit cells includes a plurality of paired bit lines, and a sense amplifier is connected to each bit line.

2 is a block diagram for explaining a layout of a sense amplifier formed on a semiconductor substrate.

Referring to FIG. 2, a plurality of active regions 210 are formed in a core region in which a sense amplifier is formed in a semiconductor device, similarly to a cell region, and two gate patterns 220 are formed on each active region. Here, the active region 210 is formed in a form similar to the active region formed in the cell region, and the gate pattern 220 is formed in a form similar to a word line formed in the cell region in a line pattern.

Two transistors formed in one active region 210 are transistors of the same kind. Here, both transistors formed in one active region 210 are both NNMOS or PMOS.

In order to implement the latch type sense amplifier 120 described with reference to FIG. 1, a source / drain region (a source / drain shared by two transistors) positioned between two gate patterns 220 formed on the active region 210 may be used. Drain region) connects the power supply voltage Vdd or ground voltage Vss, and the source / drain regions located on the other side of the two gate patterns 220 are connected to the source / drain regions of different types of transistors. do. In addition, the bit lines BL and / BL are connected to the gate pattern 220.

When the active region 210 in which the transistor constituting the sense amplifier 120 is formed and the gate pattern 220 included in the transistor are formed to have the same size as that of the active region and the word line of the cell region, the integration degree may be increased. It can be raised to the maximum. However, as the size of the minimum line width defined by the design rule is increased in order to increase the degree of integration, the size of the transistors constituting the sense amplifier 120 may be smaller, which may cause a problem due to a narrow width effect. In particular, since a high voltage is applied to the sense amplifier 120 unlike a unit cell included in a cell region, a change in a threshold voltage due to a magnetic field generated in a transistor is likely to occur.

In addition, as the size of the minimum line width of the transistor formed in the core region is reduced, it is difficult to form a uniform pattern, and thus, adjacent transistors may have different electrical characteristics. In particular, since the core region has a smaller process margin than the cell region, it is not easy to form a pattern constituting the transistor with the same size as the cell region. In the sense amplifier 120 in which transistors of the same type are connected and operated in pairs, it is difficult to accurately sense and amplify data transmitted through the bit lines BL and / BL when the electrical characteristics of adjacent transistors are different. As a result, a defect occurs in the semiconductor device.

In order to solve the above problems, the present invention classifies a plurality of transistors constituting a plurality of sense amplifiers according to the type of transistor and implements them on the same active region according to the type, thereby increasing the degree of integration of the semiconductor device as compared with the related art. Semiconductor devices that can improve the electrical properties of transistors, improve the dopant fluctuation effect and the narrow width effect while increasing the area of the active region and increasing the process margin for pattern formation while maintaining or maintaining the same. And a method for producing the same.

The present invention provides a semiconductor device comprising a plurality of sense amplifiers composed of a plurality of transistors, wherein the plurality of transistors classified by type are formed on one active region.

The plurality of transistors may include a plurality of NMOS transistors and a plurality of PMOS transistors, and each of the plurality of NMOS transistors and the plurality of PMOS transistors may be arranged in two rows or four rows in the one active region. It is characterized by.

The plurality of sense amplifiers may be included in the core region.

Each of the plurality of transistors may include a gate pattern having a ring shape, and a plurality of channel regions may be formed under the gate pattern.

The contact formed on the inner side of the ring-shaped gate pattern and the contact formed on the outer side of the gate pattern may be positioned to minimize the gap therebetween.

The plurality of transistors may share one of a source / drain region, and a power supply voltage or a ground voltage may be applied to the shared source / drain region.

The plurality of transistors may share contacts formed in the shared source / drain regions.

According to the present invention, in forming a plurality of transistors constituting the sense amplifier, there is an advantage that the electrical characteristics of the transistors can be improved and the electrical characteristics of neighboring transistors can be kept the same.

In addition, the present invention forms a plurality of transistors constituting a sense amplifier that can be classified according to the type of transistor in a common active region, thereby increasing the integration degree compared to the conventional method of forming two transistors in an island-type active region. It can increase.

Furthermore, the present invention has an advantage in that the area of the entire active region is increased as a plurality of transistors are formed in a common active region having a large size, and as a result, a dopant fluctuation effect occurred due to a decrease in design rules. In addition to preventing the effect, there is an advantage of improving the narrow width effect (Narrow width Effect).

1 is a circuit diagram illustrating a sense amplifier having a latch structure included in a general semiconductor device.
2 is a block diagram for explaining a layout of a sense amplifier formed on a semiconductor substrate.
3 is a block diagram illustrating a layout of a sense amplifier in a semiconductor device according to an embodiment of the present invention.
4 is a block diagram illustrating a layout of a sense amplifier in a semiconductor device according to another embodiment of the present invention.

According to the present invention, in the case of a circuit in which a plurality of transistors among the various components included in the semiconductor device share the source / drain region in common, the semiconductor device may not only increase the degree of integration of the semiconductor device but also prevent the electrical characteristics of the transistors from being changed. A structure for improving the operational stability of the device is presented. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a layout of a sense amplifier in a semiconductor device according to an embodiment of the present invention.

As shown, two active regions 310_1 and 310_2 are formed in a core region in which a sense amplifier connected to a bit line of a cell region is formed. In this case, the active areas 310_1 and 310_2 have a very large area compared to the active areas for forming the unit cells in the cell area. The number of active regions 310_1 and 310_2 formed in the core region corresponds to the type of transistor included in the core region. The latch type sense amplifier described in FIG. 1 includes PMOS and NMOS transistors, that is, two kinds of transistors. Accordingly, the core region includes two active regions 310_1 and 310_2 in which a plurality of PMOS transistors and a plurality of NMOS transistors are formed.

A ring pattern gate pattern 320 is formed on the two active regions 310_1 and 310_2. The gate patterns 320 are arranged in two rows, because the gate patterns 320 include two NMOS and PMOS transistors of the sense amplifier. The ring pattern gate pattern 320 has a quadrangular shape in plan view, which facilitates the formation of a pattern, and may be manufactured in various shapes according to a process method. Here, the transistor formed on the active region 310_1 is shared outside the gate pattern 320, the inner first source / drain region 312_1 surrounded by the gate pattern 320, and the gate pattern 320. And a second source / drain region 314_1.

Contacts 332_1 are formed in the second source / drain region 314_1 on the active region 310_1 where the NMOS transistor is formed to supply the ground voltage Vss. Meanwhile, a contact 334_1 is formed in the first source / drain region 312_1 to connect with the PMOS transistor. On the other hand, a contact 332_2 is formed in the second source / drain region 314_2 on another active region 310_2 in which the PMOS transistor is formed, and supplies a power source voltage Vdd, and the first source / drain region ( A contact 334_2 is formed at 312_2 to connect with the first source / drain region 312_1 of the NMOS transistor.

Here, a contact (ie, a source included in one transistor) paired to form a transistor among contacts formed on the first source / drain regions 312_1 and 312_2 and the second source / drain regions 314_1 and 314_2. The contact 332_1 and 334_1 connected to the drain are formed at a position where the distance can be minimized. The positions of the contacts 334_1 and 334_2 formed in the second source / drain regions 314_1 and 314_2 may be considered to be substantially fixed. However, since contacts may be formed in various places in the first source / drain regions 312_1 and 312_2, the first source / drain regions 312_1 and 312_2 may have a plurality of second source / drain regions 314_1, depending on the position of the contact. The distance between the contact formed at 314_2 and the channel length of the transistor are different. This is because the operation speed of the transistor is affected.

Compared to the prior art, which typically forms one or two transistors in one active region, in the present invention, a plurality of transistors are formed in an active region having a large area according to the same type. As a result, in the core region, a sense amplifier composed of a plurality of transistors includes a sense amplifier corresponding to the number of bit lines, so that the number of active regions is reduced and an element isolation region for separating each active region is unnecessary. This greatly reduces the total area occupied by sense amplifiers. In addition, as a plurality of transistors are formed in a common active region having a large size, the area of the entire active region is increased, and as a result, the dopant fluctuation effect generated as the design rule is reduced is reduced. Not only can it be prevented, but there is an advantage of improving the narrow width effect (Narrow width Effect).

4 is a block diagram illustrating a layout of a sense amplifier in a semiconductor device according to another embodiment of the present invention.

As shown in FIG. 4, two or more gate patterns 420 are formed on one active region 410. In the case of the sense amplifier formed in the core region, as the gate patterns 420 are arranged in the column direction, it becomes difficult to configure the latch by connecting each transistor to each other. As the number of transistors included in one active region 410 increases, the area occupied by the semiconductor device may be reduced, thereby improving integration. However, as the number of transistors included in one active region 410 increases, it becomes difficult to connect the source / drain regions of the transistors with each other. In case of connecting through contact and wiring, it is necessary to use a step because wiring crosses each other. As the number of wiring increases, the complexity of the process increases and productivity may decrease.

As described above, according to an embodiment of the present invention, a plurality of transistors constituting the sense amplifier included in the core region are classified according to the type of transistor to form at least two or four rows or more transistors in one active region. Increasing the degree of integration of semiconductor devices, improving the electrical characteristics of transistors, and maintaining the electrical characteristics of neighboring transistors are the same.

In addition, in the present invention, a plurality of transistors can be formed in a common active region having a large size, thereby preventing a dopant fluctuation effect that can occur as the design rule becomes smaller, as well as narrow. The narrow width effect can be improved.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

Claims (7)

A plurality of sense amplifiers comprising a plurality of transistors,
The plurality of transistors classified by type are formed on one active region. The method of claim 1,
The plurality of transistors include a plurality of NMOS transistors and a plurality of PMOS transistors, each of the plurality of NMOS transistors and the plurality of PMOS transistors are arranged in two rows or four rows in the one active region. Semiconductor device. The method of claim 1,
And the plurality of sense amplifiers are included in a core region. The method of claim 1,
Each of the plurality of transistors includes a ring-shaped gate pattern, and a plurality of channel regions are formed under the gate pattern. The method of claim 5, wherein
And the contacts formed on the inside of the ring-shaped gate pattern and the contacts formed on the outer side of the gate pattern are arranged to have a minimum gap therebetween. The method of claim 1,
The plurality of transistors share one of a source / drain region, and a power supply voltage or a ground voltage is applied to the shared source / drain region. The method of claim 1,
And the plurality of transistors share contacts formed in the shared source / drain regions with each other.

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