KR20110013159A - Method for manufacturing thin film transistor array substrate - Google Patents

Abstract

PURPOSE: A thin film transistor array substrate manufacturing method is provided to reduce the point defect generating during the lift off process by not using the lift off process with high difficulty used in 3 mask process. CONSTITUTION: A gate line(20b) and a dataline(30d) intersect each other on a substrate. A pixel electrode(20g) and a common electrode(20f) are formed in order to form the lateral electric field on the pixel region. The common line is connected to a common electrode(20f). A storage capacitor(Cst) is formed on the overlap portion of the gate line and the storage capacitor upper electrode(30c).

Description

Method for manufacturing thin film transistor array substrate

The present invention relates to a method of manufacturing a thin film transistor array substrate used in a liquid crystal display device.

Usually, a liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. The liquid crystal display is mainly formed by bonding a color filter substrate on which a color filter array is formed and a thin film transistor array substrate on which a thin film transistor array is formed, with the liquid crystal interposed therebetween.

The thin film transistor array substrate includes a thin film transistor and a pixel electrode formed in each cell region defined by the intersection of the gate line and the data line on the substrate. The thin film transistor supplies the data signal from the data line to the pixel electrode in response to the gate signal from the gate line. The pixel electrode formed of the transparent conductive layer supplies the data signal from the TFT to drive the liquid crystal. The liquid crystal is rotated according to the electric field formed by the data signal of the pixel electrode and the common voltage of the common electrode, thereby adjusting grayscale. In this case, the common electrode is supplied with a common voltage which is a reference when driving the liquid crystal, and may be formed on any one of the thin film transistor substrate and the color filter substrate.

The thin film transistor array substrate of the liquid crystal panel is formed through a plurality of mask processes. One mask process includes a plurality of processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a strip process, an inspection process, and the like.

However, as a number of mask processes are required, the manufacturing process is complicated, which is a major reason for the increase in manufacturing cost of the liquid crystal panel. Accordingly, the thin film transistor array substrate is developing in a direction of reducing the number of mask processes in a five mask process. For example, by using a diffraction exposure mask, the number of processes can be reduced by a four mask process.

In order to complete the pattern of the thin film transistor array substrate using four mask processes as described above, a double-stage photoresist pattern is formed by using a diffraction exposure mask, and then the patterned metal layer and the semiconductor layer are simultaneously patterned using the photoresist pattern. To form a source / drain electrode and a semiconductor layer.

In this case, a semiconductor layer tail protruding outside the edge of the source / drain electrode is formed in the semiconductor layer. The semiconductor layer tail 14c protrudes not only from the source / drain electrodes but also under the data line 15c as shown in FIG. 1, and the performance of the device is degraded by the semiconductor layer tail 14c.

First, due to the semiconductor layer tail, wavy noise occurs when the backlight is turned on or off.

Specifically, the conductive layer is changed in accordance with the presence or absence of light, the conductive layer is conductive when the light is received, and the conductive layer is lost like the insulating film. Therefore, when the backlight is turned off, parasitic capacitance is generated between the pixel electrode 17 and the data line 15c formed by interposing the data line 15c and the passivation layer 16 because the semiconductor layer has no conductivity. When the backlight is turned on, conductivity occurs in the semiconductor layer 14b that is closer to the pixel electrode 17 than the data line 15c, so that parasitic capacitance is generated between the semiconductor layer 14b and the pixel electrode 17. do. At this time, since the size of the data line and the semiconductor layer are different from each other by the width of the semiconductor layer tail 14c, parasitic capacitances generated between the pixel electrodes are also different from each other. That is, parasitic capacitance generated between the semiconductor layer and the pixel electrode having a larger size than the data wirings is further increased. As described above, since parasitic capacitances vary depending on backlight on / off, wavy noise occurs in an image.

Second, the pixel electrode 17 is formed to be spaced apart from the data line 15c and the semiconductor layer 14b by a predetermined distance, and the data line 15c and the pixel electrode 17 are further spaced apart by the width of the semiconductor layer tail 14c. Since the opening area of the device is reduced. For reference, since the black matrix introduced to block light leakage must be formed as large as the width of the semiconductor layer tail, the aperture ratio of the device is lowered.

Third, the off current of the device is increased due to the photo current caused by the semiconductor layer tail.

An object of the present invention for solving the above problems is to simplify the process by reducing the number of masks more than the four mask process used in the method of manufacturing a thin film transistor array substrate thin film transistor to reduce the cost and improve the yield The present invention provides a method for manufacturing an array substrate.

In addition, an object of the present invention is to provide a method of manufacturing a thin film transistor array substrate to reduce the wafer noise (wavy noise) and to further secure the opening area of the device by reducing the semiconductor layer tail generated in the four mask process.

According to an aspect of the present invention, a method of manufacturing a thin film transistor array substrate includes performing a first mask process to form a gate electrode, a storage capacitor lower pattern, a pixel electrode pattern, a common electrode pattern, and a gate pad pattern on a substrate. And forming a gate insulating pattern and a first semiconductor pattern on the substrate on which the gate electrode, the storage capacitor lower pattern, the pixel electrode pattern, the common electrode pattern, and the gate pad pattern are formed by performing a second mask process. And forming a second semiconductor pattern, a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line on a substrate on which the gate insulating pattern and the first semiconductor pattern are formed by performing a third mask process.

The process of forming the gate electrode, the storage capacitor lower pattern, the pixel electrode pattern, the common electrode pattern, and the gate pad pattern on the substrate by performing the first mask process may include a first metal layer, a second metal layer, and a third pattern on the substrate. Sequentially forming a metal layer and a photoresist, performing a photolithography process using the first mask on the photoresist, and forming a first photoresist pattern, and using the first photoresist pattern as an etching mask. And wet etching the first metal layer, the second metal layer, and the third metal layer.

The first metal layer uses MoTi, the second metal layer uses ITO, and the third metal layer uses Cu.

The forming of the gate insulating pattern and the first semiconductor pattern on the substrate by performing the second mask process may include forming a gate insulating layer, a semiconductor layer, and a photoresist on the substrate, and forming the second mask on the photoresist. Forming a second photoresist pattern by performing a photolithography process, etching and patterning the gate insulating layer and the semiconductor layer using the second photoresist pattern as an etch mask, and ashing the second photoresist pattern Forming a third photoresist pattern, and etching and patterning the patterned gate insulating layer and the semiconductor layer using the third photoresist pattern as an etch mask to form the gate insulating pattern and the first semiconductor pattern. do.

The second mask is a mask having three different transmittances.

The forming of the second semiconductor pattern, the source electrode, the drain electrode, the storage capacitor upper electrode, and the data line by performing the third mask process may include forming a fourth metal layer, a fifth metal layer, and a photoresist on the substrate. And forming a fourth photoresist pattern by performing a photolithography process using the third mask on the photoresist, and using the fourth photoresist pattern as an etch mask, the fifth metal layer and the fourth metal layer. Wet etching to form a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line; and etching the first semiconductor pattern using the fourth photoresist pattern as an etch mask to form the second semiconductor pattern. It includes more.

The fourth metal layer uses Mo, and the fifth metal layer uses Cu.

The wet etching of the fifth metal layer and the fourth metal layer using the fourth photoresist pattern as an etch mask may include the third metal layer which is the uppermost layer of each of the gate pad pattern, the common electrode pattern, and the pixel electrode pattern during the wet etching process. The method may further include forming a gate pad, a common electrode, and a pixel electrode by removing the respective electrodes.

After performing the third mask process to form a second semiconductor pattern, a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line on the substrate, a passivation layer on the substrate on which the second semiconductor pattern is formed. And forming a contact hole exposing the gate pad by performing a dry etching process using plasma on the passivation layer on which the gate pad is formed.

In the method of manufacturing a thin film transistor array substrate according to the present invention, the formation of the semiconductor layer in the data wiring formation process is omitted by performing a three-mask process of a new concept, and the formation of the semiconductor layer tail protruding outside the existing data wiring is performed. It becomes possible to prevent it. As a result, there is an effect of preventing a wavy noise generated when the backlight (B / L) is turned on or off.

In addition, in the method of manufacturing the thin film transistor array substrate according to the present invention, since the formation of the semiconductor layer is omitted below the data line, the opening ratio of the semiconductor layer tail projecting outside the existing data line can be prevented from being lowered. . Therefore, it is possible to reduce the size of the black matrix, which acts as a light leakage prevention.

In addition, the method of manufacturing the thin film transistor array substrate according to the present invention has an effect of preventing the off current of the device from being increased due to the photo current caused by the semiconductor layer tail.

In addition, the manufacturing method of the thin film transistor array substrate according to the present invention does not use a high-lift lift off process used in the conventional three mask process, it is possible to reduce the point defects generated during the lift off process It works.

In addition, the manufacturing method of the thin film transistor array substrate according to the present invention does not use expensive multi-tone masks having four or more different transmittances used in the conventional three mask process, thereby increasing the manufacturing cost. There is an effect that can be prevented.

In addition, since only the passivation layer 31 on the metal layer may be selectively etched using a laser of a specific wavelength, a contact hole exposing the gate pad 20h may be formed without a mask process. In comparison with the above, the tact time can be reduced. In addition, since direct contact is possible at the time of contacting the gate pad 21h, the afterimage resulting from the resistance of the pixel electrode and the decrease in response speed can be improved.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments.

2 is a plan view showing a thin film transistor array substrate according to an embodiment of the present invention, Figure 3 is a thin film transistor substrate shown in Figure 2 I-I ', II-II', III-III ', IV-IV A cross-sectional view taken along the line ', V-V'.

The thin film transistor array substrate shown in FIGS. 2 and 3 includes a gate line 20b and a data line 30d formed to cross each other on the substrate 10, a thin film transistor T formed at each intersection thereof, and a cross structure thereof. A pixel electrode 20g and a common electrode 20f formed to form a horizontal electric field in the provided pixel region, and a common line 20i connected to the common electrode 20f are provided.

The thin film transistor substrate further includes a storage capacitor Cst formed at an overlapping portion of the gate line 20b and the storage capacitor upper electrode 30c, and a gate pad 20h connected to the gate line 20b. do.

Although not shown in the drawing, a data pad (not shown) connected to the data line 30d and a common pad (not shown) connected to the common line 20i are further provided.

The gate line 20b for supplying the gate signal and the data line 30d for supplying the data signal are formed in a cross structure to define a pixel area. Here, the gate line 20b is formed in a structure in which the first metal layer 12a, the second metal layer 14a, and the third metal layer 16a are stacked, and the data line 30d is a patterned fourth metal layer 26b. And the fifth metal layer 28b is laminated.

The common line 20i and the common electrode 20f supply a reference voltage for driving the liquid crystal. The common line 20i includes a first common line formed in parallel with the data line 30d in the display area and a second common line formed in parallel with the gate line 20b in the display area. The common electrode 20f extends from the second common line toward the pixel area in a finger shape. The common line 20i and the common electrode 20f have a structure in which the first metal layer 12a and the second metal layer 14a are stacked.

The thin film transistor T keeps the pixel signal of the data line 30d charged and held in the pixel electrode 20g in response to the gate signal of the gate line 20b. To this end, the thin film transistor T includes a gate electrode 20a connected to the gate line 20b, a source electrode 30a connected to the data line 30d, and a drain electrode 30b facing the source electrode 30a. And a semiconductor pattern 24d for overlapping the gate electrode 20b with the gate insulating pattern 22b to form a channel between the source electrode 30a and the drain electrode 30b. In addition, the thin film transistor T further includes an ohmic contact layer (not shown) formed on the semiconductor pattern 24d except for the channel for ohmic contact with the source electrode 30a and the drain electrode 30b.

The source electrode 30a and the drain electrode 30b are formed in a stacked structure of the patterned fourth metal layer 26b and the fifth metal layer 28b.

The pixel electrode 20g forms a horizontal electric field with the common electrode 20f in the pixel area, and contacts the upper electrode 30c of the storage capacitor formed integrally with the drain electrode 30b of the thin film transistor T, and the data It is formed parallel to the line 30d.

As a result, a horizontal electric field is formed between the pixel electrode 20g supplied with the pixel signal through the thin film transistor T and the common electrode 20f supplied with the reference voltage through the common line 20i. The horizontal electric field causes liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate to rotate by dielectric anisotropy. In addition, light transmittance through the pixel region is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The storage capacitor includes a portion of the front gate line 20b serving as the lower electrode of the storage capacitor with the gate insulating pattern 22b interposed therebetween, and the storage capacitor upper electrode 30c. In this case, the storage capacitor upper electrode 30c has a structure in which the fourth metal layer 26b and the fifth metal layer 28b are stacked, and protrude toward the pixel electrode 20g to be connected to the pixel electrode 20g. This storage capacitor allows the pixel signal charged in the pixel electrode 20g to be stably maintained until the next pixel signal is charged.

The gate line 20b is connected to a gate driver (not shown) through the gate pad 20h, and the data line 30d is connected to a data driver (not shown) through the data pad (not shown).

In this case, the gate pad 20h and the data pad (not shown) are exposed through the contact hole 32 formed in the passivation layer 31.

Such a thin film transistor array substrate according to the present invention can prevent the formation of the semiconductor layer tail by applying a three-mask process.

Looking at the manufacturing method of such a thin film transistor array substrate in detail as follows.

4A and 4B are a plan view and a cross-sectional view for explaining a first mask process in the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

As shown in FIGS. 4A and 4B, the gate electrode 20a, the storage capacitor lower pattern 20b, the pixel electrode pattern 20c, and the common electrode pattern 20d are formed on the substrate 10 through the first mask process. And a gate pad pattern 20e is formed.

The gate electrode 20a, the storage capacitor lower pattern 20b, the pixel electrode pattern 20c, the common electrode pattern 20d, and the gate pad pattern 20e may include a first metal layer 12a and a second metal layer 14a. And the third metal layer 16a is laminated, the first metal layer uses MoTi, the second metal layer uses a transparent conductive film such as ITO, and the third metal layer uses Cu.

The gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20d, the pixel electrode pattern 20c, and the gate pad pattern 20e may be formed on the substrate 10. , Sequentially forming a third metal layer and a photoresist, and performing a photolithography process using a first mask on the photoresist to form a first photoresist pattern (not shown), and using the etching mask as a first metal layer and a second It is formed by wet etching the metal layer and the third metal layer.

In addition, the storage capacitor lower pattern 20b is part of the front gate line 20b.

The strip process is performed on the substrate 10 on which the gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20d, the pixel electrode pattern 20c, and the gate pad pattern 20e have been formed. The first photoresist pattern (not shown) is removed.

5A and 5B are plan views and cross-sectional views illustrating a second mask process in a method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention, and FIGS. 6A to 6D illustrate the second mask process in detail. These are cross-sectional views.

5A and 5B, the substrate 10 having the gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20c, the pixel electrode pattern 20d, and the gate pad pattern 20e is formed. ), A gate insulating pattern 22b and a second semiconductor pattern 24c are formed through a second mask process.

Specifically, as shown in FIG. 6A, a substrate on which the gate electrode 20a, the storage capacitor lower pattern 20b, the common electrode pattern 20d, the pixel electrode pattern 20c, and the gate pad pattern 20e are formed. After sequentially forming the gate insulating film 22a and the semiconductor layer 24a on the layer 10, the second photoresist pattern 100a is formed on the semiconductor layer 24a.

The second photoresist pattern 100a is formed by forming a photoresist on the semiconductor layer 24a and performing a photolithography process using a second mask on the photoresist.

In this case, the mask uses a mask having three different transmittances, including a transmissive region for transmitting light, a transflective region for transmitting and blocking a portion of the light, and a blocking region for blocking the light. In this case, the semi-transmissive region is a region having a higher transmittance than the blocking region, and the thickness of the photoresist pattern in the semi-transmissive region formed through the photolithography process is lower than the thickness of the photoresist pattern in the blocking region.

Accordingly, the blocking region is disposed in a region corresponding to the gate electrode of the region TFT in which the thin film transistor is formed, and the transflective region is a region in which the thin film transistor is formed except for the region in which the blocking region is disposed and the storage capacitor. The transmissive region is disposed in the pixel region PXL, the region D-line in which the data line is formed, and the region G-Pad in which the gate pad is formed.

As shown in FIG. 6B, the semiconductor layer 24a and the gate insulating layer 22a are etched using the second photoresist pattern 100a formed on the substrate 10 as an etch mask to form the first semiconductor pattern 24b and the gate. The insulating pattern 22b is formed.

As illustrated in FIG. 6C, an ashing process may be performed on the substrate 10 on which the second photoresist pattern 100a, the first semiconductor pattern 24b, and the gate insulation pattern 22b are formed to form a third photoresist pattern ( 100b), and the second semiconductor pattern 24c is formed by dry etching the first semiconductor pattern 24b using the third photoresist pattern 100b as an etch mask.

As shown in FIG. 6D, the gate insulating pattern 22b and the gate insulating pattern 22b and the third photoresist pattern 100b are removed by performing a strip process on the substrate 10 on which the second semiconductor pattern 24c is formed. The process of forming the second semiconductor pattern 24c is completed.

7A and 7B are plan views and cross-sectional views illustrating a third mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, and FIGS. 8A to 8D illustrate a third mask process in detail. Cross-sectional views.

As shown in FIGS. 7A and 7B, the third semiconductor pattern 24d and the source / drain may be formed through a third mask process on the substrate 10 on which the second semiconductor pattern 24c and the gate insulating pattern 22b are formed. The electrodes 30a and 30b, the storage capacitor upper electrode 30c, the data line 30d and the passivation layer 31 are formed.

Specifically, as shown in FIG. 8A, the fourth metal layer 26a and the fifth metal layer 28a are sequentially formed on the substrate 10 on which the second semiconductor pattern 24c is formed, and the fifth metal layer 28a is formed. ) A fourth photoresist pattern 100c is formed.

In this case, the fourth photoresist pattern 100c is formed by forming a photoresist and performing a photo process using a third mask on the photoresist.

At this time, Cu is used for the fifth metal layer 28a and Mo is used for the fourth metal layer 26a.

Subsequently, as shown in FIG. 8B, the fourth metal layer 26a and the fifth metal layer 28a are wet-etched using the fourth photoresist pattern 100c as an etch mask, so that the source / drain electrodes 30a and 30b and the storage are wet. The capacitor upper electrode 30c and the data line 30d are formed.

In this case, each of the source and drain electrodes 30a and 30b, the storage capacitor upper electrode 30c, and the data line 30d may have a stacked structure of a patterned fourth metal layer 26b and a fifth metal layer 28b. .

Meanwhile, in the wet etching process, the third metal layer 16a, which is the uppermost layer of each of the gate pad pattern 20e, the common electrode pattern 20c, and the pixel electrode pattern 20d stacked in the triple layer, is removed. This completes the formation of the gate pad 20h, the common electrode 20f, and the pixel electrode 20g.

Subsequently, as illustrated in FIG. 8C, a portion of the second semiconductor pattern 24c is dry-etched using the fourth photoresist pattern 100c as an etch mask to form a third semiconductor pattern 24d. In addition, the fourth photoresist pattern 100c is removed by performing a strip process on the substrate 10 on which the third semiconductor pattern 24d is formed.

Next, as shown in FIG. 8D, the protective film 31 is formed on the entire surface of the substrate 10 on which the third semiconductor pattern 24d is formed, and the dry film using plasma is formed on the protective film 31 on which the gate pad 20h is formed. This process is completed by forming a contact hole 32 exposing the gate pad 20h by performing an etching process.

A dry etching process using a plasma for removing the protective layer on the gate pad 20h will be described with reference to FIGS. 9A and 9B.

First, the dry etching process using plasma may include, for example, a beam type AP plasma method as shown in FIG. 9A and a bar type AP plasma method as shown in FIG. 9B. have.

The dry processes will be described with reference to the drawings.

As shown in FIG. 9A, the beam type atmospheric pressure plasma method selectively scans the plasma beam emitted from the plasma gun 170 to the gate pad 164. For this reason, the protective film 31 formed in the gate pad 20h shown in FIG. 8D is removed. Although not shown in the figure, the same process as above is performed for the data pad 162.

As shown in FIG. 9B, the bar type atmospheric pressure plasma method selectively scans the plasma beam emitted from the bar-shaped long plasma gun 172 to the gate pad 164. The protective film 31 formed in the gate pad 20h shown in FIG. 8D is removed. Although not shown in the figure, the same process as above is performed for the data pad 162. The plasma gun 172 may be formed in a bar shape by forming the plasma gun 170 illustrated in FIG. 9A in a long form or by connecting the plasma guns 170 in parallel.

As a result, a contact hole exposing the gate pad can be formed without a mask process.

In addition, a dry etching process using a laser having a specific wavelength to remove the protective layer 31 on the gate pad 20h will be described.

Only the passivation layer 31 on the metal layer may be selectively etched using the laser of the specific wavelength. That is, the contact hole may be exposed by selectively removing the protective layer 31 on the metal layer by scanning a laser of a specific wavelength. Therefore, since the contact hole exposing the gate pad 20h can be formed without the mask process, the process step can be reduced compared to the four mask process, thereby reducing the tact time.

The specific wavelength of the laser may be 532 nm. In addition, the degree of etching according to the thickness of the protective film 31 may be adjusted according to the wavelength of the laser, and the etching thickness may be adjusted according to the intensity of the laser. 10 is a view showing the degree of selective etching by a laser of 532 nm wavelength.

As a result, in the etching process using the laser having the specific wavelength as described above, since the direct contact is possible when the gate pad 21h contacts, the afterimage and the response speed due to the resistance of the pixel electrode can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a cross-sectional view showing a conventional data wiring and a semiconductor layer.

2 is a plan view illustrating a thin film transistor array substrate according to an embodiment of the present invention.

3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′, II-II ′, III-III ′, IV-IV ′, and V-V ′.

4A and 4B are a plan view and a cross-sectional view for explaining a first mask process in the method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention.

5A and 5B are plan views and cross-sectional views illustrating a second mask process in the method of manufacturing a thin film transistor array substrate according to an exemplary embodiment of the present invention.

6A to 6D are cross-sectional views for describing the second mask process in detail.

7A and 7B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor array substrate according to the embodiment of the present invention.

8A to 8D are cross-sectional views for describing the third mask process in detail.

9A and 9B illustrate a dry etching process using a plasma for removing a passivation layer on a gate pad.

10 is a view showing the degree of selectively etching the protective film on the metal layer by a laser of 532 nm wavelength.

Claims (10)

Performing a first mask process to form a gate electrode, a storage capacitor lower pattern, a pixel electrode pattern, a common electrode pattern, and a gate pad pattern on a substrate; Forming a gate insulating pattern and a first semiconductor pattern on a substrate on which the gate electrode, the storage capacitor lower pattern, the pixel electrode pattern, the common electrode pattern, and the gate pad pattern are formed by performing a second mask process; Forming a second semiconductor pattern, a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line on a substrate on which the gate insulating pattern and the first semiconductor pattern are formed by performing a third mask process; Manufacturing method. The method of claim 1, wherein the forming of the gate electrode, the storage capacitor lower pattern, the pixel electrode pattern, the common electrode pattern, and the gate pad pattern on the substrate is performed by performing the first mask process. Sequentially forming a first metal layer, a second metal layer, a third metal layer, and a photoresist on the substrate; Forming a first photoresist pattern by performing a photolithography process using the first mask on the photoresist; And wet-etching the first metal layer, the second metal layer, and the third metal layer using the first photoresist pattern as an etch mask. The method of claim 2, Wherein the first metal layer uses MoTi, the second metal layer uses ITO, and the third metal layer uses Cu. The method of claim 1, wherein forming the gate insulating pattern and the first semiconductor pattern on the substrate by performing the second mask process is performed. Forming a gate insulating film, a semiconductor layer, and a photoresist on the substrate; Forming a second photoresist pattern by performing a photolithography process using the second mask on the photoresist; Etching and patterning the gate insulating layer and the semiconductor layer using the second photoresist pattern as an etch mask; Ashing the second photoresist pattern to form a third photoresist pattern; And etching and patterning the patterned gate insulating layer and the semiconductor layer using the third photoresist pattern as an etch mask to form the gate insulating pattern and the first semiconductor pattern. The method of claim 4, wherein the second mask is a mask having three different transmittances. The method of claim 1, wherein the forming of the second semiconductor pattern, the source electrode, the drain electrode, the storage capacitor upper electrode, and the data line on the substrate is performed by performing the third mask process. Forming a fourth metal layer, a fifth metal layer, and a photoresist on the substrate; Forming a fourth photoresist pattern by performing a photolithography process using the third mask on the photoresist; Wet etching the fifth metal layer and the fourth metal layer by using the fourth photoresist pattern as an etch mask to form a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line; And etching the first semiconductor pattern using the fourth photoresist pattern as an etch mask to form the second semiconductor pattern. The method according to claim 6, The fourth metal layer uses Mo, and the fifth metal layer uses Cu, the method of manufacturing a thin film transistor array substrate. The method of claim 6, wherein the wet etching of the fifth metal layer and the fourth metal layer using the fourth photoresist pattern as an etching mask is performed. And removing the third metal layer, which is the uppermost layer of each of the gate pad pattern, the common electrode pattern, and the pixel electrode pattern, to form a gate pad, a common electrode, and a pixel electrode during the wet etching process. Method of manufacturing a thin film transistor array substrate. The method of claim 1, after performing the third mask process to form a second semiconductor pattern, a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line on the substrate. The method may further include forming a contact layer on the substrate on which the second semiconductor pattern is formed, and forming a contact hole exposing the gate pad by performing a dry etching process using plasma on the passivation layer on which the gate pad is formed. Method of manufacturing a substrate. The method of claim 1, after performing the third mask process to form a second semiconductor pattern, a source electrode, a drain electrode, a storage capacitor upper electrode, and a data line on the substrate. Forming a contact hole exposing the gate pad by forming a passivation layer on the substrate on which the second semiconductor pattern is formed and performing a dry etching process using a laser having a specific wavelength on the passivation layer on which the gate pad is formed; Method of manufacturing a thin film transistor array substrate.

Images