KR20110012570A - Device for protecting from electro static discharge - Google Patents

Abstract

PURPOSE: A device for protecting from electro static discharge is provided to reduce the peak voltage of electro static discharge by forming a plurality of discharge route in a plurality of discharge elements and arranging a resistor inside a discharge element. CONSTITUTION: An ESD protection chip(100) comprises an ESD protecting circuit body having a plurality of discharge routes and also includes a plurality of internal device. The ESD protection chip includes a plurality of discharge circuit devices on a semiconductor substrate. First and second discharge devices(111,112) are connected in parallel with a power contact internal device and a ground contact internal device. The first discharge device comprises a first diode(D1), a second diode(D2), and a first resistor(R1). The second discharge device comprises sixth and seventh diodes(D6,D7) and a second resistor(R2).

Description

Electrostatic Discharge Protection Device {DEVICE FOR PROTECTING FROM ELECTRO STATIC DISCHARGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrostatic discharge protection device, and more particularly, to an electrostatic discharge protection device capable of reducing an electrostatic discharge (ESD) peak voltage.

In general, an electrostatic discharge protection device is used in an electronic device to protect internal devices (eg, IC chips) from electrostatic discharge. Electrostatic discharge protection devices protect electronic components (ie, semiconductor chips) in electronic devices (ie, electronic systems) from high voltages and currents, such as static electricity, transients during switching, and lightning (or sparks). If the electrostatic discharge is introduced into the semiconductor chip of the internal circuit of the electronic device, the chip may be damaged.

In the case of electrostatic discharge, since the transient current flows in a very short time (for example, several nanoseconds), the response speed of the electrostatic discharge protection device must be very fast. That is, when the response speed of the electrostatic discharge protection device is slow, there is a problem that the transient current cannot be processed.

When a high voltage and a large amount of transient current flow into the electrostatic discharge protection device, a plurality of electrostatic discharge protection diodes are conventionally disposed in order to effectively remove this current.

Therefore, if multiple electrostatic discharge protection diodes are placed continuously between the input node and ground, the unprocessed transient current is processed by the additionally placed element, which provides stable power to the electronic device (electronic system). Stability can be increased. In this case, the ESD peak voltage is lowered by the voltage drop caused by the diode.

However, when a plurality of electrostatic discharge protection diodes are arranged continuously, the manufacturing cost of the entire device is increased, and the area occupied in the electronic device is wider than that of a single device. In addition, since the voltage drop caused by the diode is insignificant, there is a limit to reducing the ESD peak voltage.

Accordingly, the present invention can reduce the manufacturing cost and the area occupied by the device to fabricate a single chip device capable of discharging the introduced ESD to a plurality of discharge routes in order to solve the above problems, and to reduce the ESD peak voltage circuit Adding the device into the chip provides an electrostatic discharge protection device that can reduce the ESD peak voltage.

At least one discharge element for applying the ESD charge applied to the first internal terminal to at least one of the second and third internal terminals and the ESD applied to the second internal terminal by the discharge element At least one ESD chip having at least one discharge diode for discharging at least a portion of charge to the third internal terminal, wherein the discharge element is connected between the first internal terminal and the third internal terminal; It provides a static discharge protection device comprising a first diode and a second diode and a resistor connected in series between the first internal terminal and the second internal terminal.

The discharge element includes a plurality of the second diode and a first resistor connected in series between the first internal terminal and the second internal terminal, and they are connected in parallel to each other between the first internal terminal and the second internal terminal. Can be.

The second internal terminal is connected to a first power rail, the third internal terminal is connected to a ground rail, and the ESD charge applied to the fourth internal terminal is transferred to at least one of the fifth and third internal terminals. At least one discharge element to be applied; And at least one ESD chip having at least one discharge diode for discharging at least a portion of the ESD charge applied by the discharge device to the fifth internal terminal to the third internal terminal, wherein the fifth internal terminal is provided. May be connected to the second power rail.

Further, at least one discharge element for applying the ESD charge applied to the input terminal according to the present invention to at least one of an internal discharge node and a ground terminal, and at least one of the ESD charge applied to the discharge node by the discharge device. At least one ESD chip having at least one discharge diode for discharging a portion to the ground terminal, wherein the discharge element comprises: a first diode connected between the input terminal and the ground terminal; An electrostatic discharge protection device comprising a second diode and a resistor connected in series between internal discharge nodes is provided.

The discharge element includes a plurality of resistors and a second diode connected in series between the input terminal and the internal discharge node, which may be connected in parallel with each other between the input terminal and the internal discharge node.

In addition, at least one discharge element for applying the ESD charge applied to the first internal terminal according to the present invention to at least one of the second and third internal terminal and the second internal terminal by the discharge element At least one ESD chip having at least one discharge diode for discharging at least a portion of the charged ESD charge to the third internal terminal, wherein the discharge element is connected in series between the first internal terminal and a discharge node; At least one resistor and at least one first diode connected between one terminal of the resistor and a third internal terminal and a second diode connected between the discharge node and the second internal terminal; To provide.

The discharge element includes a 1-1 diode connected between the first internal terminal and a third internal terminal, a first resistor connected between the first internal terminal and the first discharge node, and the first discharge node. And a 1-2 diode connected between the third internal terminal, a second resistor connected between the first discharge node and the second discharge node, and a connection between the second discharge node and the third internal terminal. And a second diode connected between the first 1-3 diode and the second discharge node and the second internal terminal.

The discharge element includes a 1-1 diode connected between the first internal terminal and a third internal terminal, a first resistor connected between the first internal terminal and the first discharge node, and the first discharge node. And a 1-2 diode connected between the third internal terminal, a second resistor connected between the first discharge node and the second discharge node, and a connection between the second discharge node and the third internal terminal. It is possible to include the first 1-3 diode and the second diode connected between the first discharge node and the second internal terminal.

The second internal terminal may be connected to a power rail, the third internal terminal may be connected to a ground rail, and the second discharge node may be connected to the first internal terminal.

As described above, the present invention can reduce the ESD peak voltage by forming a plurality of discharge routes by a plurality of discharge elements, and placing a resistor inside the discharge element.

In addition, the present invention can reduce the manufacturing cost of the device by manufacturing a plurality of discharge devices in a single body of the chip, it is possible to reduce the area occupied by the device.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. Like numbers refer to like elements in the figures.

1 is a cross-sectional view of an electrostatic discharge protection device according to a first embodiment of the present invention, Figure 2 is a circuit diagram of the electrostatic discharge protection device according to a first embodiment of the present invention. 3 to 6 are circuit diagrams of an electrostatic discharge protection device according to a modification of the first embodiment.

1 and 2, the electrostatic discharge protection device according to the present embodiment includes an ESD protection chip 100 and a package 200 encapsulating the ESD protection chip 100.

Here, the package 200 includes a package body 210 accommodating the ESD protection chip 100, and a plurality of external terminals 220 electrically connected to the ESD protection chip 100 and extending out of the package body 210. 230, 240).

The electrostatic discharge protection device of this embodiment is located at an input node between an external connector and an internal chip as shown in FIG. 2 to discharge ESD applied to the input node to ground and / or power rails. Accordingly, the package 200 includes an input external terminal 220 connected to the input node, a power connection external terminal 230 connected to a power rail, and a ground connection external terminal 240 connected to a ground rail.

Here, as illustrated in FIG. 1, the external terminals 220, 230, and 240 extend in the inward direction from the outside of the package body 210. This reduces electrical interference and allows external connection terminals to be manufactured without the use of wires. Of course, the present invention is not limited thereto, and the external terminals 220, 230, and 240 may be located on the lower side of the package body 210. This may facilitate mounting of the package 200. In addition, the present invention is not limited thereto, and the external terminals 220, 230, and 240 may be electrically connected to each other through a separate wire.

In addition, the ESD protection chip 100 located in the package 200 includes a plurality of ESD protection circuit bodies 110 having a plurality of discharge routes, and a plurality of electrically connected discharge elements in the ESD protection circuit body 110. Internal terminals 120, 130 and 140 are provided.

The ESD protection chip 100 discharges ESD applied to the input external terminal 220 to the power connection external terminal 230 and / or the ground connection external terminal 240 through a plurality of discharge routes, as shown in FIG. 2. Let's do it.

The internal terminals 120, 130, and 140 are internal inputs for respectively connecting the ESD protection circuit body 110 to the input external terminal 220, the power connection external terminal 230, and the ground connection external terminal 240. A terminal 120, a power supply connecting internal terminal 130, and a grounding connecting internal terminal 140 are provided.

The ESD protection circuit body 110 includes a plurality of discharge circuit elements formed on a semiconductor substrate. In this case, the internal terminals 120, 130, and 140 are formed on the upper surface of the ESD protection circuit body 110 in FIG. 1. This may facilitate electrical connection with the external terminals 220, 230, and 240.

However, the present invention is not limited thereto, and the body may be variously modified.

For example, the ground connection inner terminal 140 among the inner terminals 120, 130, and 140 may be formed on the lower surface of the ESD protection circuit body 110. That is, it may be formed on the bottom surface of the semiconductor substrate. As a result, the size of the ESD protection chip 100 may be reduced, and a short circuit between internal terminals may be prevented. In addition, the ground connection inner terminal 140 may be formed on the lower side to increase the efficiency of the chip. In addition, the chip may be mounted through surface mount technology.

The ground connection inner terminal 140 of the ESD protection chip 100 having the above-described configuration is connected to the ground rail of the internal circuit of the electronic device by the ground connection outer terminal 240. The power connection inner terminal 130 is connected to the power rail by a power connection external terminal 230, and the input internal terminal 120 is connected between the connector and the internal chip by the input external terminal 220. At this time, a power supply voltage Vdd is applied to the power supply rail, and a ground voltage Vgnd is applied to the ground rail. Through this, the ESD protection chip 100 can effectively remove the ESD introduced from the connector to prevent the damage of the internal chip by the ESD.

The ESD protection circuit body 110 which performs the electrostatic discharge protection function is connected to the input internal terminal 120 respectively, and the ESD introduced into the input internal terminal 120 is connected to the power connection internal terminal 130 and the ground connection internal terminal ( A plurality of discharge elements 111 and 112 respectively discharged to the 140 and at least one discharge connected in parallel with the plurality of discharge elements 111 and 112 at the power connection internal terminal 130 and the ground connection internal terminal 140. Diodes D3 to D5 are provided. As described above, in the present exemplary embodiment, since the plurality of discharge elements 111 and 112 are disposed, the discharge lines (that is, the roots) of the ESD flowing into the input internal terminal 120 may be multiple. This also lowers the peak voltage provided to the internal chip. This is because the peak voltage due to the current of the ESD is reduced by the plurality of discharge elements 111 and 112. Furthermore, the ESD peak voltage can be reduced by the resistance in the discharge elements 111 and 112. In addition, since the plurality of discharge elements 111 and 112 having the discharge route are formed in a single chip, the unit cost can be reduced when a plurality of existing single elements are used.

In the ESD protection circuit body 110 according to the present embodiment, as shown in FIG. 2, each of the first and second discharge elements 111 and 112 is connected to the input internal terminal 120, and the first and second discharges are discharged. The elements 111 and 112 are connected in parallel between the power connection internal terminal 130 and the ground connection internal terminal 140.

In this case, the first discharge element 111 may include a first diode D1 connected between the input internal terminal 120 and the ground connection internal terminal 140, the power connection internal terminal 130, and the input internal terminal 120. ) And a second diode D2 and a first resistor R1 connected in series.

Here, when the first diode D1 receives a static voltage of a ground voltage below the ground voltage Vgnd from the outside, a charge (that is, a current) flows from the ground connection inner terminal 140 toward the input inner terminal 120. To do that.

The second diode D2 allows charge (ie, current) to flow from the input internal terminal 120 toward the power connection internal terminal 130 when the static electricity of a high voltage equal to or greater than the power supply voltage flows from the outside. At this time, the first resistor R1 lowers the ESD peak voltage applied to the second diode D2. This prevents internal chip damage from ESD voltages.

When the ESD voltage is higher than the power supply voltage, the forward resistance of the second diode D2 is lower than the reverse resistance of the first diode D1. The ESD current flows through the second diode D2 to the power supply rail and the third diode D3 to the sixth diode D6. At this time, when the first resistor R1 is present between the input internal terminal 120 and the second diode D2, the peak value of the input ESD voltage is inversely proportional to the resistance value of the first resistor R1. That is, when the first resistor R1 is inputted with an ESD voltage of 8000 V through the 1 ohm wire and the 10 Ω is set as the first resistor R1, the input peak current is inputted. Is the same as before and after passing through the first resistor R1. Thus, I = 8000 V / 1 Ω = X / 10 Ω, that is, the ESD peak voltage after passing through X = R1 is reduced to 800V. This reduces the ESD damage caused by high voltages. Thus, the addition of the first resistor can greatly prevent internal chip damage by the ESD voltage.

In addition, the second discharge element 112 also includes the sixth and seventh diodes D6 and D6 corresponding to the first and second diodes D1 and D2 and the first resistor R1 of the first discharge element 111. D7) and the second resistor R2. In this case, the connection and operation of the sixth and seventh diodes D6 and D7 and the second resistor R2 are the same as those of the first and second diodes D1 and D2 and the first resistor R1. Omit.

In addition, the ESD protection circuit body 110 according to the present embodiment may include the third to fifth discharge diodes respectively connected between the power connection inner terminal 130 and the ground connection inner terminal 140. D3, D4, D5). At this time, the third to fifth discharge diodes D3, D4, and D5 are connected in parallel with each other. The third to fifth discharge diodes D3, D4, and D5 are also connected in parallel to the first and second discharge elements 111 and 112, respectively.

In this case, the third to fifth discharge diodes D3, D4, and D5 discharge a part of the ESD charges provided to the power connection internal terminal 130 from the first and second discharge devices 111 and 112 to the ground rail. . As described above, in the present embodiment, the first and second discharge devices 111 and 112 share the third to fifth discharge diodes D3, D4, and D5. As a result, the size of the device may be reduced, and the capacitance of the entire ESD protection chip 1000 may be reduced.

In the present embodiment, the second diode D2, the third discharge diode D3, and the fifth discharge diode D5 and the sixth diode D6 are vertical back-to-back diodes. It may have a back diode structure or a lateral back-to-back diode structure. That is, the two diodes may have a vertical back-to-back diode structure connected to each other in series in the opposite direction but vertically connected thereto. At this time, the PNP structure is made vertically. In addition, when two diodes are connected in series in opposite directions, PNPs are placed adjacent to the P wells in the N well, and the P 졍 wires are attached to the terminals. As a result, the current path may have a horizontal back-to-back diode structure.

Here, the first, second, sixth and seventh diodes (D1, D2, D6, D7) and the third to fifth diodes (D3, D4, D5) are selected from among PN junction diodes, short circuit diodes, and zener diodes. Either one can be used. The built-in voltages of the first, second, sixth and seventh diodes D1, D2, D6, and D7 and the third to fifth diodes D3, D4, and D5 are 0.5. It is effective to be in the range of 0.9 to 0.9V, and the breakdown voltage is preferably 3 to 12V. Of course, the present invention is not limited thereto, and the breakdown voltages of the third to fifth diodes D3, D4, and D5 may be set differently. As a result, only some of the third to fifth diodes may discharge the ESD through breakdown according to the ESD characteristics introduced from the outside.

Hereinafter, the operation of the ESD protection chip 100 will be described.

First, a case in which a static electricity (that is, a + charge) having a high voltage greater than or equal to the power supply voltage Vdd from the system flows into the input internal terminal 120 of the ESD protection chip 100 through the connector is as follows. The introduced ESD charge is distributed by the second diode D2 of the first discharge element 111 and the sixth diode D6 of the second discharge element 112 to move to the power connection internal terminal 130. Here, the ESD charge introduced by the first resistor R1 of the first discharge element 111 and the second resistor R2 of the second discharge element 112 generates a voltage drop. This reduces the peak voltage of the incoming ESD.

At this time, the charges having a voltage equal to or higher than the breakdown voltage of the third to fifth discharge diodes D3, D4, and D5 among the charges transferred to the internal terminal 130 of the power supply connection may be the third to fifth discharge diodes D3, D4, and D5. Charge is discharged to the ground rail. The remaining charge is discharged through the power rail through the power connection inner terminal 130. Here, in the present embodiment, the introduced ESD charge is distributed by the first resistor R1 and the second diode D2 and the second resistor R2 and the sixth diode D6 to connect the internal terminal 130 to the power supply connection. The charge provided to the power supply connection internal terminal 130 is again dispersed and discharged by the third to fifth discharge diodes D3, D4, and D5. This allows multiple discharge devices to share a discharge diode, which not only effectively discharges the ESD charge but also reduces the device size. It is also possible to exit the ESD peak voltage.

In addition, by sharing a plurality of discharge diodes as described above, the passage for escaping the ESD current increases, thereby increasing the electrostatic discharge effect. Here, the number of discharge diodes is not limited, and may vary.

On the contrary, when the static electricity (that is, -charge) of the ground voltage below the ground voltage Vgnd from the outside of the system flows into the input internal terminal 120 of the ESD protection chip 100 through the connector, same. When the base voltage is provided to the input internal terminal 120, the first diode D1 of the first discharge element 111 and the seventh diode D7 of the second discharge element 112 operate as forward diodes, respectively. This replenishes the charge with the input internal terminal 120 at the ground rail. Therefore, when the static electricity of the ground voltage is introduced through the connector, the ground voltage is provided inside the internal chip. This means that base voltage static electricity is discharged to the ground rail.

As such, the ESD protection chip 100 of the present exemplary embodiment may limit a signal (ie, a voltage) provided to the internal chip within a range of a power supply voltage and a ground voltage.

In addition, the ESD protection chip 100 of the present embodiment is not limited to the above description, and various modifications are possible.

First, as shown in the modified example of FIG. 3, a plurality of resistors and diodes connected in series between the power supply connection internal terminal 130 and the input internal terminal 120 of the first and second discharge elements 111 and 112 are provided. These serially connected elements can be connected in parallel with each other. This may further lower the ESD peak voltage flowing into the input internal terminal 120. And, the discharge route of the high voltage static electricity can be further widened.

That is, the first discharge element 111 may include a second diode D2, a first resistor R1, and a ninth diode D9 connected in series between the connection internal terminal 130 and the input internal terminal 120. The third resistor R3 is provided. The second diode D2 and the first resistor R1 connected in series and the ninth diode D9 and the third resistor R3 connected in series are connected between the connection internal terminal 130 and the input internal terminal 120. In parallel to each other. Of course, the second discharge element 112 also includes a tenth diode 10 corresponding to the ninth diode D9 and includes a fourth resistor R4 corresponding to the third resistor R3.

In addition, as in the modified example of FIG. 3, the third to fifth discharge diodes D3, D4, and D5 may be integrated into one eighth discharge diode D8. As a result, the first and second discharge devices 111 and 112 may share one discharge diode. This allows the fabrication of smaller devices and reduces the overall capacitance of the ESD protection chip.

Subsequently, as in the modification of FIG. 4, the ESD charges provided to the first and second discharge devices 111 and 112 may be discharged only to the ground rail. Accordingly, the connection node N1 connecting the first and second discharge elements 111 and 112 and the third to fifth discharge diodes D3, D4, and D5 without forming the power connection internal terminal 130. Can form bays.

Accordingly, the first and second discharge devices 111 and 112 discharge external ESD to the connection node N1 and the ground rail. The ESD charges provided to the connection node N1 are discharged to the ground rail by the third to fifth discharge diodes D3, D4, and D5 connected to the connection node N1. This simplifies the device by eliminating internal terminals.

In addition, as in the modification of FIG. 5, the ESD protection chip 100 includes first and second chip circuits 101 and 102 connected to different input terminals, respectively. Through this, the ESD protection chip 100 of the present modification can protect an internal chip using a plurality of connectors and a plurality of power supplies from ESD. Here, the internal structure of each of the first and second chip circuits 101 and 102 may be the same as the description of the above-described embodiments and modifications, and thus will be omitted.

In addition, as in the modification of FIG. 6, external static electricity may be discharged through one route instead of a plurality of routes. That is, as in the modified example of FIG. 6, one discharge element 111 connected to the input internal terminal 120, the power connection internal terminal 130, and the ground connection internal terminal 140 in the ESD protection chip 100. 112 is positioned and includes third and fourth discharge diodes D3 and D4 connected in parallel to the discharge elements 111 and 112 between the power connection internal terminal 130 and the ground connection internal terminal 140. It may be. This can simplify the device and reduce the device size.

In the above description, the resistance is positioned before the second diode D2 and the sixth diode D6 of the discharge elements 111 and 112. However, the present invention is not limited thereto, and a resistor may be provided at the front end or the rear end of the first diode D1 and the seventh diode D7.

The present invention is not limited to the above-described embodiment, and various examples are possible. For example, a plurality of first diodes of the discharge element can be separated, and these can be connected by a resistor. As a result, the discharge of the base voltage can be effectively performed, and the peak voltage of the ESD can be lowered because the resistor must be passed in order to apply the ESD to the second diode.

Hereinafter, an electrostatic discharge protection device according to a second embodiment of the present invention will be described. The description overlapping with the above-described first embodiment will be omitted. At least some of the techniques of the second embodiment can be applied to the first embodiment.

7 is a cross-sectional view of the electrostatic discharge protection device according to the second embodiment of the present invention, Figure 8 is a circuit diagram of the electrostatic discharge protection device according to the second embodiment. 9 and 10 are circuit diagrams of an electrostatic discharge protection element according to a modification of the second embodiment.

As shown in FIGS. 7 and 8, the electrostatic discharge protection device according to the present embodiment includes an ESD protection chip 1000 and a package 2000 encapsulating the ESD protection chip 1000.

Here, the package 2000 includes a package body 2100 having an accommodation space for storing the ESD protection chip 1000, an input external terminal 2200 protruding outside the package body 2100, and a power connection external terminal 2300. In addition, a ground connection external terminal 2400 protruding from the bottom surface of the storage space of the package body 2100 to the outside of the package body 2100 is provided.

The ESD protection chip 1000 may include an ESD protection circuit body 1100, an input internal terminal 1200 and a power connection internal terminal 1300 formed on an upper surface of the ESD protection circuit body 1100, and the ESD protection circuit body. And a ground connection internal terminal 1400 formed on the bottom surface of 1100.

The input internal terminal 1200 is connected to the input external terminal 2200, the power connection internal terminal 1300 is connected to the power connection external terminal 2300, and the ground connection internal terminal 1400 is the ground connection internal terminal 2400. ) Is connected. As illustrated in FIG. 1, the input external terminal 2200 and the power connection external terminal 2300 are connected to the input internal terminal 1200 and the ground connection internal terminal 1300 through wires.

This effectively removes the ESD from the connector and prevents damage to the internal chip by the ESD.

The ESD protection circuit body 1100 that performs the electrostatic discharge protection function is connected to the input internal terminal 1200, the power connection internal terminal 1300, and the ground connection internal terminal 1400, as shown in FIG. A plurality of discharge elements 1110 and 1120 discharge the ESD applied to the internal terminal 1200 to at least one of the power connection internal terminal 1300 and the ground connection internal terminal 1400. And at least one discharge diode (D3, D4, D5) connected in parallel to the plurality of discharge elements (1110, 1120) between the power connection internal terminal (1300) and the ground connection internal terminal (1400).

In the present embodiment, two discharge elements, that is, the first and second discharge elements 1110 and 1120, are provided. The two discharge devices 1110 and 1120 share the discharge diodes D3, D4, and D5.

The discharge devices 1110 and 1120 include a plurality of resistors connected in series between the input internal terminal 1200 and the discharge node, a plurality of diodes connected between one terminal of the resistors and the ground connection internal terminal 1400, and And a diode connected between the discharge node and the power connection internal terminal 1300.

The first discharge device 1110 is connected to the input internal terminal 1200, the power connection internal terminal 1300, and the ground connection internal terminal 1400 as described above and illustrated in FIG. 8. The configuration of the first discharge device 1110 will be described with reference to the circuit diagram shown in FIG. 8. The first discharge device 1110 may include a 1-1 diode D1-1 connected between the input internal terminal 1200 and the ground connection internal terminal 1400, the input internal terminal 1200, and the first discharge node ( The first-first resistor R1-1 connected between Q1-a and the first-second diode D1-2 connected between the first discharge node Q1-a and the ground connection internal terminal 1400. ), The 1-2 resistor R1-2 connected between the first discharge node Q1-a and the second discharge node Q2-a, and the second discharge node Q2-a and ground. The first to third diodes D1-3 connected between the connection internal terminals 1400 and the second diode D2 connected between the second discharge node Q2-a and the power supply connection internal terminal 1300 are connected to each other. Equipped.

Here, the first-first diode (D1-1), the first-second diode (D1-2), and the first-first diode (D1-3) are input internal terminals 1200 and the first discharge node Q1-, respectively. When a) and the second discharge node Q2-a receive static electricity having a base voltage lower than or equal to the ground voltage Vgnd, the static electricity is discharged to the ground connection internal terminal 1400. By separating the diode for discharging the static electricity of the base voltage as in this embodiment, it is possible to effectively discharge the static electricity of the base voltage of various levels.

When the high voltage static electricity of the power supply voltage Vdd or more flows into the input internal terminal 1200, the second diode D2 discharges it to the power connection internal terminal 1300 and the ground connection internal terminal 1400.

In this case, the 1-1 resistor R1-1 and the 1-2 resistor R1-2 reduce the peak voltage of the ESD flowing into the input internal terminal 1200. As a result, the ESD peak voltages provided to the 1-2 diode D1-2, the 1-3 diode D1-3, and the second diode D2 may be reduced. Here, the first-first resistor R1-1 and the first-second resistor R1-2 are connected in series between the input internal terminal 1200.

As described above, since the peak voltage of the ESD is reduced by the 1-1 resistor R1-1 and the 1-2 resistor R1-2, the 1-1 diode D1-1 and the 1-2 diode It is effective that (D1-2) and the first-third diode (D1-3) have different breakdown voltages. At this time, it is effective that the breakdown voltage of the first-first diode D1-1 is the highest and the breakdown voltage of the first-first diode D1-3 is the lowest.

Since the ESD voltage of the positive potential is higher than the breakdown voltage of the first-first diodes D1-1 to 1-3, the first to third diodes D1-3, some input currents may be applied to the first-first diode D1-1. ) To the reverse current of the first to third diodes D1-3. In addition, the ESD peak voltage is lowered by the resistances of the first-first resistors R1-1 to the first-second resistors R1-2. As a result of the leaked current and the lowered peak voltage, the ESD voltage and the current are significantly lowered before being discharged to the power connection internal terminal 1300 through the forward diode (ie, the second diode D2). Therefore, the ESD voltage and the current stress applied to the second diode D2 are significantly lowered. Thus, even with a small junction area, the second diode D2 can have sufficient ESD immunity. Since the size of the second diode D2 can be reduced, the internal capacitance of the first discharge element can be made small.

Of course, the second discharge device 1120 is manufactured in the same configuration as the first discharge device 1110.

In addition, the present embodiment is not limited to the above description, and various modifications are possible.

First, as in the modification illustrated in FIG. 9, the second diode D2 may be connected between the first discharge node Q1-a and the power connection internal terminal 1300.

In the previous embodiment, the peak voltage of the ESD applied to the input internal terminal 1200 is lowered by the first-first resistor R1-1 and the first-second resistor R1-2, and then the second diode ( D2). However, the peak voltage of the ESD applied to the input internal terminal 1200 through the same connection as in the present modified example is lowered by the 1-1 resistor R1-1 or the 1-2 resistor R1-2. And then provided to the second diode D2. This speeds up the processing of the ESD chip.

In addition, it is possible to discharge the external ESD through a single root as in the variant shown in FIG. In the present modification, the first-first resistor R1-1 and the first-second resistor R1-2 are connected in series between the input internal terminal 1200 and the second discharge node Q2-a. The second diode D2 is connected between the second discharge node Q2-a and the power connection internal terminal 1300. Through this, the high voltage ESD flowing into the input internal terminal 1200 is connected to the power supply internal terminal by the 1-1 resistor R1-1, the 1-2 resistor R1-2, and the second diode D2. Is applied to 1300. The ESD applied to the power connection internal terminal 1300 is discharged to the ground connection internal terminal 1400 by the third and fourth discharge diodes D3 and D4. Of course, the ESD of the electromotive voltage is first discharged by the first-first diode D1-1 connected to the input internal terminal 1200, and the voltage is dropped by the first-first resistor R1-1. Subsequently, the second discharge is again performed by the first and second diodes D1-2, and the voltage is dropped by the first and second resistors R1-2. Thereafter, the third discharge may be performed by the first to third diodes D1-3.

In the present embodiment, the respective discharge elements and the diodes are connected to common internal terminals. However, the ESD protection chip of the present embodiment is not limited thereto, and the discharge elements and the diodes may be connected to separate internal terminals, respectively. In addition, terminals connected to a common rail among the plurality of inner terminals may be connected to each other by an outer terminal.

Although the invention has been described with reference to the accompanying drawings and the preferred embodiments described above, the invention is not limited thereto, but is defined by the claims that follow. Accordingly, one of ordinary skill in the art may variously modify and modify the present invention without departing from the spirit of the following claims.

1 is a cross-sectional view of an electrostatic discharge protection device according to a first embodiment of the present invention.

2 is a circuit diagram of an electrostatic discharge protection device according to a first embodiment of the present invention.

3 to 6 are circuit diagrams of an electrostatic discharge protection element according to a modification of the first embodiment.

7 is a cross-sectional view of an electrostatic discharge protection device according to a second embodiment of the present invention.

8 is a circuit diagram of an electrostatic discharge protection element according to the second embodiment.

9 and 10 are circuit diagrams of an electrostatic discharge protection element according to a modification of the second embodiment.

<Explanation of symbols for the main parts of the drawings>

100, 1000: ESD protection chip 110, 1100: ESD protection circuit body

111, 112, 113, 114, 1110, 1120: discharge element

120, 1200: internal terminal for input 130, 1300: internal terminal for power connection

140, 1400: Ground connection internal terminals 200, 2000: Package

Claims (9)

At least one discharge element for applying an ESD charge applied to the first internal terminal to at least one of the second and third internal terminals; And At least one ESD chip having at least one discharge diode for discharging at least a portion of the ESD charge applied by the discharge device to the second internal terminal to the third internal terminal, The discharge element, A first diode connected between the first internal terminal and the third internal terminal; And And a second diode and a resistor connected in series between the first internal terminal and the second internal terminal. The method according to claim 1, The discharge element includes a plurality of the second diode and a first resistor connected in series between the first internal terminal and the second internal terminal, and they are connected in parallel to each other between the first internal terminal and the second internal terminal. Electrostatic discharge protection element. The method according to claim 1, The second internal terminal is connected to a first power rail, the third internal terminal is connected to a ground rail, At least one discharge element for applying the ESD charge applied to the fourth internal terminal to at least one of the fifth and third internal terminals; And at least one ESD chip having at least one discharge diode for discharging at least a portion of the ESD charge applied by the discharge device to the fifth internal terminal to the third internal terminal, And said fifth internal terminal is connected to a second power rail. At least one discharge element for applying an ESD charge applied to an input terminal to at least one of an internal discharge node and a ground terminal; And At least one ESD chip having at least one discharge diode for discharging at least a portion of the ESD charge applied to the discharge node by the discharge element to the ground terminal, The discharge element, A first diode connected between the input terminal and the ground terminal; And And a second diode and a resistor connected in series between said input terminal and said internal discharge node. The method according to claim 4, And the discharge element includes a plurality of the second diode and a resistor connected in series between the input terminal and the internal discharge node, and these are connected in parallel with each other between the input terminal and the internal discharge node. At least one discharge element for applying an ESD charge applied to the first internal terminal to at least one of the second and third internal terminals; And At least one ESD chip having at least one discharge diode for discharging at least a portion of the ESD charge applied by the discharge device to the second internal terminal to the third internal terminal, The discharge element, At least one resistor connected in series between said first internal terminal and a discharge node; At least one first diode connected between one terminal of the resistor and a third internal terminal; And And a second diode connected between the discharge node and the second internal terminal. The method according to claim 6, wherein the discharge element, A 1-1 diode connected between the first internal terminal and a third internal terminal; A first resistor connected between the first internal terminal and a first discharge node; A first-second diode connected between the first discharge node and the third internal terminal; A second resistor connected between the first discharge node and the second discharge node; A first to third diode connected between the second discharge node and the third internal terminal; And And the second diode connected between the second discharge node and the second internal terminal. The method according to claim 6, wherein the discharge element, A 1-1 diode connected between the first internal terminal and a third internal terminal; A first resistor connected between the first internal terminal and a first discharge node; A first-second diode connected between the first discharge node and the third internal terminal; A second resistor connected between the first discharge node and the second discharge node; A first to third diode connected between the second discharge node and the third internal terminal; And And the second diode connected between the first discharge node and the second internal terminal. The method according to claim 7 or 8, And the second internal terminal is connected to a power supply rail, the third internal terminal is connected to a ground rail, and the second discharge node is connected to the first internal terminal.

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