CN212277198U - Integrated circuit with a plurality of transistors - Google Patents

Integrated circuit with a plurality of transistors Download PDF

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Publication number
CN212277198U
CN212277198U CN202020863679.8U CN202020863679U CN212277198U CN 212277198 U CN212277198 U CN 212277198U CN 202020863679 U CN202020863679 U CN 202020863679U CN 212277198 U CN212277198 U CN 212277198U
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electrostatic discharge
power
pin
ground
rail
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CN202020863679.8U
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Chinese (zh)
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F·塔耶特
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STMicroelectronics Rousset SAS
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STMicroelectronics Rousset SAS
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

Embodiments of the present disclosure relate to integrated circuits. The first power rail is provided as a power tree configured with coupling elements to distribute the power supply voltage to the active elements of the circuit. The second power rail is provided as an electrostatic discharge path and is not configured with a distribution tree coupling to the active elements of the circuit. The first ESD circuit is electrically connected between one end of the second power rail and the ground rail. The second electrostatic discharge circuit is directly electrically connected between the interconnection node and the ground rail. An interconnect node electrically interconnects the other end of the second power rail to the first power rail at the second electrostatic discharge circuit. Embodiments of the present invention provide a simple and inexpensive device enabling complete elimination of the risk of faults in the protection of integrated circuits from electrostatic discharge, which device exhibits reduced volume and improved performance, in particular in terms of predictability.

Description

Integrated circuit with a plurality of transistors
Technical Field
Embodiments relate to integrated circuits, and in particular to devices for protecting against electrostatic discharge in integrated circuits.
Background
Circuitry for integrated circuit electrostatic discharge (ESD) protection is subject to large currents (typically a few amperes) within the circuit.
These large currents must flow through the interior of the chip between the terminals receiving the discharge via specific paths.
As a general rule, these paths include dedicated protection components connected to the power supply rails, configured to clip electrostatic discharges through which discharge currents will flow.
In the integrated circuit interconnect layer (BEOL, for back-end-of-line), the power supply rails are typically constructed of metal tracks and distribute a supply voltage and a reference voltage to the active components at various points on the integrated circuit.
In general, the active component may be connected at any point on the power rail and is capable of withstanding a specified maximum voltage to be broken down. The active components are particularly sensitive to overvoltages in the supply voltage.
Due to ohmic voltage drops, during electrostatic discharge, the voltage on the power rail is equal to the voltage across the terminals of the dedicated protection component plus the voltage generated by the flow of discharge current to the power rail resistance.
Therefore, the voltage at one end of the power rail is typically higher than the maximum breakdown voltage, and the voltage at the point on the power rail to which the active component is connected (corresponding to the voltage divider bridge) is likely to be higher than the maximum breakdown voltage as well.
It has been proposed to reduce the resistance of the track by increasing the width of the track, but this can result in detrimental bulk.
Adjusting the protection components to reduce the voltage across the terminals is limited by the trade-off between supply voltage and maximum breakdown voltage, in addition to being technically difficult and expensive.
Increasing the number of protective components often results in random and difficult to control behavior.
Accordingly, there is a need to reduce the risk of failure during electrostatic discharge (ESD) protection of integrated circuits.
SUMMERY OF THE UTILITY MODEL
In view of the above, according to embodiments of the present disclosure, it is proposed a simple and inexpensive device enabling to completely eliminate the risk of failure in the protection of integrated circuits from electrostatic discharges, which device exhibits a reduced volume and improved performance, in particular in terms of predictability.
According to the utility model discloses, an integrated circuit is proposed, this integrated circuit includes: a first power rail configured to distribute a supply voltage to active elements of the integrated circuit; and a device for protecting against electrostatic discharge, the device comprising: a second power rail configured to conduct an electrostatic discharge current between a power pin and a ground pin, the second power rail not connected to any active element of the circuit; and a first electrostatic discharge clipping device having an input terminal; wherein the first power rail is connected to the power pin via the second power rail on the input terminal of the first electrostatic discharge clipping device.
In one or more embodiments, the first electrostatic discharge clipping device also has a reference terminal directly connected to the ground terminal.
In one or more embodiments, the second power rail is connected to the power pin and to the input terminal of the first electrostatic discharge clipping device.
In one or more embodiments, the integrated circuit further comprises a ground distribution tree connected to the ground pin, the ground distribution tree configured to distribute a ground voltage to active elements of the circuit, wherein the means for protecting against electrostatic discharge comprises a second electrostatic discharge limiting device connected directly to the power supply pin and directly to a point on the ground distribution tree.
In one or more embodiments, the integrated circuit further comprises at least one input-output pin, wherein the means for protecting against electrostatic discharge comprises at least one third electrostatic discharge clipping device directly connected to each input-output pin and directly connected to a corresponding point on the ground distribution tree, respectively.
In one or more embodiments, the integrated circuit further comprises an integrated circuit chip, produced on the semiconductor substrate and containing the active elements of the circuit; and an interconnect portion including a metal layer including the power rail and the pin.
According to the utility model discloses, another kind of integrated circuit is proposed, this integrated circuit includes: an active circuit component; a power supply pin; a ground pin; a first power rail having a first end and a second end, the first end being directly electrically connected to the power pin, wherein the first power rail does not have a distribution tree coupling for connecting a power source to any active component; a second power rail having a first end electrically connected directly to a second end of the first power rail at a node, wherein the second power rail has a distribution tree coupling for connecting a power source to an active component; a ground rail directly connected to the ground pin, wherein the ground rail has a distribution tree coupling for connecting a power source to an active component; a first electrostatic discharge clipping device having a first terminal electrically connected directly to the node and a second terminal electrically connected directly to the ground rail; and a second electrostatic discharge clipping device having a first terminal electrically connected directly to the power pin and a second terminal electrically connected directly to the ground rail.
In one or more embodiments, the integrated circuit further comprises: an input/output pin; and a third electrostatic discharge clipping device having a first terminal directly connected to the input/output pin and a second terminal directly connected to the ground rail.
With the embodiments according to the present disclosure, at least part of the aforementioned problems can be solved, and corresponding effects are achieved.
Drawings
Further advantages and features will become apparent by examining the detailed description of a completely non-limiting embodiment and the attached drawings, in which:
FIG. 1 illustrates an example of metal tracks of metal layers in a back-end of a line BEOL interconnect layer of an integrated circuit; and
fig. 2 shows the metal track described with reference to fig. 1 in the form of a circuit diagram.
Detailed Description
According to one aspect, an integrated circuit includes a first power rail configured to distribute a supply voltage to active elements of the integrated circuit, and a device for protecting against electrostatic discharge, the device including a second power rail configured to direct an electrostatic discharge current between a power pin and a ground pin, the second power rail not connected to any active elements of the circuit.
Thus, in the case of electrostatic discharge, a discharge current flows through the second power rail. Since the second power rail is not connected to any active element of the circuit, the ohmic voltage drop does not introduce a voltage higher than the maximum breakdown voltage into any active element of the circuit.
The device for protecting against electrostatic discharge according to this aspect does not require the second power rail to exhibit a very low resistivity and therefore can use a smaller area than conventional devices.
Due to the simple structure of the protection device, the behavior of the device is easily predictable and easily optimally designed.
According to one embodiment, the means for protecting against electrostatic discharge comprises a first electrostatic discharge clipping means having terminals directly connected to a ground terminal and an input terminal, and the second power supply rail is connected to the power supply pin and to said input terminal of the first electrostatic discharge clipping means.
Advantageously, the first power rail is connected to the power pin via the second power rail at said input terminal of the first electrostatic discharge clipping device.
Thus, during an electrostatic discharge, the voltage in the power distribution tree is determined by the voltage on said input terminal and this voltage is characterized by the first electrostatic discharge clipping device. For example, the electrostatic discharge limiter device is provided with thyristors and transistors using reliable and mature technologies.
According to one embodiment, the integrated circuit includes a ground distribution tree connected to the ground pin, the ground distribution tree configured to distribute a ground voltage to active elements of the circuit, and the means for protecting against electrostatic discharge includes a second electrostatic discharge limiting device connected directly to the power pin and directly to a point on the ground distribution tree.
The second clipping device is advantageously connected to a point on the ground distribution tree closest to the power supply pin.
In particular, the second clipping device makes it possible to distribute the discharge current from the power supply pin to the ground pin by simultaneously directing the discharge current through the second power supply rail and the ground distribution tree. This allows the width of the second power rail to be reduced and makes it possible to avoid the risk of fuse breakage caused by the full discharge current flowing through the second power rail.
According to one embodiment, the integrated circuit further comprises at least one input-output pin, and the means for protecting against electrostatic discharge comprises at least one third electrostatic discharge clipping device directly connected to each input-output pin and directly connected to a respective point on the ground allocation tree, respectively.
In particular, the present embodiment makes it possible to avoid an increase in the voltage in the first power rail in the case of a positive electrostatic discharge from the power supply pin to the input-output pin. In particular, the voltage increase caused by the ohmic drop on the ground distribution tree (after flowing through the second power supply rail, the discharge current flows through the ground distribution tree to the input-output pin) will be transferred to the ground pin as well as to the first power supply rail.
However, the at least one third discharge limiting device causes the discharge current to flow through a more direct resistive path between the power supply pin and the input-output pin, thereby avoiding a detrimental increase in voltage due to ohmic drop.
The present embodiment is advantageously applied to the input-output terminal closer to the power supply pin than the ground pin.
For example, the integrated circuit includes a chip produced on a semiconductor substrate and containing active elements of the circuit, and an interconnect portion including metal layers containing the power rails, the pins, and a ground distribution tree.
Fig. 1 shows an example of metal tracks of a metal layer in a BEOL interconnect layer of an integrated circuit CI. The abbreviation BEOL stands for back end of line.
The integrated circuit CI also comprises a chip (not shown) produced on the basis of a semiconductor substrate and containing the active elements of the circuit CI in the region of the front end of the line, generally indicated with the acronym FEOL.
The interconnect part of the integrated circuit CI comprises pins for external contacting of the integrated circuit, in particular a supply pin VDD for receiving a supply voltage (e.g. 5V) and a ground pin GND for receiving a reference voltage.
The integrated circuit CI comprises a first power supply rail VDDTR configured as a distribution tree for distributing the power supply voltages through various tree couplings to the active components located at various points in the chip. First power supply rail VDDTR is formed from metal tracks in one or more metal layers of the interconnect portion of integrated circuit CI.
Similarly, the ground distribution trees GNDTR are coupled to the active elements at various points Gi in the chip and are formed by metal tracks in one or more metal layers of the interconnect portion of the integrated circuit CI and are configured as distribution trees for distributing ground voltages to the active components located at various points in the chip through various tree-shaped couplings.
In the present example, the integrated circuit CI further comprises two input-output pins I/O for routing input and/or output signals.
In this specification, pins VDD, GND, I/O are shown as pads in the metal layer. After packaging, these pads will be electrically connected to the actual external pins, which are typically used to connect external devices.
The external pins may come into contact with an electrostatically charged component, such as the finger of an operator handling the integrated circuit CI. The electrostatic charge may be higher than the maximum breakdown voltage beyond which the active components of the integrated circuit CI will be destroyed.
The integrated circuit CI comprises a device ESD for protection against electrostatic discharges, which is configured to exhibit as low a voltage as possible between the two pins receiving the electrostatic discharge, so that the energy of the discharge is dissipated by the electrostatic discharge source.
In general, the Human Body Model (HBM), which is conventional and known per se, serves as a certain reference impedance capable of dissipating discharge energy.
To this end, the devices ESD for protection against electrostatic discharge include electrostatic discharge limiting devices ESD1, ESD2, ESD3, ESD4 ("ESDi") associated with each pin VDD, GND, I/O.
The electrostatic discharge clipping devices ESDi are connected directly to the respective pins, i.e. as close as possible and without any other elements coupled between them.
By arbitrary number, the first electrostatic discharge clipping device ESD1 is a device directly connected to the ground pin GND.
The electrostatic discharge clipping device ESDi generally includes a semiconductor component, such as a thyristor, which is configured to exhibit a high impedance ("open circuit") when the voltage between the two terminals is below a trigger voltage (also referred to as a discharge voltage), and to exhibit a negligible impedance ("short circuit") if the voltage between the two terminals exceeds the trigger voltage. The term "negligible impedance" is understood to mean an impedance that is negligible with respect to the impedance of the Human Body Model (HBM).
The device ESD for protection against electrostatic discharge further comprises a second power supply rail VDDBUS connecting the power supply pin VDD to a terminal of the first electrostatic discharge clipping device ESD 1.
Second power supply rail VDDBUS is formed, for example, by metal tracks in one or more metal layers of the interconnect portion of integrated circuit CI.
The second power supply rail VDDBUS is not connected to any active elements of the chip of the integrated circuit CI between the power supply pin VDD and said input terminal of the first discharge limiting device ESD1 (i.e. this bus is not configured as a distribution tree and therefore does not comprise any tree-like coupling for distributing the power supply voltage to active components located at various points in the chip).
Further, in order to distribute the power supply voltage to the active elements of the chip, the first power supply rail VDDTR is connected to the power supply pin VDD receiving the power supply voltage via the second power supply rail VDDBUS. Therefore, the first power supply rail VDDTR is connected to said input terminal NE of the first electrostatic discharge clipping device ESD 1.
The metal rails of first power supply rail VDDTR are configured to route the supply voltage from input terminal NE to the active elements located at various points Vi in the chip.
Further, the device ESD for protection from electrostatic discharge includes a second electrostatic discharge clipping device ESD2 connected directly to power supply pin VDD and a point on ground distribution tree GNDTR. Advantageously, the point on ground allocation tree GNDTR is selected as close as possible to power supply pin VDD.
The third ESD clipping devices ESD3, ESD4 are directly connected to each I/O pin and a corresponding point on the ground distribution tree GNDTR, respectively.
Reference is now made to fig. 2.
Fig. 2 shows the metal track described with reference to fig. 1 in the form of a circuit diagram.
Resistance RVi (where 0 ≦ i ≦ n-1), representing the inherent resistance of the metal tracks of the distribution tree of the first power supply rail VDDTR between the two points Vi and Vi +1 (where 0 ≦ i ≦ n-1), to which the active elements of the chip are coupled.
Resistance RGi (where 0. ltoreq. i.ltoreq.n-1) represents the intrinsic resistance of the metal track of ground distribution tree GNDTR between two points Gi and Gi +1 (where 0. ltoreq. i.ltoreq.n-1), to which the active elements of the chip are coupled.
Resistors RG' and RG "represent the inherent resistance of the metal tracks of ground distribution tree GNDTR between power supply pin VDD and the next input-output pin I/O and between ground pin GND and the next input-output pin I/O, respectively.
The resistance Rbus represents the intrinsic resistance of the metal rail of the second power rail VDDBUS connecting the power supply pin VDD to the input terminal NE of the first electrostatic discharge limiting device ESD 1.
Therefore, in the case where electrostatic discharge occurs between the power supply pin VDD and the ground pin GND, the discharge current IESDbus flows through the second power supply rail VDDBUS. Furthermore, since second power rail VDDBUS is not connected to any active elements of the chip at point Vi, the ohmic voltage drop in second rail VDDBUS does not introduce a voltage higher than the maximum breakdown voltage to the active elements of the chip.
In contrast, during electrostatic discharge, the voltage in the power distribution tree VDDTR is determined by the voltage on said input terminal NE and is determined by the design of the first electrostatic discharge clipping device ESD 1.
The technique, which is conventional and known per se, allows to configure the first electrostatic discharge limiting device ESD1 such that in the on-state the voltage on the input terminal NE is below the maximum breakdown voltage specified for the active element.
The parallel discharge current IESDg flows through the ground distribution tree GNDTR via the second discharge limiting device ESD2 and the first discharge clamp device ESD 1.
The voltage level at the Gi point rises due to the ohmic drop across resistor RGi, and is not detrimental to the active elements of the chip.
However, if electrostatic discharge occurs between the power supply pin VDD and the input/output pin I/O, for example, near the power supply pin VDD (I/O on the left side in fig. 2), instead of flowing through the direct metal line VDDBUS to the ground pin GND, and then flowing through the ground distribution tree GNDTR via the third electrostatic discharge limiting device ESD3 to the I/O of the input/output pin, the discharge current directly flows through the ground distribution tree between the power supply pin VDD and the input/output pin I/O via the second discharge limiting device ESD2 and the third discharge limiting device ESD 3.
This avoids combining the resistances Rbus, RGi (0 i n-1) and Rg 'of the metal tracks through which the discharge current flows, thereby avoiding an excessive rise in the voltage level at the supply pin due to ohmic drop caused by the combination of the resistances Rbus, RGi (0 i n-1) and Rg'.
In particular, in the absence of the second limiting means ESD2, the voltage increase due to the ohmic voltage drop across the resistors Rbus, RGi (0 ≦ i ≦ n-1) and Rg' will be transferred to the ground pin GND and, through the first discharge limiting means ESD1, to the input terminal NE connected to the power distribution tree VDDTR.
However, the second discharge limiting device ESD2 and the at least one third discharge limiting device ESD3 allow the discharge current to flow through a more direct resistive path between the power supply pin VDD and the input-output pin I/O, i.e. only through Rg', so that no voltage increase is caused by the ohmic voltage drop in the power distribution tree VDDTR.
The metal lines that are not required for the second power supply rail VDDBUS for device ESD protection from electrostatic discharge exhibit very low resistivity and the metal lines can be as small as the design rules allow, especially in view of the maximum allowable current density limitations during discharge and normal operation.
Due to the simple structure of the protection device ESD, the behavior of the device is easily predictable and can be easily optimally designed.
In other words, a dual power rail configuration is proposed, one rail acting as a standard power tree, the other rail carrying only electrostatic discharge current and not connected to any active components.
This structure makes it possible to foreseeably avoid the risk of a malfunction due to the local introduction of an overvoltage in the active element by the resistivity of the power supply rail, which is not very good in terms of protection of the integrated circuit against electrostatic discharges.
This configuration allows the size of the power rails to be based only on the normal operating requirements of the integrated circuit, rather than on minimizing voltage drops during electrostatic discharge. This makes it possible to avoid consuming silicon area or to implement more expensive processes for protection against electrostatic discharge.

Claims (8)

1. An integrated circuit, comprising:
a first power rail configured to distribute a supply voltage to active elements of the integrated circuit; and
a device for protecting against electrostatic discharge, the device comprising:
a second power rail configured to conduct an electrostatic discharge current between a power pin and a ground pin, the second power rail not connected to any active element of the circuit; and
a first electrostatic discharge clipping device having an input terminal;
wherein the first power rail is connected to the power pin via the second power rail on the input terminal of the first electrostatic discharge clipping device.
2. The integrated circuit of claim 1, wherein the first electrostatic discharge clipping device further has a reference terminal directly connected to the ground pin.
3. The integrated circuit of claim 1, wherein the second power rail is connected to the power pin and to the input terminal of the first electrostatic discharge clipping device.
4. The integrated circuit of claim 1, further comprising a ground distribution tree connected to the ground pin, the ground distribution tree configured to distribute a ground voltage to active elements of the circuit, wherein the means for protecting against electrostatic discharge comprises a second electrostatic discharge limiting device connected directly to the power pin and directly to a point on the ground distribution tree.
5. The integrated circuit of claim 4, further comprising at least one input-output pin, wherein the means for protecting against electrostatic discharge comprises at least one third electrostatic discharge limiting device directly connected to each input-output pin and directly connected to a corresponding point on the ground distribution tree, respectively.
6. The integrated circuit of claim 1, further comprising:
an integrated circuit chip produced on a semiconductor substrate and containing active elements of the circuit; and
an interconnect portion comprising a metal layer including the power rail and the pin.
7. An integrated circuit, comprising:
an active circuit component;
a power supply pin;
a ground pin;
a first power rail having a first end and a second end, the first end being directly electrically connected to the power pin, wherein the first power rail does not have a distribution tree coupling for connecting a power source to any active component;
a second power rail having a first end electrically connected directly to a second end of the first power rail at a node, wherein the second power rail has a distribution tree coupling for connecting a power source to an active component;
a ground rail directly connected to the ground pin, wherein the ground rail has a distribution tree coupling for connecting a power source to an active component;
a first electrostatic discharge clipping device having a first terminal electrically connected directly to the node and a second terminal electrically connected directly to the ground rail; and
a second electrostatic discharge clipping device having a first terminal electrically connected directly to the power pin and a second terminal electrically connected directly to the ground rail.
8. The integrated circuit of claim 7, further comprising:
an input/output pin; and
a third electrostatic discharge clipping device having a first terminal directly connected to the input/output pin and a second terminal directly connected to the ground rail.
CN202020863679.8U 2019-05-22 2020-05-21 Integrated circuit with a plurality of transistors Active CN212277198U (en)

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FR1905367 2019-05-22
FR1905367A FR3096516B1 (en) 2019-05-22 2019-05-22 Integrated electrostatic discharge protection device

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ATE229230T1 (en) * 1995-04-06 2002-12-15 Infineon Technologies Ag INTEGRATED SEMICONDUCTOR CIRCUIT WITH A PROTECTIVE AGENT
US6144542A (en) * 1998-12-15 2000-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. ESD bus lines in CMOS IC's for whole-chip ESD protection
JP3908669B2 (en) * 2003-01-20 2007-04-25 株式会社東芝 Electrostatic discharge protection circuit device
US7746606B2 (en) * 2004-01-12 2010-06-29 Conexant Systems, Inc. ESD protection for integrated circuits having ultra thin gate oxides
JP5085139B2 (en) * 2004-02-07 2012-11-28 サムスン エレクトロニクス カンパニー リミテッド Buffer circuit with electrostatic protection function
KR100996171B1 (en) * 2008-12-31 2010-11-24 주식회사 하이닉스반도체 Integrated circuit
JP2015180050A (en) * 2014-02-26 2015-10-08 セイコーエプソン株式会社 Semiconductor integrated circuit device and electronic apparatus using the same
US10826290B2 (en) * 2016-12-23 2020-11-03 Nxp B.V. Electrostatic discharge (ESD) protection for use with an internal floating ESD rail

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US11244941B2 (en) 2022-02-08
CN111987093A (en) 2020-11-24
FR3096516A1 (en) 2020-11-27
US20200373295A1 (en) 2020-11-26

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