KR20110012468A - Data converting apparatus in semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: A data converting apparatus in a semiconductor integrated circuit is provided to improve the stability of operation and the efficiency of an area by generating an analog signals through the phase difference of a clock. CONSTITUTION: A first differential amplifier(110) generates a first amplified clock by differently internal positive and negative clock. A first holding unit(120) generates a first level signal by holding a first amplification clock. A second amplification unit differently amplifies internal positive clock and a negative clock to generate a second amplification clock. A second holding unit generates a second level signal by holding the second amplification clock. A selection unit selectively outputs a first level signal or a second level signal as converted data.

Description

Data Converting Apparatus in Semiconductor Integrated Circuit

The present invention relates to a semiconductor integrated circuit, and more particularly to a data conversion device of a semiconductor integrated circuit.

Recently, semiconductor integrated circuits are becoming faster, more integrated, and larger. In order to implement such advanced semiconductor integrated circuits, a number of different technologies are being used, and multi-level transmission and reception technologies are widely used as information transmission technologies. Multi-level transmission / reception technology is a technology for transmitting information transmitted as a data signal of a plurality of bits as a one-bit data signal, where one bit of data contains information to be transmitted at that level. In other words, one bit of data does not contain only two pieces of information, a high level and a low level, but four or more pieces of information. The loss can be reduced. Such a technology could increase the information transfer speed of a semiconductor integrated circuit.

As such, in order to convert data implemented as a plurality of bits of digital signals into analog level signals, conventional semiconductor integrated circuits have been provided with data conversion devices. A conventional data conversion apparatus of a semiconductor integrated circuit generates a plurality of analog level signals and operates one of the analog level signals according to a logic value of the data. To produce, a large number of resistive elements were provided. That is, an analog level signal is generated by differentially dropping a voltage using a plurality of resistor elements, and selectively outputs it as a data signal.

However, in generating the analog level signal in the above manner, it is an important issue whether each resistance element has exactly the resistance value intended by the designer. Substantially, the resistance values included in the semiconductor integrated circuit are because the resistance value can be changed by various causes. Therefore, such a configuration is not easy to ensure the stability of the data conversion apparatus. In addition, a large number of resistance elements must be provided for such an operation, which causes a problem that the occupied area of the data conversion device becomes large. As described above, the data conversion device of the conventional semiconductor integrated circuit has exhibited problems in terms of stability and area efficiency, and accordingly, improvement of its configuration is required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and there is a technical problem to provide a data converting device of a semiconductor integrated circuit which improves stability and area efficiency.

The data conversion device of a semiconductor integrated circuit according to an embodiment of the present invention for achieving the above-described technical problem, by changing the phase of the negative internal clock of the positive / negative internal clock by the first time, the positive internal clock and the phase A first differential amplifier configured to differentially amplify the changed sub-internal clock to generate a first amplified clock; A first holding part which holds the first amplified clock to generate a first level signal in response to a first sample clock; A second differential amplifier configured to change a phase of a negative internal clock of the positive / negative internal clock by a second time and differentially amplify the positive internal clock and the phase-changed negative internal clock to generate a second amplified clock; A second holding unit configured to hold the second amplified clock in response to the first sample clock to generate a second level signal; And a selector configured to selectively output the first level signal or the second level signal as converted data in response to a second sample clock and a selection signal.

The data conversion device of the semiconductor integrated circuit of the present invention improves stability and area efficiency of operation by generating analog level signals by using a phase difference of a clock without having a resistor for generating an analog voltage through voltage drop. Create an effect.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a block diagram illustrating a configuration of a data conversion device of a semiconductor integrated circuit according to an embodiment of the present invention.

As illustrated, the data conversion apparatus of the semiconductor integrated circuit according to an exemplary embodiment of the present invention amplifies the positive / negative internal clocks CLK_INT and / CLK_INT in response to the first sample clock CLK_SMP1 and respectively performs first amplification. First to fourth level generators 10 to 40 generating the fourth to fourth level signals ALV1 to ALV4; And a selector 50 for selectively outputting the first to fourth level signals ALV1 to ALV4 as converted data D_CVT in response to a second sample clock CLK_SMP2 and the selection signal SEL. .

Here, although four level generators are provided as an example, this is only an example, and the data conversion apparatus of the semiconductor integrated circuit of the present invention may include a plurality of level generators without any limitation.

The first sample clock CLK_SMP1 and the second sample clock CLK_SMP2 are pulse signals generated from a clock generator, and are toggled once every predetermined period (for example, 20 cycles) of the internal clock CLK_INT. ) Is a signal. In the present embodiment, it is assumed that the toggle timing of the first sample clock CLK_SMP1 advances the toggle timing of the second sample clock CLK_SMP2 by one period of the internal clock CLK_INT.

The positive / negative internal clocks CLK_INT and / CLK_INT are clock signals in the form of clock signal pairs and have opposite phases.

The first to fourth level generators 10 to 40 perform an operation of differentially amplifying the positive and negative internal clocks CLK_INT and / CLK_INT, respectively. The phases of the negative internal clocks / CLK_INT are respectively set. After changing by time, differential amplification operation is performed. At this time, the time for changing the phase of the sub-internal clock / CLK_INT is set differently for each of the first to fourth level generators 10 to 40. Accordingly, the first to fourth level signals 10 to 40 are implemented as analog level signals having different levels. Here, although the first to fourth level generators 10 to 40 change the phase of the negative internal clock / CLK_INT, the phase may be configured to change the phase of the positive internal clock CLK_INT. have.

The selection signal SEL is a signal generated by decoding data of a plurality of bits (here, 2 bits), and is preferably understood to be a set of a plurality of signals. Although not shown in the configuration for decoding the data, the selection signal SEL is implemented in a form in which any signal corresponding to a logic value of the data among the signals included therein is enabled.

As such, the selector 50 selects one of the first to fourth level signals ALV1 to ALV4 according to the state of the selection signal SEL, and the second sample clock CLK_SMP2. The signal selected at the time of toggling is output as the conversion data D_CVT.

FIG. 2 is a configuration diagram of the first level generator shown in FIG. 1. Since the first to fourth level generators 10 to 40 are configured in the same form, the first level generator 10 will be described. This is shown to replace the description of the remaining level generator 20 ~ 40.

As illustrated, the first level generator 10 changes a phase of the negative internal clock / CLK_INT and differentially amplifies the positive internal clock CLK_INT and the phase-changed negative internal clock / CLK_INT. A differential amplifier 110 generating an amplified clock CLK_AMP; And a holding unit 120 holding the amplifying clock CLK_AMP to generate the first level signal ALV1 in response to the first sample clock CLK_SMP1.

As described above, the differential amplifier 110 of the first level generator 10 changes the phase of the sub-internal clock / CLK_INT before performing the differential amplification operation. The phase of the amplified clock CLK_AMP generated by the differential amplification operation of the differential amplifier 110 is affected by the phase change of the sub internal clock / CLK_INT. Therefore, the phase of the amplifying clock CLK_AMP that is periodically toggled is changed to change the transition timing of the potential level. In general, signals such as clocks have analog characteristics because of a certain limit in the slew rate of the signal when the potential level transitions. At this point, an analog level signal can be obtained by holding a point. Here, the first level generator 10 changes the level transition timing of the amplified clock CLK_AMP as described above, and then uses the first sample clock CLK_SMP1 at any point of the transition level. By holding, the first level signal ALV1 is generated.

If the amount of changing the phase of the sub-internal clock / CLK_INT is changed, the phase of the amplified clock CLK_AMP may be changed, and as a result, the level of the first level signal ALV1 may be changed. By using the same principle, the first to fourth level generators 10 to 40 may generate the first to fourth level signals ALV1 to ALV4 having different levels.

Such an operation principle may be more easily understood through the drawing of FIG. 3.

3 is a view for explaining the operation of the data conversion device of the semiconductor integrated circuit shown in FIGS. 1 and 2.

3 illustrates a point where the levels of the positive internal clock CLK_INT and the sub internal clock / CLK_INT intersect with each other. As described above, the first to fourth level generators 10 to 40 indicate that the sub-clocks are negative. Adjust the phase of the internal clock slightly (/ CLK_INT). Accordingly, the level transition timing of the amplified clock CLK_AMP also shows a slight difference for each of the first to fourth level generators 10 to 40. At this time, when the first sample clock CLK_SMP1 toggles and holds any point of the potential level of the amplifying clock CLK_AMP, the first to fourth level signals ALV1 to ALV4 having different analog levels are provided. ) Can be created.

4 is a detailed configuration diagram of the differential amplifier shown in FIG. 2.

As shown, the differential amplifier 110 includes a delay unit 112 for delaying the sub-internal clock / CLK_INT by a predetermined time; A first amplifier 114 which differentially amplifies the positive internal clock CLK_INT and the clock output from the delay unit 112; And a second amplifier 116 which differentially amplifies the signals output from the first amplifier 114 to generate the amplified clock CLK_AMP.

The first amplifier 114 includes: a first resistor (R1) disposed between a supply terminal of an external supply power source (VDD) and the first node (N1); A second resistor (R2) disposed between a supply terminal of the external supply power source (VDD) and a second node (N2); A first transistor TR1 having a positive internal clock CLK_INT input to a gate terminal thereof, a drain terminal thereof connected to the first node N1, and a source terminal thereof connected to a third node N3; A second transistor TR2 having an output signal of the delay unit 112 at a gate end thereof, a drain end thereof connected to the second node N2, and a source end thereof connected to the third node N3; And a third transistor TR3 having a bias voltage Vbias applied to the gate terminal, a drain die connected to the third node N3, and a source terminal grounded.

The second amplifier 116 may include: a first output node Nout1 for outputting the amplified clock CLK_AMP; A fourth transistor TR4 having a gate terminal and a drain terminal connected to the fourth node N4 and an external supply power supply VDD applied to the source terminal; A fifth transistor TR5 having a gate terminal connected to the fourth node N4, an external supply power supply VDD applied to a source terminal, and a drain terminal connected to the first output node Nout1; A sixth transistor of which a gate terminal is connected to the second node N2 of the first amplifier 114, a drain terminal is connected to the fourth node N4, and a source terminal is connected to the fifth node N5. (TR6); A gate terminal connected to the first node N1 of the first amplifier 114, a drain terminal connected to the first output node Nout1, and a source terminal connected to the fifth node N5. 7 transistor TR7; And an eighth transistor TR8 to which the bias voltage Vbias is applied to the gate terminal, the drain terminal is connected to the fifth node N5, and the source terminal is grounded.

In such a configuration, since the potential of the amplified clock CLK_AMP is basically high as the potential of the positive internal clock CLK_INT becomes high, the potential of the positive internal clock CLK_INT becomes low. As a result, it is low level. However, since the delay unit 112 is provided as described above to perform the delay operation with respect to the sub-internal clock / CLK_INT, the level transition timing of the amplified clock CLK_AMP is adjusted by the delay unit 112. As a result, the amplified clock CLK_AMP has a level transition timing that is faster or slower by a predetermined time than the basic level transition timing.

In addition to the first level generator 10, the second to fourth level generators 20 to 40 also include a differential amplifier and a holding unit, and each differential amplifier includes the first level generator 10. Each of the delay amplifiers in the same form as the differential amplifier 110 provided in the. At this time, each delay portion must have a different delay amount, and thus each amplified clock has a different phase.

FIG. 5 is a detailed configuration diagram of the holding unit shown in FIG. 2.

As shown, the holding unit 120 includes a second output node Nout2 for outputting the first level signal ALV1; An inverter IV receiving the first sample clock CLK_SMP1; A ninth transistor TR9 having an output signal of the inverter IV at a gate end thereof, an amplifying clock CLK_AMP input through a source end thereof, and a drain end thereof grounded to a sixth node N6; A capacitor CAP disposed between the sixth node N6 and a ground terminal; A tenth transistor TR10 having a gate terminal connected to the sixth node N6, a source terminal connected to the second output node Nout2, and a drain terminal grounded; And a current source CS disposed between the supply terminal of the external supply power source VDD and the second output node Nout2.

In the holding unit 120 configured as described above, the ninth transistor TR9 is turned on in the state where the first sample clock CLK_SMP1 is disabled, that is, at a low level. On). Accordingly, charge is charged in the capacitor CAP in response to the amplification clock CLK_AMP. If the potential of the amplifying clock CLK_AMP is at a high level, the charge charge amount is increased in the capacitor CAP. If the potential of the amplifying clock CLK_AMP is at a low level, the charge is precharged in the capacitor CAP. Is discharged. As the above operation is repeated, the amount of charge charged in the capacitor CAP is maintained in a predetermined range. As such, the amount of through current of the tenth transistor TR10 changes according to the amount of charge charged in the capacitor CAP. As a result, the level of the first level signal ALV1 formed at the second output node Nout2 is increased. Is formed.

Thereafter, when the first sample clock CLK_SMP1 is enabled, that is, when the potential is at a high level, the ninth transistor TR9 is turned off, and the capacitor CAP is turned off. Since the amount of charge to be charged is fixed, the potential level of the first level signal ALV1 is thus fixed.

As such, the potential level of the fixed first level signal ALV1 may change when the potential of the first sample clock CLK_SMP1 transitions to a low level. However, as soon as the second sample clock CLK_SMP2 is toggled and the first level signal ALV1 is input to the selector 30, the first level generated from the holding unit 120 is generated. The signal ALV1 can always function as a signal having a constant level.

As described above, the data conversion device of the semiconductor integrated circuit of the present invention includes a plurality of level generating units, and each level generating unit includes a differential amplifier unit and a holding unit. The differential amplifiers of the level generators each include a delay unit having a different delay amount, and perform an operation of changing the phase of the secondary internal clock by a predetermined time among the positive and negative internal clocks. Thereafter, each of the differential amplifiers differentially amplify the positive internal clock and the phase shifted sub internal clock to generate an amplified clock. Each holding unit performs an operation of holding each level of the amplified clock in response to the first sample clock to generate each level signal. Thereafter, in response to the second sample clock and the selection signal, the selection unit selectively outputs the plurality of level signals transmitted from the plurality of level generators as converted data.

By the function of the data conversion device of the semiconductor integrated circuit of the present invention, the semiconductor integrated circuit can overcome the problems that occur when the operation to generate an analog signal through the voltage drop having a resistor element. . That is, since the data conversion device of the semiconductor integrated circuit of the present invention does not have a large number of resistance elements as in the prior art, the area efficiency can be improved. In addition, it is possible to overcome the deterioration in stability of the data conversion operation caused by the unstable resistance value of the resistance elements, and to implement a more stable data conversion operation.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram showing the configuration of a data conversion device of a semiconductor integrated circuit according to an embodiment of the present invention;

2 is a configuration diagram of a first level generator shown in FIG. 1;

3 is a view for explaining the operation of the data conversion device of the semiconductor integrated circuit shown in FIG.

4 is a detailed configuration diagram of the differential amplifier shown in FIG. 2;

FIG. 5 is a detailed configuration diagram of the holding unit shown in FIG. 2.

<Description of the symbols for the main parts of the drawings>

10 to 40: first to fourth level generating unit 50: selecting unit

110: amplification unit 120: holding unit

Claims (7)

A first differential amplifier configured to change a phase of the negative internal clock among the positive / negative internal clocks by a first time and differentially amplify the positive internal clock and the phase-changed negative internal clock to generate a first amplified clock; A first holding part which holds the first amplified clock to generate a first level signal in response to a first sample clock; A second differential amplifier configured to change a phase of a negative internal clock of the positive / negative internal clock by a second time and differentially amplify the positive internal clock and the phase-changed negative internal clock to generate a second amplified clock; A second holding unit configured to hold the second amplified clock in response to the first sample clock to generate a second level signal; And A selector for selectively outputting the first level signal or the second level signal as converted data in response to a second sample clock and a selection signal; Data conversion device of a semiconductor integrated circuit comprising a. The method of claim 1, The first sample clock and the second sample clock are pulse signals that toggle once every predetermined period of the positive and negative internal clocks, and the first sample clock has a faster toggle timing than the second sample clock. A data conversion device for a semiconductor integrated circuit. The method of claim 1, The selection signal is a set of a plurality of signals generated by decoding a plurality of bits of data, and any one signal corresponding to a logic value of the data among the signals included therein is implemented to be enabled. A data conversion device for semiconductor integrated circuits. The method of claim 1, The first differential amplifier, A delay unit delaying the sub-internal clock by the first time; A first amplifier which differentially amplifies the positive internal clock and the clock output from the delay unit; And A second amplifier for generating the first amplified clock by differentially amplifying the signals output from the first amplifier; Data conversion apparatus of a semiconductor integrated circuit comprising a. The method of claim 1, The first holding part includes a capacitor, and in the disabled state of the first sample clock, charges or discharges charge in the capacitor in response to the first amplified clock, and when the first sample clock is enabled, the capacitor And fix the charge amount and generate the first level signal of a level corresponding to the fixed amount of charge. The method of claim 1, The second differential amplifier, A delay unit delaying the sub-internal clock by the second time; A first amplifier which differentially amplifies the positive internal clock and the clock output from the delay unit; And A second amplifier configured to differentially amplify signals output from the first amplifier to generate the second amplified clock; Data conversion apparatus of a semiconductor integrated circuit comprising a. The method of claim 1, The first holding part includes a capacitor, and in the disabled state of the first sample clock, charges or discharges charge in the capacitor in response to the first amplified clock, and when the first sample clock is enabled, the capacitor And fix the charge amount and generate the first level signal of a level corresponding to the fixed amount of charge.

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