KR20110010542A - System and apparatus for synchronization between heterogeneous periodic clock domains, circuit for detecting synchronization failure and data receiving method - Google Patents

Abstract

PURPOSE: A system and apparatus for synchronization between heterogeneous periodic clock domains, a circuit for detecting synchronization failure and data receiving method are provided to avoid synchronization failure without latency by estimating the synchronization failure between heterogeneous periodic clock domains. CONSTITUTION: A sender(100) outputs a prediction clock having a first clock which is delayed a first time. A receiver(200) predicts the synchronization failure between the first clock and a second clock by using the prediction clock. The receiver delays the second clock which is selected from an estimation result by a second time to synchronize the second clock with the first clock. The sender detects the synchronization failure between the estimation clock and the second clock, thereby estimating synchronization failure generation time in advance.

Description

System and apparatus for synchronization between heterogeneous periodic clock domains, circuit for detecting synchronization failure and data receiving method}

The present invention relates to a synchronization system, a synchronization device, a synchronization failure detection circuit, and a data receiving method capable of preventing performance degradation due to increased latency in a multi-clock domain environment.

The present invention is derived from a study conducted as part of the government pension project of the Ministry of Knowledge Economy. [Task management number: 1415094961, Assignment name: Development of embedded system technology for intelligent automotive electronics]

In a System on a Chip (SoC) design using numerous IPs, each IP can operate at a different clock frequency. Integrating these different IPs requires solving the synchronization failure that can occur when transferring data between IPs. For example, driving all of the IPs to a single clock to match the IP operating at the lowest clock frequency ensures synchronization, but with performance degradation. By adjusting the clock cycles of each IP in an integer multiple, it is possible to apply a relatively easy synchronization technique and prevent performance degradation rather than a single clock based synchronization technique. However, the adjustment of the integer multiple relationship between clocks decreases the application effect as the number of IPs increases and the difference in optimized clock frequencies between IPs increases.

Various synchronization techniques have been proposed to solve this synchronization failure problem.

The "Synchronous" assumption refers to the underlying assumption of synchronous circuitry, which is the assumption that the clock characteristics must be the same throughout the chip. The "Mesochronous" assumption assumes that there is no frequency difference between clocks observed in the chip but only a phase difference. In other words, the delay time from the clock source to two specific leaf nodes is assumed to be different. Therefore, the synchronization device uses a delay device that adjusts the clock or data transfer rate. The "Plesiochronous" assumption admits slight frequency differences, so the phase can change. It is assumed that you use the "Mesochronous" home synchronization method and perform it repeatedly.

The "Related" assumption is an assumption that the clock frequencies of two points in a chip are integral multiples. In this hypothesis, the case of synchronization failure can be easily predicted by characterizing the clock frequency. "Heterogeneous" assumptions require specialized synchronization failure prediction schemes where the clock frequencies vary, regardless of the integer multiple of the clock frequencies. The "Asynchronous" assumption is a home that covers all the assumptions described so far, and synchronization requires a synchronization device based on an asynchronous design technique.

The "Synchronous", "Mesochronous", and "Plesiochronous" assumptions are the divisions in a single clock environment, and the "Related", "Heterogeneous", and "Asynchronous" assumptions are the divisions in a multi-clock environment with multiple clock sources. In homes up to "Heterogeneous", all clocks must remain periodic.

Accordingly, an object of the present invention is to provide a synchronization device, a system, a synchronization failure detection circuit, and a data receiving method which solve the synchronization failure problem that may occur when data is transmitted between heterogeneous clock domains having a plurality of periodic clocks without latency.

The object of the present invention is not limited to the above-mentioned object, and many other objects not mentioned will be clearly understood by those skilled in the art from the following description.

A synchronization system according to an aspect of the present invention for achieving the above object is a synchronization system between heterogeneous cycle clock domains comprising a sender and a receiver operating in accordance with the first clock and the second clock of the heterogeneous period, respectively, A predictor that outputs a predicted clock having a first time delayed by a first time delay and the predicted clock are used to predict whether synchronization between the first clock and the second clock has failed, and optionally, the second clock is selectively determined according to the prediction result. And a receiver for synchronizing with the first clock by a second time delay.

A synchronization device according to another aspect of the present invention for achieving the above object is a synchronization device for performing synchronization between a first clock and a second clock of a heterogeneous period, the first clock is a first clock delayed prediction clock; A first sampling unit configured to sample the predicted clock in response to a first delayed signal received and delayed by the second clock by a hold time of the first clock; The second sampling unit for sampling the prediction clock and the result sampled by the first and second sampling units, respectively, in response to the second delayed signal delaying the second clock by a time subtracted from the setup time. A detector configured to detect a synchronization failure between the first and second clocks by sampling at two clocks and comparing the results sampled by the second clock; And a synchronization unit configured to delay two clocks by a second time to synchronize with the first clock.

The synchronization failure detection circuit according to another aspect of the present invention for achieving the above object is a synchronization failure detection circuit for detecting whether or not the synchronization failure between the first clock and the second clock, the hold time of the first clock In response to the first delayed signal delaying the second clock, a first sampling unit for sampling the first clock, and the second clock by a time obtained by subtracting the setup time of the first clock from the period of the second clock; And a second sampling unit for sampling the first clock and a detector for detecting whether the results sampled by the first and second sampling units are different from each other in response to the delayed second delayed signal.

A data receiving method according to another aspect of the present invention for achieving the above object, in accordance with a second clock of a period different from the period of the first clock from the first clock domain operating in accordance with the first clock A method of receiving data in a second clock domain, the method comprising: receiving a prediction clock whose first clock is delayed by a first time from the first clock domain and using the prediction clock; Predicting whether or not the synchronization has failed, delaying the second clock by a second time, and sampling the data in response to the second clock delayed by the second time.

Details of other embodiments are specifically disclosed by the detailed description and the drawings.

According to the configuration of the present invention, it is possible to predict whether synchronization between heterogeneous clock domains fails, and thus to avoid synchronization failure without latency.

1 is a block diagram illustrating a general system consisting of a sender and a receiver.
2 is a circuit diagram illustrating a synchronization failure detection circuit according to an embodiment.
3 is a signal diagram for describing an operation of a synchronization failure detection circuit of FIG. 2.
4 and 5 are signal diagrams for explaining how many cycles before the second clock can be predicted in advance when the first clock is delayed by how much time.
6 is a block diagram illustrating a synchronization system between heterogeneous periodic domains according to an embodiment.
FIG. 7 is a block diagram illustrating the clock predictor illustrated in FIG. 6.
FIG. 8 is an exemplary circuit diagram illustrating the synchronizer shown in FIG. 6.
9 is a circuit diagram illustrating a modification of the synchronization unit of FIG. 8.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, “comprises” and / or “comprising” refers to a component, step, operation and / or device that is present in one or more other components, steps, operations and / or elements. Or does not exclude additions.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, and the same reference numerals are used for components having the same configuration and function in each of the drawings.

A synchronization failure detection circuit according to an embodiment will be described with reference to FIGS. 1 to 3. 1 is a block diagram illustrating a general system including a sender and a receiver, FIG. 2 is a circuit diagram illustrating a synchronization failure detection circuit according to an embodiment, and FIG. 3 is a signal diagram for describing an operation of the synchronization failure detection circuit of FIG. 2. to be.

First, as shown in FIG. 1, the sender and the receiver operate in different clock domains. That is, the sender operates according to the first clock sclk, and the receiver operates according to the second clock rclk. Here, the first clock sclk and the second clock rclk are different from each other, but both are periodic signals. Since the sender operates according to the first clock sclk and outputs data, the data is synchronized to the first clock sclk. However, since the sender and the receiver operate in different clock domains, the receiver operating as the second clock rclk may fail to synchronize with the first clock sclk.

The synchronization failure in the receiver may be detected through a synchronization failure detection circuit as shown in FIG. 2.

The synchronization failure detection circuit 1 delays the second clock rclk by T-Ts (T: period of the second clock rclk, Ts: setup time of the first clock sclk). (Or a signal that advances the second clock rclk by the setup time of the first clock sclk) and delays the second clock rclk by Th (Th: hold time of the first clock sclk) The first clock sclk may be sampled and determined using each of the signals. Delaying the second clock rclk by T-Ts and Th, respectively, creates a window corresponding to the hazard period of the first clock sclk, and the second clock rclk is generated in this window period. .

As shown in FIG. 2, the synchronization failure detection circuit 1 includes a first sampling unit 20, a second sampling unit 30, and a detection unit 40. The first and second sampling units 20 and 30 include delayers 22 and 32 and flip-flops FF1 and FF2, respectively.

The first sampling unit 20 samples the first clock sclk in response to a signal delaying the second clock rclk by Th, and the second sampling unit 30 sets the second clock rclk to T−. The first clock sclk is sampled in response to the signal delayed by Ts. Specifically, the first delayer 22 delays the second clock rclk by Th, and the first flip-flop FF1 responds to the second clock rclk delayed by the first delayer 22. One clock (sclk) is sampled. The second delayer 32 delays the second clock rclk by T-Ts, and the second flip-flop FF2 responds to the second clock rclk delayed by the second delayer 32. One clock (sclk) is sampled.

The detector 40 compares the sampling results of the first and second sampling units 20 and 30 to detect whether a synchronization failure between the first clock sclk and the second clock rclk occurs.

The operation of the synchronization failure detection circuit 1 will be described in more detail with reference to FIG. 3.

If the first and second sampling units 20 and 30 of FIG. 2 sample the same value as shown in FIGS. 3A and 3B, there is no synchronization failure. In the case of Fig. 3 (a), the A and B node values of Fig. 2 are all '0', and in Fig. 3 (b), the A and B node values are '1'. However, when the node A is '0' and the node B is '1' as shown in FIG. 3C, the second clock rclk means that the second clock rclk is in a critical section of the first clock sclk. Indicates that a synchronization failure exists. Therefore, when the sampling results of the first and second sampling units 20 and 30 are different, the detection unit 40 of FIG. 2 detects a synchronization failure, and the sampling results of the first and second sampling units 20 and 30 are the same. Do not detect synchronization failures.

The detector 40 includes an AND operator to invert a sampling result of any one of the first and second sampling units 20 and 30 and perform an AND operation with another sampling result. Can be. However, the detection unit 40 is not limited thereto, and may be implemented in various forms, for example, may be configured as XOR gates (Exclusive-OR gates).

On the other hand, even if the synchronization failure detection circuit 1 of FIG. 2 can detect the synchronization failure, if the synchronization failure cannot be determined in advance, data cannot be correctly transmitted. Therefore, when the first clock sclk, which is delayed by a specific time instead of the first clock sclk, is input to the synchronization failure detection circuit 1 of FIG. 2, a synchronization failure may be predicted before several cycles of the second clock rclk. This prevents synchronization failures in advance.

Hereinafter, with reference to FIGS. 4 and 5, how many cycles before the second clock rclk can be predicted in advance when the first clock sclk is delayed by how much time will be described.

4 and 5 are signal diagrams for explaining how many cycles before the second clock rclk can be predicted beforehand by how much time the first clock sclk is delayed.

를 갖는 free running 신호의 rising edge의 시간 집합을

라 가정하고,

를 시간

만큼 지연 시킨 신호의 rising edge의 시간 집합을

라고 가정한다. 사실상, 주기

를 갖는 free running 신호는

만큼 지연 혹은 앞당겨도 동일한 rising edge 시간 집합을 갖기 때문에

는 다음과 같이 표현할 수 있다.Give first

Set the time of rising edge of free running signal with

Assume that

Time

Time set of the rising edge of the signal delayed by

Assume that Virtual cycle

Free running signal with

Delaying or advancing by as much as the same rising edge time set

Can be expressed as

(1)

(One)

는therefore

Is

(2)

(2)

의 (n<0)인 경우와

의 (-nT+t)<0인 경우는 의미상 신호를 앞 시간으로 당김을 나타낸다. . From here

For (n <0) of and

(-NT + t) <0 means that the signal is pulled forward in time.

As shown in FIG. 4, assuming a second clock rclk having a period Tr and a first clock sclk of a Ts period, and delaying the first clock sclk by a specific time, the second clock ( How many cycles before the cycle of the first clock (sclk) can be predicted. A synchronization failure phenomenon occurs with the first clock sclk at the fourth rising edge H of the second clock rclk. At G, which is one cycle before the fourth rising edge H of the second clock rclk, the first clock sclk may be delayed from F to G (Tp) to predict whether or not the synchronization has failed at H. On the other hand, the relationship between the first clock sclk_del and the second clock rclk delayed by Tr, which is the period of the second clock rclk, is the relationship between the second clock rclk and the first clock sclk before one cycle. Same as relationship Therefore, as shown in FIG. 4, the time from F 'to H is equal to Tp in the signal sclk_del in which the first clock sclk is delayed by Tr (see point B at point A). However, Tp is equal to a phase difference between the first clock sclk and the first clock sclk_del delayed by Tr. That is, the phase difference between the first clock sclk_del delayed by Tr and the first clock sclk is Tp, and the sclk_e1 signal is a signal obtained by delaying the first clock sclk by Tp (see point C at point A). The synchronization failure occurs before one cycle of the fourth cycle of the second clock rclk, that is, the third cycle G.

The sclk_e2 and sclk_e3 signals delay the first clock sclk by twice Tp and triple Tp, respectively, and as a result, a second failure in which synchronization failure between the first clock sclk and the second clock rclk occurs. From the fourth cycle H of the clock rclk, a synchronization failure phenomenon occurs two cycles and three cycles, respectively, so that the synchronization failure phenomenon can be predicted in advance. This shows that the synchronization failure is predictable a few cycles before, according to a certain law.

That is, when the sclk_e1, sclk_e2, and sclk_e3 signals are input to the synchronization failure detection circuit 1 of FIG. 2 instead of the first clock sclk, it is possible to predict whether the synchronization has failed before Tr, 2 * Tr, and 3 * Tr, respectively. sclk_e1, sclk_e2, sclk_e3 signals are hereinafter referred to as prediction clocks).

When implementing a circuit for predicting synchronization failure in advance, the delay element is used to delay a specific signal. The longer the delay time is, the more difficult the delay element is to be designed and additional side effects such as power consumption are generated. do. However, by using the characteristics of the periodic signals of Equations (1) and (2), the same effect can be obtained while reducing the delay time.

In FIG. 4, the prediction clock sclk_e3, which is a signal obtained by delaying the first clock sclk by 3 * Tp, is applied to Equation (2) as an example.

(3)

(3)

It can be expressed as From here

(4)

(4)

값이 sclk 를 3*Tp 만큼 지연시킨 신호와 동일한 free running 신호의 최소 지연 시간이 된다. We can determine the minimum value of n (n = ...,-3, -2, -1,0,1,2,3, ...) that satisfies

The value is the minimum delay of the free running signal that is equal to the signal that delayed sclk by 3 * Tp.

를 만족시키는 n은 n≥-2.5, 즉 -2로 결정된다. 결론적으로 제2 클록(rclk)을 기준으로 3 싸이클 이전에 동기화 실패를 예측하기 위해서는, 제1 클록(sclk)을 3*Tp 만큼 지연시켜도 가능하지만, 최소의 지연 시간을 위해, 제1 클록(sclk)을 3*Tp 만큼 지연시킨 예측 클록 (sclk_e3)과 동일한 파형을 같는 신호를 이용하면 된다 즉, 제1 클록(sclk)을

만틈 지연시킨 예측 클록(sclk_e4)을 이용하면, 회로 구현할 때에도 지연 시간을 최소로 할 수 있어 지연 소자의 설계가 간단해 지고, 전력 소모도 줄일 수 있다. 이러한 예측 클록(sclk_e4)을 생성하는 클록 예측부에 관한 설명은 도 7을 참조하여 후술한다.Looking more specifically with reference to Figure 5, assuming that Tr, Ts is 70 ns, 60 ns, respectively, Tp is 50 ns. At this time

N satisfying n is determined as n ≧ −2.5, that is, −2. In conclusion, in order to predict synchronization failure before three cycles based on the second clock rclk, it is possible to delay the first clock sclk by 3 * Tp, but for the minimum delay time, the first clock sclk Is a signal having the same waveform as that of the predicted clock sclk_e3 having a delay of 3 * Tp. That is, the first clock sclk

By using the delayed prediction clock sclk_e4, the delay time can be minimized even when the circuit is implemented, thereby simplifying the design of the delay device and reducing power consumption. A description of the clock predictor that generates the predicted clock sclk_e4 will be described later with reference to FIG. 7.

6 to 8, a synchronization system according to an embodiment of the present invention will be described. FIG. 6 is a block diagram illustrating a synchronization system between heterogeneous periodic domains, FIG. 7 is a block diagram illustrating a clock predictor illustrated in FIG. 6, and FIG. 8 is an exemplary circuit diagram illustrating the synchronizer illustrated in FIG. 6. .

6 shows a top block diagram for synchronization of a heterogeneous environment. The synchronization system 10 includes a sender 100 and a receiver 200, the sender 100 includes a clock predictor 110, and the receiver 200 includes a synchronizer 210.

In order to detect the above-described synchronization failure, the clock predictor 110 delays the first clock sclk for a predetermined time to generate the prediction clock sclk_e. The sender 100 outputs the prediction clock sclk_e and the data to the receiver 200.

The synchronizer 210 of the receiver 200 provides a function of detecting and avoiding synchronization failure in advance.

First, the clock predictor 110 of the sender 100 will be described in detail with reference to FIG. 7.

The clock predictor 110 includes a variable delay element 120, a fixed delay element 130, and a phase comparator 140.

The variable delay element 120 delays and outputs the first clock sclk by a variable time according to the feedback of the phase comparator 140. The fixed delay element 130 delays and outputs the first clock sclk delayed by the variable delay element 120 by a period, for example, three periods 3 * Tr. The phase comparator 140 compares the phase between the output of the variable delay element 120 and the first clock sclk and feeds back the comparison result to the variable delay element 120.

For example, initially, the variable delay element 120 outputs the first clock sclk without delay, and the fixed delay element 130 delays the first clock sclk by 3 * Tr. The phase comparator 140 compares the phases of the first clock sclk and the first clock sclk delayed by 3 * Tr by the fixed delay element 130. If the comparison does not have the same phase, it is fed back to the variable delay element (120). The variable delay element 120 delays and outputs the first clock sclk by a predetermined time according to the feedback, and the fixed variable element delays and outputs the signal output by the variable delay element 120 by 3 * Tr. The phase comparator 140 compares the phase of the signal output from the first clock sclk with the fixed variable element and feeds back the comparison result to the variable delay element 120.

As such, when the delay time is added to the variable delay element 120 until the phase difference disappears in the phase comparator 140 and finally there is no difference in the phase comparator 140, the variable delay element 120 at that time The prediction clock sclk_e is generated and output through the delay time. The predicted clock sclk_e output here may be, for example, the predicted clock sclk_e4 of FIG. 5.

On the other hand, the synchronizer 210 includes a synchronization failure detection circuit 1 of the structure shown in FIG. 2 to detect whether synchronization failed. The prediction clock sclk_e is received to predict a synchronization failure in advance, and when synchronization fails, the second clock rclk is delayed by a predetermined time to synchronize with the first clock sclk, and the second clock rclk_del2 delayed by a predetermined time is delayed. Receive data. If the synchronization does not fail, the synchronizer 210 receives data according to the second clock rclk. An example of such a synchronizer 210 will be described in detail with reference to FIG. 8.

Referring to FIG. 8, the synchronizer 210 includes a first sampling unit 220, a second sampling unit 230, a detection unit 240, and a synchronization unit 250.

First, the first sampling unit 220 delays the second clock rclk by the hold time Tsh of the first clock sclk, and outputs the first delay signal rclk_del0. The first and second flip-flops FF1 and FF2 are connected in series and operate in response to the first delay signal rclk_del0. The first flip-flop FF1 samples the prediction clock sclk_e in response to the first delay signal rclk_del0, and the second flip-flop FF2 outputs the output sclk_e_s0A of the first flip-flop FF1 to the first. The sampling is performed in response to the delay signal rclk_del0.

The second sampling unit 230 delays the second clock rclk by a time obtained by subtracting the setup type of the first clock sclk from the period Tr of the second clock rclk (or setup of the first clock sclk). A second delayer 232 for outputting a second delay signal rclk_del1 by advancing the second clock rclk by a time, and third and third devices connected in series to operate in response to the second delay signal rclk_del1. 4 flip-flops (FF3, FF4). The third flip-flop FF3 samples the prediction clock sclk_e in response to the second delay signal rclk_del1, and the fourth flip-flop FF4 receives the output sclk_e_s1A of the third flip-flop FF3 from the second flip-flop FF3. Sampling in response to a delay signal.

The first and second sampling units 220 and 230 of FIG. 8 are blocks corresponding to the first and second sampling units 20 and 30 shown in FIG. 2. However, since the first and second delay signals rclk_del0 and rclk_del1 are asynchronous with the prediction clock sclk_e, the synchronization scheme of the double-latch concept in which the storage devices FF1, FF2, FF3, and FF4 are connected in series is used. To use.

Meanwhile, as shown in FIG. 2, the detector 240 may detect whether the synchronization has failed by comparing the sampled results sclk_e_s0B and sclk_e_s1B of the first and second sampling units 220 and 230. However, in the example illustrated in FIG. 8, after the first and second sampling results sclk_e_s0B and sclk_e_s1B are synchronized with the second clock rclk through the fifth to eighth flip-flops FF5, FF6, FF7, and FF8. Detect synchronization failure. Explain why. In FIG. 8, the first sampling unit 220 is in the first clock domain Domain 1, and the second sampling unit 230 is in the second clock domain Domain 2. However, since the synchronization failure is determined by the synchronization failure detection unit 240 of the third domain region 3 operating with the second clock rclk, the first and second sampling units which are inputs of the synchronization failure detection unit 240 are provided. Each sampling result (sclk_e_s0B, sclk_e_s1B) of (220, 230) is preferably synchronized to the second clock (rclk). Synchronizing each of the sampling results sclk_e_s0B and sclk_e_s1B of the first and second sampling units 220 and 230 to the second clock rclk may be performed by transferring between different clock domains (Domain 1, Domain 3, and Domain 2). This is to reduce the probability of synchronization failure due to Domain 3).

Accordingly, the detection unit 240 includes the fifth to eighth flip-flops FF5, FF6, FF7, and FF8 in a double-latch-type synchronization manner similar to the first and second sampling units 220 and 230. . The sixth and eighth flip-flops FF6 and FF8 sample the outputs sclk_e_S02A and sclk_e_S12A of the fifth and seventh flip-flops FF5 and FF7, respectively, in response to the second clock rclk.

The detection unit 240 includes an AND operator, and compares the outputs sclk_e_S02B and sclk_e_S12B of the sixth and eighth flip-flops FF6 and FF7, and fails to synchronize the first and second clocks sclk and rclk. Detect whether or not. If the outputs sclk_e_S02B and sclk_e_S12B of the sixth and eighth flip-flops FF6 and FF7 are different from each other, that is, the sampling results of the first and second sampling units 220 and 230 are different from each other, the detector 240 It is determined that synchronization has failed. If the outputs sclk_e_S02B and sclk_e_S12B of the sixth and eighth flip-flops FF are the same, that is, the sampling results of the first and second sampling units 220 and 230 are the same, the detection unit 240 fails to synchronize. Judging by For example, in case of a synchronization failure, sclk_e_S02B in FIG. 8 corresponds to a signal '1' sampled after sclk rising in FIG. 3 (c), and sclk_e_S12B is a signal (') sampled before sclk rising in FIG. 3 (c). 0 '). Through the AND gate using these two signals, it is possible to determine whether synchronization has failed.

If not, it means that the first and second clock (sclk, rclk) is synchronized, the synchronization unit 250 samples the data (data) to the second clock (rclk) and receives.

If the synchronization fails, the first and second clocks sclk and rclk are not synchronized, and the synchronization unit 250 sets the second clock rclk for a predetermined time, for example, setting up the first clock sclk. Delay by the time Tss plus the hold time Tsh. In other words, data can be stably received by sampling and receiving data with a signal rclk_del2 that has undergone the maximum delay that can be avoided in case of synchronization failure.

As shown in FIG. 8, the synchronizer 250 includes a third delay unit 252, a ninth flip-flop FF9, a tenth flip-flop FF10, and a selector 254.

The third delay unit 252 outputs the signal rclk_del2 by delaying the second clock rclk by a time obtained by adding the setup time Tss and the hold time Tsh of the first clock sclk. The ninth flip-flop FF9 samples the data with the second clock rclk. The tenth flip-flop FF10 samples the data with the signal rclk_del2 delayed by the third delay unit 252. The selector 254 selects any one of the ninth flip-flop FF9 and the tenth flip-flop FF10 according to the output SF of the detector 240, and outputs sampled data data_s.

The synchronizer 210 has a total of one flip-flop (FF0, FF1) for the synchronization failure detection input and two flip-flops (FF2, FF4, FF5, and FF7) required for two double-latch synchronization). It is necessary to go through three pipelines in total to find out whether the current data has failed to synchronize. Therefore, when the synchronizer 210 illustrated in FIG. 8 is used in the sender 200, the sender 240 may predict whether the detection unit 240 fails to synchronize three cycles (3 cycles) based on the second clock rclk. The clock predictor 110 of 100 must generate a predicted clock sclk_e. Therefore, the fixed delay element 130 of the clock predictor delays by 3 * Tr.

9 is a circuit diagram illustrating a modification of the synchronization unit 250 of FIG. 8.

Referring to FIG. 9, according to a result of the synchronization failure, the synchronization unit 251 may set the second clock rclk by a time obtained by adding the setup time Tss and the hold time Tsh of the first clock sclk. A selection unit 254 for selecting any one of the signals rclk_del2 delaying the two clocks rclk, and an eleventh flip-flop FF11 for sampling data in response to any one of the selected signals. . The selection unit 258 may be configured as a mux.

Those skilled in the art will appreciate that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the claims and their equivalents should be construed as being included in the scope of the present invention.

1: synchronization failure detection circuit 10: synchronization system
20: first sampling unit 30: second sampling unit
40: detector 100: sender
200: receiver

Claims (20)

A synchronization system between heterogeneous periodic clock domains comprising a sender and a receiver operating in accordance with a first clock and a second clock of a heterogeneous period, respectively,
A sender configured to output a prediction clock obtained by delaying the first clock by a first time; And
A receiver for predicting synchronization failure between the first clock and the second clock by using the prediction clock and selectively delaying the second clock for a second time according to the prediction result to synchronize with the first clock
Synchronization system between heterogeneous cycle clock domain comprising a. The method of claim 1, wherein the sender
Detecting whether a synchronization failure between the predicted clock and the second clock occurs and predicting a predetermined time in advance than a time point at which an actual synchronization failure occurs between the first clock and the second clock;
Synchronization system between heterogeneous periodic clock domains. The method of claim 2,
The first time is determined according to the predetermined time to be predicted in advance
Synchronization system between heterogeneous periodic clock domains. The method of claim 1,
The sender includes a clock predictor for outputting the prediction clock,
The clock predictor
A variable delay element for delaying the first clock by a variable time in response to a feedback;
A fixed delay element for delaying the first clock delayed by the variable delay element by the time to be predicted in advance; And
Comprising a phase comparator for comparing the phase between the first clock and the output of the fixed delay element, and feeds back the comparison result to the variable delay element,
The variable delay element outputs a first clock delayed by the variable time to the predicted clock when the comparison result is the same phase.
Synchronization system between heterogeneous periodic clock domains. The method of claim 1, wherein the receiver
The prediction is performed by using a signal that delays the second clock by the hold time of the first clock and a signal that delays the second clock by a time obtained by subtracting the setup time of the first clock from the period of the second clock. And a synchronization failure detector for sampling clocks respectively and detecting whether synchronization between the first and second clocks has failed based on each sampling result.
Synchronization system between heterogeneous periodic clock domains. The method of claim 5, wherein the synchronization failure detector is
A first sampling unit sampling the predicted clock in response to a signal of delaying the second clock by a hold time of the first clock;
A second sampling unit configured to sample the prediction clock in response to a signal of delaying the second clock by a time obtained by subtracting a setup time of the first clock from a period of the second clock; And
And a detecting unit for detecting that the synchronization has failed when the sampling results of the first and second sampling units are different from each other.
Synchronization system between heterogeneous periodic clock domains. The method of claim 1, wherein the receiver
If it is predicted that the synchronization between the first and second clock has failed,
And a synchronizer for delaying the second clock by the sum of the hold time and the setup time of the first clock to synchronize the delayed second clock with the first clock.
Synchronization system between heterogeneous periodic clock domains. 8. The apparatus of claim 7, wherein the synchronizer
A first sampling unit configured to sample data output from the sender in synchronization with the first clock as the second clock;
A delay unit delaying the second clock by the sum of the hold time and the setup time of the first clock;
A second sampling unit for sampling the data with a second clock delayed by the delay unit; And
And a selection unit for selecting any one of data sampled by the first sampling unit and data sampled by the second sampling unit according to a prediction result of the synchronization failure.
Synchronization system between heterogeneous periodic clock domains. A synchronization device for performing synchronization between a first clock and a second clock of a heterogeneous period,
A first sampling unit configured to sample the predicted clock in response to a first delayed first clock received by a first time delayed prediction clock and delaying the second clock by a hold time of the first clock;
A second sampling unit configured to sample the prediction clock in response to a second delay signal that delays the second clock by a time subtracted from the setup time of the first clock by a period of the second clock;
A detector configured to sample the results sampled by the first and second sampling units with the second clock, respectively, and compare the results sampled with the second clock to detect whether synchronization between the first and second clocks has failed; And
A synchronization unit for selectively delaying the second clock by a second time and synchronizing with the first clock according to the detection result
Synchronizing device comprising a. The method of claim 9, wherein the synchronization unit
If it is predicted that the synchronization failure, the second clock delayed by the second time, the data received in synchronization with the first clock,
Receiving, as the second clock, data that is input in synchronization with the first clock when the synchronization is not expected to fail.
Synchronization device between heterogeneous periodic clock domains. The method of claim 10, wherein the synchronization unit
A third sampling unit for sampling the data with a second clock delayed by the second time;
A fourth sampling unit for sampling the data with the second clock; And
And a selection unit for selecting any one of outputs of the third and fourth sampling units according to the detection result.
Synchronization device between heterogeneous periodic clock domains. The method of claim 10, wherein the synchronization unit
A selector configured to select one of a second clock and a second clock delayed by the second time according to the detection result; And
And a third sampling unit for sampling the data in response to any one selected by the selection unit.
Synchronization device between heterogeneous periodic clock domains. 10. The method of claim 9,
The detector predicts a predetermined time in advance than a time point at which an actual synchronization failure occurs between the first clock and the second clock.
The first time is determined according to the predetermined time to be predicted in advance
Synchronization device between heterogeneous periodic clock domains. 10. The method of claim 9,
The second time is the sum of the hold time and the setup time of the first clock.
Synchronization device between heterogeneous periodic clock domains. In the synchronization failure detection circuit for detecting whether the synchronization failure between the first clock and the second clock,
A first sampling unit sampling the first clock in response to a first delayed signal delaying the second clock by a hold time of a first clock;
A second sampling unit configured to sample the first clock in response to a second delay signal that delays the second clock by a time obtained by subtracting a setup time of the first clock from a period of the second clock; And
A detector for detecting whether the results sampled by the first and second sampling units are different from each other
Synchronization failure detection circuit comprising a. The method of claim 15, wherein the detection unit
Detecting that synchronization between the first and second clocks fails when the results sampled by the first and second sampling units are different from each other.
Synchronization failure detection circuit. A method for receiving data from a first clock domain operating in accordance with a first clock to a second clock domain operating in accordance with a second clock at a period different from a period of the first clock, the method comprising:
Receiving a prediction clock from which the first clock is first delayed from the first clock domain; And
The prediction clock is used to predict whether or not the synchronization fails between the first clock and the second clock, and if it fails, delay the second clock by a second time, and respond to the second clock delayed by the second time. Steps to Sample Data
Method of receiving data from a heterocyclic clock domain comprising a. 18. The method of claim 17, wherein sampling the data comprises
Detecting whether a synchronization failure between the predicted clock and the second clock occurs, and predicting a predetermined time in advance than a time point at which an actual synchronization failure occurs between the first clock and the second clock;
Synchronization system between heterogeneous periodic clock domains. 18. The method of claim 17, wherein sampling the data comprises
First sampling the predicted clock in response to a first delayed signal that delayed the second clock by a hold time of the first clock;
Second sampling the predicted clock in response to a second delayed signal that delayed the second clock by a time subtracted from the setup time of the first clock by a period of the second clock; And
Comparing each sampling result of the first and second sampling steps, and predicting that synchronization fails between the first clock and the second clock in different cases;
Comprising
A method of receiving data from an heterocyclic clock domain. The method of claim 17,
The first time is determined according to the predetermined time to be predicted in advance,
The second time is the sum of the hold time and the setup time of the first clock.
Synchronization system between heterogeneous periodic clock domains.

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