KR20110010246A - Surge protective device using thyristor - Google Patents

Abstract

PURPOSE: A surge protector is provided to effectively execute a surge restriction function in a common mode and a differential mode by using a thyristor device. CONSTITUTION: A first surge protecting circuit prevent an excessive voltage from being applied to between a voltage line and a ground line by using a first and a second thyristor(S1,S2). The first surge protecting circuit includes a first or a fourth capacitor, a first or a third resistor, and a first and a second inductor. The first capacitor and the first resistor are connected to the cathode electrode of the first thyristor and the anode electrode of the second thyristor. A second surge protecting circuit prevents an excessive voltage from being applied to between a neutral line and a ground line by using a third and a fourth thyristor(S3,S4).

Description

Surge Protective Device Using Thyristor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surge protector, which uses a thyristor element such as a silicon controlled rectifier (SCR) to keep the limit voltage low and to resist noise and to perform excellent surge limit function in common mode and differential mode. To a surge protector.

Surge protectors are defined in KS C IEC 61643, also known as surge suppressors. Surge protectors are devices that attenuate transients or noise and provide low voltage (for example, AC 1000 V or less) power lines, telephone lines, and data. It is a device designed to attenuate dangerous transient voltages in very short moments in power lines and control lines connected to networks, CCTV circuits, cable TV circuits and electronic equipment. In other words, a surge protector is a device that prevents a destructive transient from reaching its installation (load). It does not reduce the surge voltage to '0', but the load can be safely tolerated. It is a device for attenuating surge.

If the system voltage is higher than the surge protector's rated voltage when the surge protector is installed, the surge protector attempts to suppress the system voltage, causing the inside to overheat and fail quickly. On the contrary, if the grid voltage is much lower than the surge protector's rated voltage, the equipment in the grid cannot expect the surge suppression effect of the surge protector. In addition, surge protector acts as a large impedance when the voltage across both ends is below the set limit voltage so that almost no current flows, but when the voltage exceeding the value is exceeded, the impedance suddenly decreases and a large current flows, so that the voltage is below a certain level. To maintain. If the applied system voltage is the same, such a low voltage surge protector is a good choice.

However, conventional surge protectors using only metal oxide varistors (MOVs) must have a rated voltage above the applied system voltage, so that the pulse waves used for voltage impulse testing in the IEC 61643-1 standard, ie wave front length ) When the pulse wave is applied at 1.2 μs and wave tail length of 50 μs, the limiting voltage tends to appear as high as 2-3 kV.

Accordingly, an object of the present invention is to solve the above-described problems, and an object of the present invention is to maintain a low limit voltage by using a thyristor element such as an SCR, and in addition, a load may be shorted in the event of a malfunction of the SCR. The present invention provides a surge protector with strong non-operational characteristics and excellent surge limiting function in common mode and differential mode.

First, to summarize the features of the present invention, a surge protector for preventing the input of the transient voltage to the voltage line, the neutral line, and the ground line according to an aspect of the present invention for achieving the above object, the first thyristor connected in opposite directions A first surge protection circuit for preventing input of transient voltages in opposite directions between the voltage line and the ground line by using a second thyristor; And a second surge protection circuit for preventing input of transient voltages in opposite directions between the neutral line and the ground line using the third and fourth thyristors connected in opposite directions.

The first surge protection circuit may include a first capacitor and a first resistor connected in series between the voltage line and the gate terminal of the first thyristor; A second capacitor and a first inductor connected in parallel between a first contact between the cathode electrode of the first thyristor and the anode electrode of the second thyristor and a gate terminal of the first thyristor; A third capacitor and a second resistor connected in series between the first contact point and the gate terminal of the second thyristor; A fourth capacitor and a second inductor connected in parallel between the voltage line and the gate terminal of the second thyristor; And a third resistor connected between the first contact point and the ground line, wherein the second surge protection circuit comprises: a fifth capacitor and a fourth resistor connected in series between the neutral line and the gate terminal of the third thyristor; A sixth capacitor and a third inductor connected in parallel between a second contact between the cathode electrode of the third thyristor and the anode electrode of the fourth thyristor and a gate terminal of the third thyristor; A seventh capacitor and a fifth resistor connected in series between the second contact point and the gate terminal of the fourth thyristor; An eighth capacitor and a fourth inductor connected in parallel between the neutral line and the gate terminal of the fourth thyristor; And a sixth resistor connected between the second contact point and the ground line.

The first thyristor, the second thyristor, the third thyristor, and the fourth thyristor are SCRs.

The grid voltage to the voltage line or the neutral line is low voltage (for example, AC 1000V or less) and is generally single-phase 220Vrms or three-phase 380Vrms in Korea.

The first surge protection circuit and the second surge protection circuit are deactivated even when a pulse wave of 4 kV is applied to an EFT (Electrical Fast Transient) waveform having a wave length of 5 ns and a wave length of 50 ns.

The limiting voltages of the first surge protection circuit and the second surge protection circuit are suppressed to within 1 kV even when a voltage of 20 kV is applied to a standard brain impulse voltage waveform having a wavelength of 1.2 µs and a wavelength of 50 µs.

Connect one terminal of the first inductor to the voltage line inlet, connect the other terminal of the first inductor to the voltage line of the first surge protection circuit, and connect the one terminal of the second inductor to the neutral line inlet; The other terminal of the second inductor may be connected to the neutral line of the surge protection circuit.

A first MOV connected between the voltage line lead-in and the neutral line lead-in; A second MOV connected between the voltage line lead and the ground line; And a third MOV connected between the neutral lead portion and the ground line.

According to the surge protector according to the present invention, it is possible to keep the limit voltage low by using a thyristor element such as SCR, to improve the malfunction characteristic due to the noise of the SCR, and to provide excellent surge limit function in the common mode and the differential mode. Can be done.

       In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view for explaining a circuit for a surge protector 10 according to an embodiment of the present invention.

Referring to FIG. 1, a surge protector 10 according to an embodiment of the present invention includes varistors MOV1, MOV2, and MOV3, inductors L _CM1 and L _CM2 , a first surge protection circuit 11, and a first surge protector 11. Two surge protection circuits 12. MOV is a metal-oxide-varistor.

Important components of the surge protector 10 according to an embodiment of the present invention are the first surge protection circuit 11 and the second surge protection circuit 12, but the inductor L _CM1 is connected to the voltage line inlet L. One terminal may be connected, and the other terminal of the inductor L _CM1 may be connected to the voltage line terminal (load side L) of the first surge protection circuit 11, and one terminal of the inductor L _CM2 may be connected to the neutral lead N. The other terminal of the inductor L _CM2 may be connected to the neutral terminal (load side N) of the second surge protection circuit 12. In addition, between the voltage line lead-in part L and the neutral line lead-in part N, the first MOV (MOV1), the second MOV (MOV2) and the neutral line lead-in part N between the voltage line lead-in part L and the ground line G. The third MOV MOV3 may be connected between the ground line G and the ground line G to prevent the load from the transient voltage input through the inlets L, N, and G. FIG. In some cases, the above varistors MOV1, MOV2, and MOV3 or inductors L _CM1 and L _CM2 may not be used.

Even without using the varistors (MOV1, MOV2, MOV3) or inductors (L _CM1 , L _CM2 ) as described above, simply using the first surge protection circuit 11 and the second surge protection circuit 12 which are important elements of the present invention. The input of the transient voltage to the load side can also be prevented. By connecting the first surge protection circuit 11 between the voltage line lead-in (L) and the ground line (G), it is possible to prevent the input of the transient voltage to the load-side voltage line terminal and the ground line, the neutral line lead (N) and the ground line (G) The second surge protection circuit 12 may be connected between the input of the transient voltage to the load-side neutral terminal and the ground line.

The first surge protection circuit 11 can prevent the input of the transient voltage between the load side voltage line terminal L and the ground line G by using a pair of thyristors S1 and S2. In addition, the second surge protection circuit 12 can prevent the input of the transient voltage between the load-side neutral line terminal N and the ground line G by using a pair of thyristors S3 and S4. The pair of thyristors S1 and S2 of the first surge protection circuit 11 are connected in parallel with opposite polarities so that a transient voltage of positive polarity and negative polarity is input to the load side voltage line terminal L and the ground line G. It is composed of a structure that can sufficiently protect the load. In addition, a pair of thyristors S3 and S4 of the second surge protection circuit 12 are also connected in opposite directions, so that positive and negative transient voltages are input to the load-side neutral line terminal N and the ground line G. Even if it is, the load can be sufficiently protected from the transient voltage.

The thyristors S1, S2, S3, and S4 may be silicon controlled rectifiers (SCRs), and in some cases, may use a triac, a diac, or the like.

The first surge protection circuit 11 may include a first thyristor S1, a second thyristor S2, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4), a first resistor R1, a second resistor R2, a third resistor R3, a first inductor L1, and a second inductor L2.

The second surge protection circuit 12 is similar to the first surge protection circuit 11, and has a third thyristor S3, a fourth thyristor S4, a fifth capacitor C5, and a sixth capacitor C6. , The seventh capacitor C7, the eighth capacitor C8, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the third inductor L3, and the fourth inductor L4 It includes.

In the first surge protection circuit 11, the first capacitor C1 and the first resistor R1 are connected in series between the load-side voltage line terminal L and the gate terminal of the first thyristor S1. The second capacitor C2 and the first inductor L1 may have a gate of the first contact point and the first thyristor S1 to which the cathode electrode of the first thyristor S1 and the anode electrode of the second thyristor S2 are connected. It is connected in parallel between the terminals. The third capacitor C3 and the second resistor R2 are connected in series between the first contact point and the gate terminal of the second thyristor S2. The fourth capacitor C4 and the second inductor L2 are connected in parallel between the load-side voltage line terminal L and the gate terminal of the second thyristor S2. The third resistor R3 is connected between the first contact point and the ground line G.

In the second surge protection circuit 12, the fifth capacitor C5 and the fourth resistor R4 are connected in series between the load-side neutral terminal N and the gate terminal of the third thyristor S3. The sixth capacitor C6 and the third inductor L3 have a gate of the second contact point and the third thyristor S3 to which the cathode electrode of the third thyristor S3 and the anode electrode of the fourth thyristor S4 are connected. It is connected in parallel between the terminals. The seventh capacitor C7 and the fifth resistor R5 are connected in series between the second contact point and the gate terminal of the fourth thyristor S4. The eighth capacitor C8 and the fourth inductor L4 are connected in parallel between the load-side neutral terminal N and the gate terminal of the fourth thyristor S4. The sixth resistor R6 is connected between the second contact point and the ground line G.

As described above, the first surge protection circuit 11 and the second surge protection circuit 12 are subjected to any transient voltage such as a common mode or a differential mode to the load-side voltage line terminal L, the neutral terminal N, and the ground line terminal G. In response, the load can be protected. Even when varistors MOV1, MOV2, MOV3 or inductors L _CM1 , L _CM2 are used, the varistors MOV1, MOV2, A decrease in the resistance of MOV3) can attenuate the transient voltage, but there is still a high residual voltage, even when the varistors MOV1, MOV2, MOV3 or inductors L _CM1 , L _CM2 have insufficient operation. The protection circuit 11 and the second surge protection circuit 12 operate to generate 220Vrms system voltage to the voltage line lead-in part L or the neutral line lead-in part N, or to the first ETF (Electrical Fast Transient) waveform as shown in FIG. Although the surge protection circuit 11 and the second surge protection circuit 12 are deactivated, the surge protection circuit 11 and the second surge protection circuit 12 are inactivated to operate at a predetermined transient voltage (see FIG. 4) to protect the load. Here, C1 and R1 are primarily used to limit the gate current of SCR (S1), and C1 is selected to satisfy the leakage current limit condition of the system. For SCR (S2), select C3 and R2 to satisfy the leakage current limit conditions of the system as above.

For example, when a 220 Vrms grid voltage is applied between the lead LG or NG in a steady state, the first surge protection circuit 11 and the second surge protection circuit 12 are deactivated. By designing L1 and C2 of the first surge protection circuit 11 to satisfy the condition as shown in [Equation 1], the trigger to be applied to the gate of the thyristor S1 when the 220Vrms system voltage is input through the inlet LG. The current is bypassed through L1 to deactivate the thyristor S1. In Equation 1, Z _L1 is the impedance of L1, Z _C2 is the impedance of C2, and R _GK is the internal resistance between the gate and the cathode of the thyristor.

[Equation 1]

Z _L1 << R _GK << Z _C2

In addition, similarly, when the 220Vrms system voltage is input to the opposite phase through the inlet LG, the thyristor is designed such that L2 and C4 of the first surge protection circuit 11 are determined in a manner similar to that of [Equation 1]. The trigger current to be applied to the gate of S2 may be bypassed through L2 to deactivate the thyristor S2. In addition, when 220Vrms system voltage is input through the inlet NG, L3 and C6 of the second surge protection circuit 12 are designed to be determined in a manner similar to [Equation 1], thereby applying it to the gate of the thyristor S3. The trigger current to be bypassed through L3 may cause the thyristor S3 to be deactivated, and when the 220Vrms grid voltage is input in the opposite phase through the inlet NG, L4 of the second surge protection circuit 12 And by designing C8 to be determined in a manner similar to [Equation 1], the trigger current to be applied to the gate of the thyristor S4 is bypassed through L4 so that the thyristor S4 is inactivated.

In addition, when the EFT (Electrical Fast Transient) waveform shown in FIG. 2 is applied between the inlets LG, LN, or NG, the first surge protection circuit 11 and the second surge protection circuit 12 are also deactivated. . As shown in FIG. 3, which shows a detailed waveform for one pulse of FIG. 2, the EFT waveform is a pulse wave with an amplitude of 4 kV (or less) and a 5 kHz period, having a wavelength of 5 ns (or less) and a wave. 50ns (or less) long. When the EFT waveform as shown in FIG. 2 is input through the inlet LG, the L1 and C2 of the first surge protection circuit 11 are designed to satisfy the condition as shown in [Equation 2] to be applied to the gate of the thyristor S1. Trigger current is bypassed through C2 to disable thyristor S1.

[Equation 2]

Z _C2 << R _GK << Z _L1

In addition, similarly, when the EFT waveform is input to the opposite phase through the inlet portion LG, L2 and C4 of the first surge protection circuit 11 are designed to be determined in a manner similar to [Equation 2], thereby the thyristor S2. The trigger current to be applied to the gate of may be bypassed through C4 to cause the thyristor S2 to be deactivated. Further, when the EFT waveform is input through the inlet NG, the L3 and C6 of the second surge protection circuit 12 are designed to be determined in a manner similar to that of [Equation 2], whereby a trigger to be applied to the gate of the thyristor S3. The trigger current can be bypassed through C6 to cause the thyristor S3 to be deactivated. When the EFT waveform is input to the opposite phase through the inlet NG, L4 and C8 of the second surge protection circuit 12 By designing to be determined in a manner similar to Equation 2, the trigger current to be applied to the gate of the thyristor S4 can be bypassed through C8 so that the thyristor S4 is inactivated.

4 is a waveform of a pulse wave used in a voltage impulse test for a surge state.

As shown in Fig. 4, in the voltage impulse test for the surge state of IEC 61643-1, pulse waves having a wave length of 1.2 μs and a wave length of 50 μs are used. The wave length is a time Tf corresponding to 1.67 times the time T1 between 0.3 and 0.9 of the peak voltage Vpk, which is about 1.2 μs. The wave length is the time when the tangent of 0.3 Vpk reaches 0.5 Vpk from the time axis intercept. ) Is about 50 μs.

In experiments with such surge pulses, it was confirmed that the limit voltages of the first surge protection circuit 11 and the second surge protection circuit 12 appear within 1 kV when an impulse of 20 kV was applied. For example, when an impulse having an amplitude of 1 kV or more is applied between the inlets L-G or N-G, the first surge protection circuit 11 and the second surge protection circuit 12 are activated to protect the load. For example, by designing L1 and C2 of the first surge protection circuit 11 to satisfy the condition as shown in [Equation 3], the impulse waveform as shown in FIG. 3 having an amplitude of 1 kV or more can be input through the inlet LG. At this time, the triggering current is introduced into the gate of the thyristor S1 to activate the thyristor S1 to pass most of the voltage and current to the ground and to prevent the transient voltage flowing to the load. At this time, R3 protects SCR by limiting excessive short-circuit current because instantaneous short circuit is formed during SCR conduction.

&Quot; (3) &quot;

R _GK ≒ Z _L1 << Z _C2

Similarly, when the impulse waveform as shown in FIG. 3 having an amplitude of 1 kV or more is input to the opposite phase through the inlet portion LG, L2 and C4 of the first surge protection circuit 11 are similar to the equation (3). By designing the circuit, the triggering current is introduced into the thyristor S2 gate, thereby activating the thyristor S2 to pass most of the voltage and current to the ground and to prevent the transient voltage flowing to the load. In addition, when an impulse waveform like FIG. 3 having an amplitude of 1 kV or more is input through the inlet NG, L3 and C6 of the second surge protection circuit 12 are designed to be determined in a manner similar to [Equation 3], The triggering current is introduced into the gate of the thyristor S3 to enable the thyristor S3 to pass most of the voltage and current to the ground and to prevent the transient voltage flowing into the load, and having an amplitude of 1 kV or more through the inlet NG. When an impulse waveform such as is input to the opposite phase, by designing L4 and C8 of the second surge protection circuit 12 to be determined in a manner similar to [Equation 3], the triggering current enters the gate of the thyristor S4. This enables the thyristor S4 to pass most of the voltage and current to ground and to prevent transient voltages flowing into the load.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a view for explaining a circuit for a surge protector according to an embodiment of the present invention.

2 shows an EFT waveform.

3 is a detailed waveform of one pulse wave of FIG. 2.

4 is a waveform of a pulse wave used in a voltage impulse test for a surge state.

Claims (7)

In the surge protector which prevents the input of the transient voltage to the voltage line, the neutral line, and the ground line, A first surge protection circuit for preventing input of a transient voltage between the voltage line and the ground line by using a first thyristor and a second thyristor connected in opposite directions; And A second surge protection circuit for preventing input of a transient voltage between the neutral line and the ground line by using a third and fourth thyristor connected in opposite directions to each other; Surge protector comprising a. The method of claim 1, wherein the first surge protection circuit, A first capacitor and a first resistor connected in series between the voltage line and the gate terminal of the first thyristor; A second capacitor and a first inductor connected in parallel between a first contact between the cathode electrode of the first thyristor and the anode electrode of the second thyristor and a gate terminal of the first thyristor; A third capacitor and a second resistor connected in series between the first contact point and the gate terminal of the second thyristor; A fourth capacitor and a second inductor connected in parallel between the voltage line and the gate terminal of the second thyristor; And A third resistor connected between the first contact point and the ground line; The second surge protection circuit, A fifth capacitor and a fourth resistor connected in series between the neutral line and the gate terminal of the third thyristor; A sixth capacitor and a third inductor connected in parallel between a second contact between the cathode electrode of the third thyristor and the anode electrode of the fourth thyristor and a gate terminal of the third thyristor; A seventh capacitor and a fifth resistor connected in series between the second contact point and the gate terminal of the fourth thyristor; An eighth capacitor and a fourth inductor connected in parallel between the neutral line and the gate terminal of the fourth thyristor; And And a sixth resistor connected between the second contact point and the ground line. The surge protector of claim 1, wherein the first thyristor, the second thyristor, the third thyristor, and the fourth thyristor are SCRs. The method of claim 1, wherein the first surge protection circuit and the second surge protection circuit, Surge protector, which is deactivated for pulse waves within 4 kV of wave length 5 ns and wave length 50 ns. The surge protector according to claim 1, wherein the limit voltages of the first surge protection circuit and the second surge protection circuit are within 1 kV when a pulse wave of 20 kV having a wavelength of 1.2 µs and a wavelength of 50 µs is applied. The method of claim 1, Connect one terminal of the first inductor to a voltage line inlet and the other terminal of the first inductor to the voltage line of the first surge protection circuit; And a terminal of one side of the second inductor connected to the neutral lead and a second terminal of the second inductor connected to the neutral of the second surge protection circuit. The method of claim 6, A first MOV connected between the voltage line lead-in and the neutral line lead-in; A second MOV connected between the voltage line lead and the ground line; And A third MOV connected between the neutral lead and the ground lead Surge protector, characterized in that it further comprises.

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