KR20110001806A - Semiconductor comprising recess gate and method of forming the same - Google Patents

Semiconductor comprising recess gate and method of forming the same Download PDF

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Publication number
KR20110001806A
KR20110001806A KR1020090059511A KR20090059511A KR20110001806A KR 20110001806 A KR20110001806 A KR 20110001806A KR 1020090059511 A KR1020090059511 A KR 1020090059511A KR 20090059511 A KR20090059511 A KR 20090059511A KR 20110001806 A KR20110001806 A KR 20110001806A
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KR
South Korea
Prior art keywords
gate
forming
recess
active region
semiconductor substrate
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Application number
KR1020090059511A
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Korean (ko)
Inventor
이승진
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주식회사 하이닉스반도체
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Priority to KR1020090059511A priority Critical patent/KR20110001806A/en
Publication of KR20110001806A publication Critical patent/KR20110001806A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a recess gate and a method of forming the same, and particularly, to prevent a bridge between recess gates occurring at an end of the recess gate structure in a cell region, thereby preventing the recess gate. The present invention relates to a semiconductor device including a recess gate capable of increasing a process yield of a recess gate or a saddle fin transistor, and a method of forming the same.

A semiconductor device including a recess gate of the present invention and a method of forming the same include: forming an isolation layer defining an active region in a semiconductor substrate; Forming a dummy active region at an end of the cell region in the semiconductor substrate; And forming a gate structure on the semiconductor substrate, wherein an end portion of the gate structure is formed to be located in the dummy active region.

Description

A semiconductor device including a recess gate, and a method of forming the same {SEMICONDUCTOR COMPRISING RECESS GATE AND METHOD OF FORMING THE SAME}

The present invention relates to a semiconductor device including a recess gate and a method of forming the same. More particularly, the present invention relates to a semiconductor device including a recess gate formed in a structure in which a substrate is recessed a predetermined depth in a semiconductor substrate including an active region and an isolation layer.

The DRAM of the semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor. Among them, a capacitor is used for temporarily storing data, and a transistor is used for transferring data between a bit line and a capacitor corresponding to a control signal (word line) by using the property of a semiconductor whose electrical conductivity changes according to an environment. A transistor consists of three regions: a gate, a source, and a drain. A charge is transferred between the source and the drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When a conventional transistor is formed on a semiconductor substrate, a gate is formed on a semiconductor substrate and doping is performed on both sides of the gate to form a source and a drain. In this case, between the source and the drain under the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a semiconductor substrate of a certain area. In the case of a complicated semiconductor memory device, it is difficult to reduce the total area due to a plurality of transistors included in the semiconductor memory device.

By reducing the total area of the semiconductor memory device, the number of semiconductor memory devices that can be produced per wafer can be increased and productivity is improved. Various methods have been proposed to reduce the total area of the semiconductor memory device. A recess in which a channel is formed along a curved surface of the recess by forming a recess in the substrate and forming a gate in the recess in place of a conventional planar gate, in which one of them has a horizontal channel region. Is to use a gate.

1 is a plan view illustrating a semiconductor device including a conventional recess gate. Referring to FIG. 1, a plurality of active regions 10 and an isolation region 20 defining the active regions are formed in a semiconductor substrate. In addition, a plurality of gate structures 30 are formed in a direction perpendicular to the active region 10 so that two gate structures 30 are formed in one active region 10.

The semiconductor substrate shown in FIG. 1 indicates a right end portion in a cell region, and a peripheral region may be formed on the right side of the semiconductor substrate shown in FIG. 1.

As shown in FIG. 1, the gate structure 30 is provided with an end 35 at a point that does not endlessly extend and ends at an end of the cell region. However, since the plurality of active regions 10 are formed in a zigzag shape, the end 35 of the gate structure 30 may be adjacent to the active region 10 (first, second, fifth and sixth from above in FIG. 1). While there is a gate structure, there is a portion (third, fourth, seventh, and eighth gate structures from above in FIG. 1) formed at a predetermined distance from the active region 10.

Referring to FIG. 2, which is a cross-sectional view along the AA ′ line in FIG. 1, that is, a cross section of the semiconductor substrate at the end side of the gate structure 30, the gate structure 30 is not formed on the surface of the substrate but is formed on the substrate. It can be seen that it is formed in the portion recessed to a predetermined depth, and this gate is the recess gate described above.

In FIG. 2, the recess gate structure 30 formed in the active region 10 is stably formed without the bridge gates being bridged with each other, but the recess gate structure formed in the device isolation layer 20 is formed. 30 may confirm that the adjacent gate structure 30 and the bridge are generated.

This is because in the process of etching the recess in which the recess gate structure 30 is to be formed, the device isolation layer 20, which is an oxide material, may be etched deeper than the silicon active region 10. Because it can. In the process of etching a recess to form the gate structure 30, the portion corresponding to the end 35 (see FIG. 1) of the gate structure 30 has a greater risk of over-etching than other portions. It is a door.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. In the semiconductor substrate, a dummy active region is formed at the end of the cell region, and the end of the recess gate structure is positioned in the dummy active region, thereby providing Recesses that can prevent the recess gate-to-recess bridges occurring at the end of the recess gate structure in the recess gate, thereby increasing the process yield of the recess gate or saddle fin transistor An object of the present invention is to provide a semiconductor device including a gate and a method of forming the same.

In order to achieve the above object, the present invention comprises the steps of forming an isolation layer defining an active region on the semiconductor substrate; Forming a dummy active region at an end of the cell region in the semiconductor substrate; And forming a gate structure in the semiconductor substrate, wherein an end of the gate structure is formed to be located in the dummy active region, so that an inter-recess gate bridge is formed at an end of the recess gate structure in a cell region. The phenomenon can be prevented.

Further, the device isolation film may include an oxide film, and the dummy active region may include silicon to prevent excessive etching of the device isolation film including an oxide film having a high etching selectivity.

In addition, the dummy active region may provide an advantageous effect in terms of forming a layout of the active region when the dummy active region is formed only at a position corresponding to a part of the end of the gate structure.

And forming the gate structure, forming a recess in the semiconductor substrate; Forming a gate conductive layer in the recess; Forming a barrier metal layer on the gate conductive layer; Forming a gate hard mask layer on the barrier metal layer; And etching the stacked structure including the gate conductive layer, the barrier metal layer, and the gate hard mask.

Furthermore, after etching the stacked structure including the gate conductive layer, the barrier metal layer, and the gate hard mask, the method may further include forming a gate spacer on the side of the gate structure, thereby protecting the side of the gate structure. do.

On the other hand, the semiconductor device including a recess gate according to the present invention, an isolation layer formed on the substrate to define an active region; A dummy active region formed at an end of a cell region in the semiconductor substrate; And a gate structure formed on the semiconductor substrate and having an end portion positioned in the dummy active region, to prevent a bridge between recess gates occurring at an end portion of the recess gate structure in the cell region. It is characterized by.

Further, the device isolation film may include an oxide film, and the dummy active region may include silicon to prevent excessive etching of the device isolation film including an oxide film having a high etching selectivity.

In addition, the dummy active region may be formed only at a position corresponding to a part of the end of the gate structure, thereby providing an advantageous effect in terms of forming a layout of the active region.

Further, the gate structure may include a gate conductive layer formed in a recess formed in the semiconductor substrate; A barrier metal layer formed on the gate conductive layer; The gate hard mask layer may be formed on the barrier metal layer. The gate hard mask layer may further include a gate spacer formed on side surfaces of the gate conductive layer, the barrier metal layer, and the gate hard mask layer.

The semiconductor device including the recess gate of the present invention and a method of forming the same may prevent a bridge between recess gates occurring at the end of the recess gate structure in the cell region, thereby preventing the recess gate. Alternatively, it provides an effect of increasing the process yield of the saddle fin transistor.

Hereinafter, an exemplary embodiment of a semiconductor device including a recess gate and a method of forming the same will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a semiconductor device including a recess gate according to the present invention. Referring to FIG. 3, a plurality of active regions 10 and an isolation region 20 defining the active regions are formed in a semiconductor substrate. In addition, a plurality of gate structures 30 are formed in a direction perpendicular to the active region 10 so that two gate structures 30 are formed in one active region 10.

The semiconductor substrate illustrated in FIG. 3 represents a right end portion in a cell region, and a peripheral region may be formed on the right side of the semiconductor substrate illustrated in FIG. 3.

In the semiconductor device according to the present invention, a plurality of dummy cell regions 12 are formed at a portion where an end portion of the recess gate structure 30 is formed at an end portion of the cell region. Since the dummy cell region 12 does not operate as a transistor like the actual cell region 10, a junction region such as a source / drain is not formed, but the dummy cell region 12 is a region formed of the same material and structure as the cell region 10. . The dummy cell region 12 is configured to prevent an end portion of the recess gate structure 30 from being excessively etched to generate a bridge between the recess gate structures 30.

When the dummy cell region 12 is formed at the end of the cell region, the end 35 of the recess gate structure 30 is formed in the dummy cell region 12 made of silicon (Si) instead of the oxide layer (SiOx). Because of the location, no excessive etching occurs in the process of forming a recess at the end of the gate structure 30.

Meanwhile, in FIG. 3, the dummy active region 12 is not formed at the end of the entire gate structure 30, but is formed only at a portion of the end 35 of the gate structure 30. In this case, the dummy active region 12 is formed. Since it is arranged in a regular pattern with the other active region 10, it is convenient in terms of forming the layout of the active regions 10, 12. However, although not shown in the drawing, in terms of preventing the bridge of the recess gate, the dummy active region 12 is most preferably formed to include the ends 35 of all the gate structures 30.

And in the embodiment shown in FIG. 3, the ends of the gate structures 30 (the first, second, fifth and sixth gate structures from above in FIG. 3) of the portion where the dummy cell region 12 is not formed are adjacent to each other. Since the gap is formed at a sufficient distance from the active region 10, the bridge between the recess gates does not easily occur during the recess etching.

Next, referring to FIG. 4, which is a cross-sectional view along the line BB 'of FIG. 3, the gate structure 30 is a recess gate structure in which a gate structure 30 is formed at a portion recessed to a predetermined depth from the surface of the semiconductor substrate. It can be confirmed that it is formed. The gate structure 30 includes a gate conductive layer 31 formed at a lower portion thereof, a barrier metal layer 32 formed at an upper portion thereof, and a gate hard mask 33 formed at an upper portion thereof to protect side surfaces of the gate materials. It is preferable that the gate spacer 34 is formed in a side structure.

In addition, although not separately illustrated in the drawings of the present invention, when the transistor of the semiconductor device is formed in a 'saddle fin' structure, the present invention may effectively prevent the bridge between gates.

The saddle fin transistor has a cross section in the longitudinal direction (vertical direction in FIGS. 1 and 3) of the active region, in which the gate region is etched downward from the substrate surface in the same manner as the recess gate, and in the longitudinal direction of the active region. In the vertical direction (the horizontal direction in FIGS. 1 and 3), the isolation layer 20 is recessed to a predetermined depth so that the active region 10 refers to a transistor structure having a structure protruding from the isolation layer 20 ( In the case of the saddle fin transistor, the length direction of the active region is the same as that of the recess gate, so the structure shown in FIGS. 3 and 4 of the present invention is shown).

Since the saddle fin transistor includes a process of etching an oxide film (element isolation layer) in addition to the process of etching the silicon substrate when the recess gate structure 30 is formed, the gate structure 30 at the end 35 of the gate structure 30. It is easier to see the bridges bridged together.

That is, the semiconductor device and the recess gate forming method according to the present invention can provide an effect of preventing the gate-to-gate bridge even when applied to not only the recess gate structure but also the saddle fin transistor structure.

As described above, the method for forming a recess gate of a semiconductor device according to the present invention comprises forming a dummy active region at an end portion of a cell region in a semiconductor substrate and having an end portion of the recess gate structure at this dummy active region. It is possible to prevent the inter-recess gate bridge phenomenon occurring at the end of the recess gate structure in the cell region, thereby increasing the process yield of the recess gate or saddle fin transistor. Can provide a beneficial effect.

The present invention is not limited to the described embodiments, and various modifications and changes can be made to those skilled in the art without departing from the spirit and scope of the present invention. Such modifications or modifications may be made to the present invention. It belongs to the scope of claims.

1 is a plan view showing a semiconductor device including a conventional recess gate;

2 is a cross-sectional view along the line AA ′ in FIG. 1;

3 is a plan view showing a semiconductor device including a recess gate according to the present invention; And,

4 is a cross-sectional view taken along line BB ′ in FIG. 3.

<Explanation of symbols for the main parts of the drawings>

10: active area 12: dummy active area

20 device isolation layer 30 gate structure

31: gate conductive layer 32: barrier metal layer

33: gate hard mask 34: gate spacer

35: end

Claims (10)

Forming an isolation layer defining an active region on the semiconductor substrate; Forming a dummy active region at an end of a cell region in the semiconductor substrate; And Forming a gate structure on the semiconductor substrate, And an end portion of the gate structure is positioned in the dummy active region. The method according to claim 1, The device isolation film includes an oxide film, And the dummy active region comprises silicon. The method according to claim 1, The dummy active area is, And forming a recess gate only at a position corresponding to a part of the end of the gate structure. The method according to claim 1, Forming the gate structure, Forming a recess in the semiconductor substrate; Forming a gate conductive layer in the recess; Forming a barrier metal layer on the gate conductive layer; Forming a gate hard mask layer on the barrier metal layer; Etching the stacked structure including the gate conductive layer, the barrier metal layer, and the gate hard mask. Recess gate forming method of a semiconductor device comprising a. The method according to claim 4, After etching the stacked structure including the gate conductive layer, the barrier metal layer, and the gate hard mask, And forming a gate spacer on a side surface of the gate structure. An isolation layer formed on the semiconductor substrate to define an active region; A dummy active region formed at an end of a cell region in the semiconductor substrate; And A gate structure formed on the semiconductor substrate and having an end portion located in the dummy active region A semiconductor device comprising a recess gate comprising a. The method according to claim 6, The device isolation film includes an oxide film, And a recess gate, wherein the dummy active region comprises silicon. The method according to claim 6, The dummy active area is, And a recess gate formed only at a position corresponding to a part of the ends of the gate structure. The method according to claim 6, The gate structure, A gate conductive layer formed in a recess formed in the semiconductor substrate; A barrier metal layer formed on the gate conductive layer; A gate hard mask layer formed on the barrier metal layer; A semiconductor device comprising a recess gate comprising a. The method according to claim 9, And a gate spacer formed on side surfaces of the gate conductive layer, the barrier metal layer, and the gate hard mask layer.
KR1020090059511A 2009-06-30 2009-06-30 Semiconductor comprising recess gate and method of forming the same KR20110001806A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105467B2 (en) 2013-09-26 2015-08-11 Samsung Electronics Co., Ltd. Dummy cell array for fin field-effect transistor device and semiconductor integrated circuit including the dummy cell array
KR20230064512A (en) 2021-11-03 2023-05-10 아프로비에이 주식회사 Heating device for sock and sock including such an heating device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105467B2 (en) 2013-09-26 2015-08-11 Samsung Electronics Co., Ltd. Dummy cell array for fin field-effect transistor device and semiconductor integrated circuit including the dummy cell array
KR20230064512A (en) 2021-11-03 2023-05-10 아프로비에이 주식회사 Heating device for sock and sock including such an heating device

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