KR20100135100A - Method for manufacturing photomask - Google Patents

Abstract

PURPOSE: A method for manufacturing a photomask is provided to effectively suppress photomask defect generation by foreign material adsorption. CONSTITUTION: A method for manufacturing a photomask comprises: a step of forming a phase shift layer(210), optical shield layer(230) and first resist layer on a substrate(100); a step of forming a second resist pattern(333); a step of transferring a pattern layout to the first resist layer to form a first resist layer pattern; a step of selectively etching a part of the shift layer and optical shield layer; and a step of selectively removing the second and first resist layer pattern.

Description

Photomask manufacturing method {Method for manufacturing photomask}

TECHNICAL FIELD The present invention relates to lithography technology, and more particularly, to a method of manufacturing a photomask.

In order to implement a circuit line width of a semiconductor device on a wafer, a lithography process of pattern transfer using an exposure apparatus is performed. In such a lithography process, a process of manufacturing a photomask having a pattern to be transferred onto a wafer as a mask pattern has been preceded. The photomask is a blank in which a molybdenum silicon (MoSi) alloy layer as a phase shift layer and a chromium (Cr) layer and a first resist layer as a light shielding layer are laminated on a transparent quartz substrate. It is manufactured using a blank mask.

A resist pattern is formed by an electron beam exposure and development process in which a pattern layout designed by an electron beam exposure process using an electron beam exposure apparatus is transferred to a first resist layer, and a chromium layer and a molybdenum silicon layer are formed. The selective first etching performs a first patterning process. Subsequently, after reapplying the second resist layer, the second exposure and the optional chromium layer pattern of the frame region, which is an edge portion, and the chromium layer pattern of the chip region, which is the middle portion, are removed. The second patterning process of the second etching is performed to form a photomask having a final phase shift mask (PSM) structure. At this time, in the process of applying the second resist layer, the second exposure and the second etching process, a large number of foreign substances are generated on the photomask, which often causes deterioration of the quality of the photomask.

The present invention is to provide a photomask manufacturing method that can suppress the generation of foreign matter.

According to an aspect of the present invention, there is provided a method of forming a phase shift layer, a light shielding layer, and a first resist layer on a substrate including a frame region at an edge portion and a chip region at an inner side thereof; Forming a second resist layer pattern exposing the portion of the first resist layer on the chip region; Transferring a pattern layout designed on the exposed first resist layer portion to form first resist layer patterns; Selectively etching portions of the light blocking layer and the phase shift layer exposed to the second and first resist layer patterns; Sequentially removing the first resist layer pattern portion and the lower light blocking layer portion exposed to the second resist layer pattern; And selectively removing the second resist layer pattern and the lower portion of the first resist layer pattern, wherein the shielding layer portion is shielded in the second resist layer pattern, thereby removing the phase shift layer and the A method of manufacturing a photomask including exposing a layered pattern of a light shielding layer and a pattern of the phase shift layer on the chip region is provided.

According to another aspect of the present invention, there is provided a method of forming a phase shift layer and a light shielding layer on a substrate including a frame region at an edge portion and a chip region at an inner side thereof; Forming different first and second resist layers on the light shielding layer; First exposing and developing the second resist layer to form a second resist layer pattern exposing the portion of the first resist layer on the chip region; Forming a first pattern of the first resist layer by forming a second pattern of the exposed first resist layer and second developing the electron beam, and forming a first pattern of the second resist layer shielded by the second resist layer pattern. step; The light blocking layer and the phase shift layer are selectively etched using the second resist pattern and the first resist layer first pattern as an etching mask to form first light blocking layer patterns and first phase shift layer patterns on the chip region. Forming a light shielding layer second pattern and a phase shifting layer second pattern on the frame region; Selectively removing the first resist layer first pattern to expose the light blocking layer first patterns; Selectively removing the light blocking layer first patterns to expose the phase shift layer first patterns; And selectively removing the second resist layer pattern and the first resist layer first pattern.

The second resist layer may include a resist that is not developed during the first development of the first resist layer, and the first resist layer may include another resist that is not developed during the second development.

The second resist layer may be formed to include a negative resist.

The first resist layer may be formed to include a positive resist exposed to an electron beam.

An embodiment of the present invention can provide a photomask manufacturing method that can suppress the generation of foreign matter.

1 to 10 are views showing a photomask manufacturing method according to an embodiment of the present invention.

Referring to FIG. 1, a phase shift layer 210 and a light shielding layer 230 are formed on a transparent quartz substrate 100. The phase shift layer 210 may include a molybdenum silicon (MoSi) alloy layer, and the light shielding layer 230 may include a chromium (Cr) layer. Different first and second resist layers 310 and 330 are formed on the light blocking layer 230. In this case, the first resist layer 310 may be formed of a first resist exposed to ultraviolet light, and the second resist layer 330 may be formed of a second resist exposed to an electron beam. In addition, the first resist may be formed of a negative resist, and the second resist may be formed of a positive resist for electron beam exposure that reacts with the electron beam. As such, a blank mask in which the phase shift layer 210, the light shielding layer 230, and the double layer resist layers 310 and 330 are sequentially stacked on the quartz substrate 100 is used.

Referring to FIG. 2, a frame region 101 for installing a frame is set at an edge portion of the substrate 100. Inside the frame region 101, a chip region 103 or a mask region in which chip patterns to be transferred onto a wafer is located is set. After introducing a blade or mask 400 exposing the first portion 312 of the second resist layer positioned in the frame region 101, the first portion of the second resist layer exposed to the mask 400. 332 is selectively exposed to the first exposure. The first exposure may be performed by an exposure process using ultraviolet light as an exposure light source. When the second resist layer 330 is composed of a negative resist, the first exposed second resist layer first portion 332 is left in the subsequent first development process, and is shielded by the mask 400 to form the first portion. The second portion 331 of the second resist layer not exposed to the exposure light source remains.

Accordingly, as shown in FIG. 3, a second resist pattern 333 is formed to cover the frame region 101 and to expose the chip region 103. In this case, the lower first resist layer 310 is a resist exposed to the electron beam, and is not exposed by the first exposure, but partially exposed by the second resist pattern 333.

Referring to FIG. 4, an electron beam second exposure process for transferring a pattern layout designed on a portion of the first resist layer 310 exposed by the second resist pattern 333 is performed. A portion of the first resist layer 310 exposed to the second resist pattern 333 is limited to a portion located in the chip region 103. Pattern transfer is selectively performed only on a portion of the first resist layer 310 exposed by the electron beam second exposure process. The first resist layer first portion 311 exposed to the electron beam second exposure is removed in a subsequent second development process, and the first resist layer second portion 312 not exposed to the electron beam second exposure remains. . Accordingly, as shown in FIG. 5, the first resist layer first pattern 313 is formed. In this case, the portion of the first resist layer shielded by the second resist pattern 333 is not exposed to the electron beam second exposure, and thus remains as the first resist layer second pattern 314.

Referring to FIG. 6, a portion of the light shielding layer 230 selectively exposed by the first resist layer first pattern 313 and the second resist layer pattern 333 is selectively etched to selectively shield the light shielding layer pattern 231. 233 and second phase etching of portions of the phase shift layer 210 exposed to the light blocking layer patterns 231 and 233 to form the phase shift layer patterns 211 and 213. In this case, the light blocking layer first pattern 233 and the phase shifting layer first pattern 213 formed by the patterning process including the first and second etchings on the chip region 103 may be substantially formed of the first resist layer. The light shielding layer second pattern 231 and the phase shift layer second pattern 211 selectively patterned by the first pattern 313 and formed by the patterning process on the frame region 101 may include a second resist layer pattern ( 333).

Referring to FIG. 7, portions of the first resist layer first pattern 313 remaining on the chip region 103 are selectively stripped and removed. Accordingly, the light blocking layer first pattern 233 on the chip region 103 is exposed. At this time, the second resist layer pattern 333 formed of a resist different from the first resist layer first pattern 313 is left without being stripped in the first strip process.

Referring to FIG. 8, the exposed light blocking layer first pattern 233 is selectively removed. Accordingly, the upper surface of the phase shift layer first pattern 213 on the chip region 101 is exposed. In this case, in the third etching process of removing the light blocking layer first pattern 233, the light blocking layer second pattern 231 is not exposed and remains blocked by the second resist layer pattern 333. Accordingly, the light blocking layer second pattern 231 remains on the frame region 101 in the frame pattern.

Referring to FIG. 9, a second strip process may be performed to selectively remove the second resist layer pattern 333.

Referring to FIG. 10, a third strip process may be performed to selectively remove the first resist layer second pattern 314 exposed by the removal of the second resist layer pattern 333. Accordingly, the phase shift layer first patterns 213 are disposed on the chip region 103 on the quartz substrate 100, and the phase transition layer second pattern 213 and the light shielding layer second are disposed on the frame region 101. A photomask having a phase shift mask structure in which the pattern 231 is arranged in a frame pattern may be formed.

Exemplary embodiments of the present invention exclude the introduction of a separate resist coating and developing process to selectively remove the light blocking layer first pattern 233 on the chip region 103 after forming the light blocking layer patterns 233 and 231. can do. Accordingly, it is possible to effectively suppress the occurrence of photomask defects due to foreign matter adsorption or residual that may be involved in this process.

1 to 10 are views for explaining a photomask manufacturing method according to an embodiment of the present invention.

Claims (5)

Forming a phase shift layer, a light shielding layer, and a first resist layer on a substrate including a frame region at an edge portion and a chip region therein; Forming a second resist layer pattern exposing the portion of the first resist layer on the chip region; Transferring a pattern layout designed on the exposed first resist layer portion to form first resist layer patterns; Selectively etching portions of the light blocking layer and the phase shift layer exposed to the second and first resist layer patterns; Sequentially removing the first resist layer pattern portion and the lower light blocking layer portion exposed to the second resist layer pattern; And Retaining the shielding layer portion shielded in the second resist layer pattern and selectively removing the second resist layer pattern and the lower portion of the first resist layer pattern, thereby blocking the phase shift layer and the light shielding on the frame region. Exposing a layered pattern of layers and a pattern of the phase shift layer on the chip region. Forming a phase shifting layer and a light shielding layer on a substrate including a frame region at an edge portion and a chip region therein; Forming different first and second resist layers on the light shielding layer; First exposure and first development of the second resist layer to form a second resist layer pattern exposing the first resist layer portion on the chip region; Forming a first pattern of the first resist layer by forming a second pattern of the exposed first resist layer and second developing the electron beam, and forming a first pattern of the second resist layer shielded by the second resist layer pattern. step; The light blocking layer and the phase shift layer are selectively etched using the second resist pattern and the first resist layer first pattern as an etching mask to form first light blocking layer patterns and first phase shift layer patterns on the chip region. Forming a light shielding layer second pattern and a phase shifting layer second pattern on the frame region; Selectively removing the first resist layer first pattern to expose the light blocking layer first patterns; Selectively removing the light blocking layer first patterns to expose the phase shift layer first patterns; And And selectively removing the second resist layer pattern and the first resist layer first pattern. The method of claim 2, And the second resist layer includes a resist that is not developed during the first development of the first resist layer, and the first resist layer includes another resist that is not developed during the second development. The method of claim 2, The second resist layer is a photomask manufacturing method comprising a negative resist (negative) resist. The method of claim 2, The first resist layer is a photomask manufacturing method including a positive (positive) resist is exposed to the electron beam.

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