KR101129022B1 - Method for manufacturing half tone PSM - Google Patents

Abstract

A phase inversion layer and a light shielding layer are formed on a substrate including a chip region and a frame outer region, and relatively large line widths are formed on the first resist patterns and the frame outer region of minute size on the chip region. After forming the second resist pattern, the etching process is performed to form the first light blocking layer pattern and the first phase inversion layer pattern, and the second light blocking layer pattern and the second phase inversion layer pattern. The first and second resist patterns are irradiated with ultraviolet light to shrink the size of the first resist pattern to expose most of the upper surface of the first light blocking layer pattern, and then lift off the exposed first light blocking layer pattern. lift off) to expose the first phase inversion layer pattern. A halftone phase inversion mask (halftone PSM) is manufactured by stripping the second resist pattern remaining during the lift-off to expose the second light blocking layer pattern.

PSM, chrome layer, frame, UV, resist shrink

Description

Halftone phase inversion mask manufacturing method {Method for manufacturing half tone PSM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to lithography technology, and more particularly, to a method for manufacturing a half tone phase shift mask (PSM).

Lithographic processes are being performed to integrate semiconductor devices on wafers. The lithography process involves a photomask fabrication process that designs the layout of the circuit pattern to be formed on the wafer and implements a mask pattern on the transparent quartz substrate that follows the layout of the designed circuit pattern. Is performed. An exposure process using the manufactured photomask is performed to pattern transfer the mask pattern to a photoresist layer on the wafer. When the photomask is manufactured to transfer a pattern having a smaller line width during the exposure process, a phase inversion mask (PSM) structure incorporating a phase inversion region is introduced.

The halftone phase inversion mask (half tone PSM) introduces a halftone phase inversion layer, such as molybdenum silicon nitride (MoSiN), onto a transparent quartz substrate as a mask pattern, and utilizes an optical phase difference between the mask pattern and the quartz substrate during exposure. The finer pattern is transferred onto the wafer. Such halftone PSMs are manufactured through process steps of approximately 40 to 50 steps.

In order to form a halftone PSM, an approximately 6% transmittance MoSiN layer is formed as a phase inversion layer on a transparent quartz substrate, and a chromium (Cr) light shielding layer is formed on the phase inversion layer, and then the first light shielding layer is formed on the first light shielding layer. A process of forming a resist layer is performed. In this case, a first electron beam writing process of performing electron beam exposure of the first resist layer is performed to pattern the phase inversion layer. A first resist pattern transferred with a pattern layout designed by the first electron beam writing and development is formed, and a selective etching process using the first resist pattern as an etching mask is performed to form a light shielding layer pattern and a phase shift layer pattern. Is formed.

However, the PSM is configured to include a chip region, which is an exposure region to be pattern-transferred onto a wafer, and a frame outer region, which is a non-exposed portion surrounding the chip region. In this case, a process of remaining the chromium light shielding layer pattern on the frame outer region and selectively removing the chromium light shielding layer patterns of the main chip region as the exposure region is performed. In order to selectively remove the chromium light shielding layer pattern, it is required to form a second resist pattern covering the non-exposed portion of the frame outer region and opening the chip region. Thus, a resist coating, a second electron beam writing and developing process for exposure are introduced to form the second resist pattern. A process of selectively stripping the exposed chromium light shielding layer patterns using the second resist pattern as an etching mask and stripping the second resist pattern is performed.

As described above, in the process of manufacturing the halftone PSM, a plurality of processes are introduced to selectively remove the chromium light shielding layer patterns formed in the chip region to be pattern-transferd during wafer exposure, thereby forming a binary mask structure. The process is quite complicated. In addition, as such additional processes of second resist coating, electron beam second writing, chromium light shielding layer pattern etching, and second resist strip are introduced, defects accompanying these processes may be caused on the PSM. Can be. In particular, significant defects can be caused in the PSM by the second resist coating and strip.

The present invention is to provide a method of manufacturing a halftone phase shift mask that can reduce the manufacturing process steps to suppress the occurrence of defects.

One aspect of the present invention, forming a phase inversion layer and a light shielding layer on a substrate including a chip region and a frame outer region; Forming first resist patterns of minute size on the light shielding layer portion of the chip region and a second resist pattern having a relatively large line width on the light shielding layer portion on the frame outer region; Selectively etching the light blocking layer and the phase inversion layer using the first and second resist patterns as an etch mask to form a first light blocking layer pattern and a first phase inversion layer pattern having a fine size on the chip region, and the frame outer region Forming a second light blocking layer pattern and a second phase inversion layer pattern having a relatively large line width on the phase; Irradiating ultraviolet light to the first and second resist patterns to shrink the size of the first resist pattern to expose the upper surface of the first light blocking layer pattern; Exposing the first phase inversion layer pattern by lifting off the first light blocking layer pattern exposed by shrinkage of the first resist pattern; And stripping the second resist pattern remaining during the lift-off so that the second light shielding layer pattern is exposed.

When the ultraviolet light is irradiated, the second resist pattern is left to cover the second light blocking layer pattern part due to the difference in size between the first and second resist patterns, and the second light blocking layer is formed by the remaining second resist pattern. The pattern portion may remain during the lift off.

Embodiments of the present invention can reduce the manufacturing process step can propose a halftone phase shift mask manufacturing method that can suppress the occurrence of defects.

An embodiment of the present invention provides a method of manufacturing a halftone phase shift mask that shrinks and etches a resist pattern using ultra violet light and selectively removes the exposed chromium light shield layer pattern by lift off. . Embodiments of the present invention may omit additional processes, such as secondary resist coating, secondary electron beam writing, secondary resist pattern strips, and the like, for remaining the chromium light shielding layer pattern in the frame outer region. have. As such additional additional processes are preferably omitted, it is possible to prevent the occurrence of a defect due to the performance of these additional processes. In addition, it is possible to implement a simplification of the entire mask manufacturing process, thereby increasing the mask manufacturing yield and productivity.

1 to 5 are cross-sectional views provided to explain a method for manufacturing a half tone PSM according to an embodiment of the present invention. FIG. 6 is a measurement photograph provided to explain a resist pattern shrink by ultraviolet irradiation according to an embodiment of the present invention.

Referring to FIG. 1, a phase inversion layer 200 such as a molybdenum silicon nitride layer (MoSiN) having a 6% transmittance is formed on a transparent quartz substrate 100. Thereafter, the chromium (Cr) light shielding layer 300 is formed on the phase inversion layer 200. Thereafter, the resist layer 400 is coated on the light shielding layer 300. The quartz substrate 100 may include a chip region, which is a region to be pattern-transferred onto a wafer by exposure, and an outer region of a frame, on which a pellicle frame is to be installed. The frame outer region may be set to a rectangular border surrounding the chip region.

Referring to FIG. 2, resist patterns 410 and 430 are formed by performing and developing E-beam writing on the resist layer 400. The first resist patterns 410 having a fine size to be pattern-transferred onto the wafer are formed on the chip region, and the second resist pattern 430 having a relatively large line width is formed on the outer region of the frame. A patterning process is performed to selectively etch portions of the light blocking layer 300 and the phase inversion layer 200 exposing the resist patterns 410 and 430 using an etch mask. Accordingly, the first light blocking layer pattern 310 and the first phase inversion layer pattern 210 having fine sizes are formed on the chip region, and the second light blocking layer pattern 330 having a relatively large line width is formed on the outer region of the frame. And a second phase inversion layer pattern 310 is formed.

Referring to FIG. 3, ultraviolet (UV) light is radiated onto the first and second resist patterns 410 and 430 to expose the upper surface of the first light blocking layer pattern 310. Shrink the size. The contracted first resist pattern 411 may remain in a form in which the line width thereof is substantially reduced, and the upper surface of most of the first light blocking layer patterns 310 is formed by the contracted first resist pattern 411. The part is exposed. The shrinkage due to UV irradiation of the first resist pattern 411 may be demonstrated by a scanning electron microscope (SEM) photographic image taken of the PSM image as shown in FIG. 6. As shown in FIG. 6, by the UV irradiation, the resist pattern 641 may be shrink-etched so that the observation resist pattern 641 remains on the observation light shielding layer pattern 630 only at a substantially fine line width. This proves that the resist pattern 641 shrinks greatly by UV irradiation.

Referring back to FIG. 3, UV light is irradiated to induce shrinkage etching of the first resist pattern 411 such that the upper surface portion of the first light blocking layer pattern 310 is mostly exposed. At this time, the second resist pattern 431 may also be shrunk by irradiation of UV, but since the line width of the initial second resist pattern 430 of FIG. 2 is relatively large, it occurs in the first resist pattern 411. When the contracted shrinkage is equally applied, the contracted second resist pattern 431 is still maintained covering most of the second light blocking layer pattern 330.

Referring to FIG. 4, the first light blocking layer pattern 310 exposed by the contraction of the first resist pattern 411 is lifted off to expose the first phase inversion layer pattern 210. By performing wet etching or dry etching on the quartz substrate 100 on which the first resist pattern 411 is contracted by UV irradiation, the first light blocking layer pattern 310 having the uppermost surface exposed is etched away. . In this case, the portion covered by the first resist pattern 411 that is contracted and remains with a fine line width may have a relatively small area so that the lower portion of the first light blocking layer pattern 310 may be etched away by the etching environment. . Therefore, the remaining first resist pattern 411 is also removed during lift off.

Since the second light blocking layer pattern 330 is covered and protected by the second resist pattern 431 in which most of the upper surfaces remain, the second light blocking layer pattern 330 remains without being lifted off by such wet etching or dry etching. At this time, a part of the exposed second light blocking layer pattern 330 may be lost, but most of the second light blocking layer pattern 330 remains on the frame outer region without being affected by the lift-off.

Referring to FIG. 5, the remaining second resist pattern 431 is removed by a strip process. This stripping process may be performed including ashing and sulfuric acid stripping processes.

In this embodiment of the present invention, in order to leave the chromium light shielding layer portion in the outer region of the frame, the introduction of additional process steps such as additional secondary resist coating, secondary electron beam writing and development may be omitted. Therefore, the manufacturing process of the halftone phase inversion mask can be simplified more. By simplifying such a manufacturing process, the defect generation on a phase inversion mask can be suppressed more effectively, and also the productivity of a mask manufacturing process can be increased.

1 to 5 are cross-sectional views provided to explain a method for manufacturing a half tone PSM according to an embodiment of the present invention.

FIG. 6 is a measurement photograph provided to explain a resist pattern shrink by ultraviolet irradiation according to an embodiment of the present invention.

Claims (3)

Forming a phase shifting layer and a light shielding layer on a substrate including a chip region and a frame outer region; Forming first resist patterns of minute size on the light shielding layer portion of the chip region and a second resist pattern having a relatively large line width on the light shielding layer portion on the frame outer region; Selectively etching the light blocking layer and the phase inversion layer using the first and second resist patterns as an etch mask to form a first light blocking layer pattern and a first phase inversion layer pattern having a fine size on the chip region, and the frame outer region Forming a second light blocking layer pattern and a second phase inversion layer pattern having a relatively large line width on the phase; Irradiating ultraviolet light to the first and second resist patterns to shrink the size of the first resist pattern to expose the upper surface of the first light blocking layer pattern; Exposing the first phase inversion layer pattern by lifting off the first light blocking layer pattern exposed by shrinkage of the first resist pattern; And Stripping the second resist pattern remaining during the lift-off so that the second light blocking layer pattern is exposed; When the ultraviolet light is irradiated, the second resist pattern may remain to cover the second light blocking layer pattern part due to the difference in size between the first and second resist patterns. The second light blocking layer pattern portion is left during the lift-off due to the remaining second resist pattern. delete Claim 3 was abandoned when the setup registration fee was paid. The method of claim 1, The lift-off method is a halftone phase shift mask manufacturing method performed by wet etching or dry etching the exposed first light-shielding layer pattern.

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