KR20100131180A - Semicondoctor package, semiconductor module and method for fabricationg the semiconductor package - Google Patents

Semicondoctor package, semiconductor module and method for fabricationg the semiconductor package Download PDF

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Publication number
KR20100131180A
KR20100131180A KR1020090049948A KR20090049948A KR20100131180A KR 20100131180 A KR20100131180 A KR 20100131180A KR 1020090049948 A KR1020090049948 A KR 1020090049948A KR 20090049948 A KR20090049948 A KR 20090049948A KR 20100131180 A KR20100131180 A KR 20100131180A
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KR
South Korea
Prior art keywords
semiconductor package
substrate
melt
redistribution
melting point
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Application number
KR1020090049948A
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Korean (ko)
Inventor
강선원
백승덕
이종기
Original Assignee
삼성전자주식회사
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Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020090049948A priority Critical patent/KR20100131180A/en
Priority claimed from US12/588,477 external-priority patent/US20100096754A1/en
Publication of KR20100131180A publication Critical patent/KR20100131180A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Abstract

PURPOSE: A semiconductor package, a semiconductor module, and a method for manufacturing the semiconductor package are provided to reduce the number of processes for manufacturing the semiconductor package by omitting the forming process of a solder mask. CONSTITUTION: A substrate(300) including a bonding pad(302) is prepared. An insulating layer(306) is formed to expose the bonding pad through the substrate. A rerouting line(310) which is in electric connection with the bonding pad is formed on the insulating layer. A melt with a first melting point and a solder ball with a second melting point are formed on the rerouting line. The melt is selectively melted to form an external terminal(320).

Description

Semiconductor package, semiconductor module and manufacturing method of semiconductor package {SEMICONDOCTOR PACKAGE, SEMICONDUCTOR MODULE AND METHOD FOR FABRICATIONG THE SEMICONDUCTOR PACKAGE}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor package, a semiconductor module including such a semiconductor package, and a method for manufacturing a semiconductor package.

One of the major trends in technology development in the semiconductor industry is miniaturization and light weight. Accordingly, a package technology called a chip scale package (CSP) or chip size package has been developed in which the size of a semiconductor package is reduced to that of a semiconductor chip. In addition, a wafer level package or wafer level chip scale package manufacturing technology for simultaneously manufacturing a plurality of semiconductor packages at the wafer level has been developed. However, the process of forming the semiconductor chip and the external terminal in the manufacturing step of the chip scale package or wafer level package is complicated.

One technical problem to be solved by the present invention is to provide a semiconductor package and a method of manufacturing the same, which simplifies the manufacturing process and has reliability.

Another technical problem to be solved by the present invention is to provide a semiconductor module, a memory card and an information processing system using a semiconductor package.

The present invention for achieving the above object is characterized in that the process is simplified by not forming a solder mask defining the ball land, and the structure of the semiconductor package is simplified.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor package, the method including: providing a substrate including at least one bonding pad; Forming an insulating layer exposing the bonding pad on the substrate; Forming redistribution electrically connected to the bonding pads on the insulating layer; Providing a solder ball on the redistribution having a melt of a first melting point and a melt of a second melting point that is smaller than the first melting point; And selectively melting the melt to form external terminals.

In the method of the present embodiment, forming the external terminal may include not forming a second insulating layer exposing a part of the redistribution on the insulating layer.

In the method of the present embodiment, forming the external terminal may include selectively melting the melt to wet the redistribution without melting the non-melt.

In the method of this embodiment, the limited wetting of the melt is such that the non-melt is not melted so that the selectively melted melt is not infinitely wetted to the redistribution by the contact force with the non-melt. It may include.

In the method of the present embodiment, forming the external terminal may include heating the solder ball to an intermediate temperature between the first and second melting points.

In the method of the present embodiment, forming the external terminal comprises a convection reflow process of selectively melting the shell by heating the solder ball to a temperature between the first and second melting points, and induction heater of the substrate. It may be adopted to any one of the Joule heating process to provide to selectively melt the shell.

In the method of the present embodiment, providing the solder ball may include attaching a solder ball on the redistribution having a structure in which the melt surrounds the non-melt.

In the method of the present embodiment, the method may further include forming a molding layer partially exposing the external terminal.

In accordance with another aspect of the present invention, a semiconductor package may include: a substrate having a bonding pad; An insulating layer disposed on the substrate and exposing a portion of the bonding pad; A redistribution disposed on the insulating layer and electrically connected to the bonding pads; And an external terminal disposed on the redistribution line and having an outer shell having a low melting point surrounding the inner core of the high melting point.

In the semiconductor package of the present embodiment, the inner core includes a first metal, a heat resistant resin, or a combination thereof; The envelope may include a second metal having a lower melting point than the first metal.

In the semiconductor package of the present embodiment, the inner core is copper (Cu), nickel (Ni), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), polyimide, polyamideimide (Polyamideimide), Polyetherimide, Polyethersulfone, Polyarylate, Polyphenylenesulfide, Polyetheretherketone, Polysulfone or a combination thereof It may include.

In the semiconductor package of the present embodiment, the shell includes lead (Pb), lead (Pb) / tin (Sn), tin (Sn) / zinc (Zn), tin (Sn) / bismuth (Bi), tin (Sn). / Silver (Ag), Tin (Sn) / Zinc (Zn) / Bismuth (Bi), Tin (Sn) / Silver (Ag) / Copper (Cu), Tin (Sn) / Bismuth (Bi) / Silver (Ag) / Indium (In), or a combination thereof.

A semiconductor module according to an embodiment of the present invention capable of implementing the above features includes a module substrate; And at least one semiconductor package mounted on the module substrate; The at least one semiconductor package includes a substrate having at least one bonding pad; An insulating layer disposed on the substrate and exposing a portion of the at least one bonding pad; At least one redistribution disposed on the insulating layer and electrically connected to the at least one bonding pad; And at least one external terminal disposed on the at least one redistribution line and having a low melting envelope covering the inner core of a high melting point; And a molding layer disposed on the insulating layer to cover the redistribution and partially exposing the external terminal; The at least one semiconductor package may be electrically connected to the module substrate through the at least one external terminal.

According to the present invention, it is possible to secure the reliability of the semiconductor package while omitting the process of forming the solder mask for forming the shape of the external terminals on the redistribution. Accordingly, it is possible to reduce the consumption of the insulator and to shorten the process time. Also, the patterning step of the solder mask can be omitted, so that the photolithography step can be reduced. Therefore, the semiconductor package forming step can be simplified to reduce the manufacturing cost.

Hereinafter, a method of manufacturing a semiconductor package, a semiconductor module, and a semiconductor package according to the present invention will be described in detail with reference to the accompanying drawings.

Advantages over the present invention and prior art will become apparent through the description and claims with reference to the accompanying drawings. In particular, the present invention is well pointed out and claimed in the claims. However, the present invention may be best understood by reference to the following detailed description in conjunction with the accompanying drawings. Like reference numerals in the drawings denote like elements throughout the various drawings.

In embodiments of the present invention, terms such as first and second may be used to describe various components, but the components should not be limited by these terms. These terms are only used to distinguish one component from another.

The terms used in the embodiments of the present invention are merely used to describe the embodiments, and are not intended to limit the present invention. In embodiments of the invention, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, one or It is to be understood that no other features or numbers, steps, actions, components, parts, or combinations thereof are excluded in advance.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are ideally or excessively formal, unless explicitly defined in the embodiments of the present invention. It is not interpreted in the sense.

(Example of Semiconductor Package)

1A is a cross-sectional view illustrating a semiconductor package in accordance with an embodiment of the present invention.

Referring to FIG. 1A, a semiconductor package 350 according to an embodiment of the present invention may include a passivation layer sequentially stacked on a substrate 300 having at least one bonding pad 302 and an upper surface 301 of the substrate 300. 304, an interlayer insulating layer 306, and a redistribution 310 may be included. The semiconductor package 350 may further include a molding layer 340. At least one external terminal 320 may be disposed on the redistribution 310. A plurality of redistribution 310 may be provided according to the design.

The substrate 300 may be a wafer unit, and the semiconductor package 350 may be a wafer unit package (WFP). However, the exemplary embodiment is not limited thereto. For example, the substrate 300 may be a chip (die) unit board and the semiconductor package 350 may be a chip unit package (CSP). An integrated circuit 303 electrically connected to the bonding pad 302 may be formed on the substrate 300.

The number of bonding pads 302 may be appropriately selected depending on the type and capacity of the integrated circuit 303. For example, the plurality of bonding pads 302 may be irregularly arranged on the upper surface 301 of the substrate 300 according to the design, or alternatively, locally or entirely regularly arranged. For example, when the substrate 300 is a chip unit substrate, the bonding pads 302 may form a so-called center pad structure in which one or more rows are arranged in the center of the substrate 300. As another example, the bonding pads 302 may form a so-called edge pad structure in which one or more rows are arranged at the edge of the substrate 300. As another example, the bonding pads 302 may be arranged in a matrix form irregularly or regularly distributed over the entire area of the substrate 300.

The passivation layer 304 may have a first opening 322 exposing the bonding pads 302. The interlayer insulating layer 306 may have a second opening 332 exposing the first opening 322. In the present exemplary embodiment, the passivation layer 304 and the interlayer insulating layer 306 are separated from each other, but are not distinguished from each other and may be referred to as a name (for example, an insulating layer) or may be omitted.

The redistribution 310 may be disposed on the interlayer insulating layer 306 and may be electrically connected to the bonding pad 302 through the first and second openings 322 and 332. Accordingly, the redistribution 310 may electrically connect the bonding pad 302 and the external terminal 320. The external terminal 320 may be directly attached on the redistribution 310 without the help of a so-called solder mask. The redistribution 310 may serve to rearrange the bonding pads 302.

1B is a cross-sectional view illustrating a semiconductor package in accordance with an embodiment of the present invention. In FIG. 1B, the substrate 300 is generally illustrated as a substrate having a rectangular chip unit, and the passivation layer 304, the interlayer insulating layer 306, and the molding layer 340 are omitted.

Referring to FIG. 1B, as an example, the redistribution 310 may reposition the bonding pads 302 having the center pad structure to the edge of the substrate 300 (I). In this case, the external terminals 320 may be arranged at the edge of the substrate 300. The bonding pads 302 may be arranged in one or more rows in the center of the substrate 300. The external terminals 320 may be arranged in one or more rows at left, right, top, bottom, left and right edges of the substrate 300. As another example, the redistribution 310 may rearrange the bonding pads 302 of the edge pad structure to the center of the substrate 300 (II). The external terminals 320 may be arranged in one or more rows at left, right, top, bottom, left and right edges of the substrate 300. As another example, the redistribution 310 may rearrange the bonding pads 302 of the edge pad structure in a matrix form over the entire area of the substrate 300 (III). That is, the external terminals 320 may be arranged in a matrix form over the entire area of the substrate 300. In (III) of FIG. 1B, the bonding pads 302 may have a center pad structure or may be arranged in a matrix form over the entire area of the substrate 300. As another example, the redistributions 310 may be used to adjust the spacing of the bonding pads 302 or to adjust the spacing and position. This embodiment is not limited to the arrangement of the bonding pads 302 and the external terminals 320 described above with reference to FIG. 1B.

Referring back to FIG. 1A, the external terminal 320 may be entirely made of the same material, or may include an inside and an outside made of different materials. According to the present embodiment, the external terminal 320 may be the latter. For example, the external terminal 320 may be a solder ball having a dual structure including an inner core 322 and an outer shell 324 surrounding the inner core 322. According to the present embodiment, the inner core 322 may be made of a material that does not melt even when the outer shell 324 is melted during the reflow process. For example, the outer shell 324 may be made of a low melting point material, and the inner core 322 may be made of a high melting point material.

In this specification, the high melting point and the low melting point mean a relative height between the melting points of the inner core 322 and the outer shell 324. For example, "inner core 322 is composed of a high melting point material" means that the inner core 322 is composed of a material having a higher melting point than the outer shell 324. Likewise, "shell 324 is composed of low melting point material" means that shell 324 is comprised of a material having a lower melting point than inner core 322.

Since the outer terminal 320 is an electrical connection medium, at least the outer shell 324 is preferably made of a conductive material. The inner core 322 may be made of a conductive material such as a metal or a non-conductive material such as a heat resistant resin. When the inner core 322 is made of a conductive material such as metal, it is possible to implement the external terminal 322 having excellent electrical conductivity. In contrast, when the inner core 322 is formed of a heat resistant resin such as polyimide, the semiconductor package 350 may be reduced in weight. The external terminal 320 may include a solder ball having a plurality of structures including at least one conductive or nonconductive film surrounding the inner core 322 between the inner core 322 and the outer shell 324.

The molding layer 340 may cover the insulating layer 306 but partially expose the external terminal 320. As another example, the molding layer 340 may be provided to expose a portion of the external terminal 320 but to mold the semiconductor package 350.

(Example of Manufacturing Method of Semiconductor Package)

2 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention, and FIGS. 3A to 3F are cross-sectional views illustrating an example of the method of FIG. 2. Reference numerals S310-S380 indicating the process steps of FIG. 2 are written together in corresponding portions when describing FIGS. 3A to 3F.

Referring to FIG. 3A, a method of manufacturing a semiconductor package according to an embodiment of the present invention may provide a substrate 300 (S310). The substrate 300 may be a silicon (Si), silicon-germanium (SiGe), or silicon on insulator substrate on a wafer basis. As another example, the substrate 300 may be a substrate in a chip (die) unit in which a wafer unit substrate is sawed and individually separated. According to the present exemplary embodiment, the substrate 300 may be a silicon substrate in a wafer unit, and the present exemplary embodiment is not limited thereto. The integrated circuit 303 may be formed on the substrate 300. The integrated circuit 303 may be memory, logic, or a combination of these.

At least one bonding pad 302 electrically connected to the integrated circuit 303 may be formed on the upper surface 301 of the substrate 300. The bonding pads 302 may be formed in a center pad, an edge pad, or a matrix structure, as described above with reference to FIG. 1B. The bonding pad 302 may be made of a conductive material including a metal such as aluminum (Al), copper (Cu), or an alloy thereof. The bonding pads 302 may be formed by deposition and patterning of a conductive material or plating.

A passivation layer 304 may be formed on the top surface 301 of the substrate 300 having a first opening 322 that partially exposes the bonding pads 302 (S320). The passivation layer 304 may be formed by deposition and patterning of an insulating material. Subsequently, an interlayer insulating layer 306 may be formed to cover the passivation layer 304 and have a second opening 332 exposing the first opening 322 (S330). The bonding pads 302 may be exposed through the first and second openings 322 and 332. As another example, the deposition and patterning of the insulating material may form the passivation layer 304 and the interlayer insulating layer 306 successively, and form the first and second openings 322 and 332 exposing the bonding pad 302. have. Forming the first and second openings 222 and 232 may include patterning the interlayer insulating layer 306 and the passivation layer 304 in order to form a trench that exposes the bonding pad 302.

Optionally, one of the passivation layer 304 and the interlayer insulating layer 306 may be omitted. In the present embodiment, it will be described that the passivation layer 304 and the interlayer insulating layer 306 are formed separately from each other, and the present embodiment is not limited thereto. The passivation layer 304 and the interlayer insulating layer 306 may be formed of the same or similar materials, or may be formed of different materials. For example, the passivation layer 304 may be formed by depositing an oxide or nitride, and the interlayer insulating layer 306 may be formed by depositing or spin coating a resin such as polyimide, and vice versa.

Referring to FIG. 3B, at least one redistribution 310 may be formed on the interlayer insulating layer 306 (S340). The redistribution 310 may be formed by deposition and patterning of a conductor, or electrolytic or electroless plating. The redistribution 310 may be formed of a metal such as gold (Au), silver (Ag), platinum (Pt), copper (Cu), aluminum (Al), tungsten (W), or an alloy thereof. For example, the redistribution 310 may be formed by plating copper (Cu), and may be thinly coated with nickel (Ni) to prevent oxidation of the copper surface. The redistribution 310 may be electrically connected to the bonding pads 302 through the first and second openings 322 and 332. The redistribution 310 may be formed in a straight line form, but may be formed in a curved form or in a separate form.

Referring to FIG. 3C, at least one solder ball 320a may be provided and attached to the redistribution 310 (S350). Optionally, prior to attaching the solder balls 320a, the method may further include applying flux on the redistribution 310. The flux may include at least one of a resin, thinner, and an activator.

The solder ball 320a may have a structure in which the non-fusion melt 322a and the melt 324a are combined. For example, the non-fusion 322a may have a generally solid sphere shape (hereinafter inner core), and the melt 324a may have a shape of a hollow sphere (hereinafter, referred to as a hollow sphere). Sheath). As another example, the melt 324a may not be spherical. According to the present embodiment, the solder ball 320a may have a double structure in which the outer shell 324a surrounds the inner core 322a. The melting point TM1 of the inner core 322a may be made of a material higher than the melting point TM2 of the outer shell 324a. As another example, the solder ball 320a may have a multiple structure including at least one intermediate film surrounding the inner core 322a between the inner core 322a and the outer shell 324a. The melting point of this interlayer may be equal to or greater than the melting point TM2 of the shell 324a. Alternatively, the melting point of the interlayer may be equal to or larger than the melting point TM1 of the inner core 322a. Alternatively, the melting point of the interlayer may be a value between the melting point TM2 of the outer shell 324a and the melting point TM1 of the inner core 322a.

The outer shell 324a is, for example, lead (Pb), lead (Pb) / tin (Sn), tin (Sn) / zinc (Zn), tin (Sn) / bismuth (Bi), tin (Sn) / silver (Ag) , Tin (Sn) / zinc (Zn) / bismuth (Bi), tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / bismuth (Bi) / silver (Ag) / indium (In) , Or a combination thereof.

The inner core 322a may be formed of a heat resistant metal, copper (Cu), nickel (Ni), or an alloy thereof. The heat resistant metal may include, for example, molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), or a combination thereof. When the inner core 322a is made of a conductive material, electrical conductivity of the external terminal 320 of FIG. 3D may be improved. As another example, the inner core 322a may be formed of a heat resistant resin. Heat-resistant resins are, for example, polyimide, polyamideimide, polyetherimide, polyethersulfone, polyarylate, polyphenylenesulfide, polyetheretherketone (Polyetheretherketone), polysulfone (Polysulfone), or a combination thereof. When the inner core 322a is formed of a heat resistant resin, the external terminal 320 of FIG. 3D may be reduced in weight, and thus the weight of the semiconductor package 350 of FIG. 3D may be reduced.

The reflow process may be performed while the solder balls 320a are attached to the redistribution 310. The reflow temperature TR may be a value between the melting point TM1 of the inner core 322a and the melting point TM2 of the outer shell 324a. As an example, it is assumed that the outer shell 324a is made of lead (Pb) / tin (Sn) or tin (Sn) / zinc (Zn), and the inner core 322a is made of nickel (Ni). In this case, the reflow temperature TR is the melting point (TM2: approximately 183 ° C) of lead (Pb) / tin (Sn) constituting the outer shell 324a, and the melting point (TM1) of nickel (Ni) constituting the inner core 322a. : Approximately 1452 ° C.), and may range from approximately 200 to 250 ° C. In the case where the solder balls 320a have multiple structures, the interlayer film between the inner core 322a and the outer shell 324a is not melted together with the outer shell 324a or melted together with the inner core 324a during the reflow process. Can be set.

According to the reflow process, the outer shell 324a is selectively melted, but the inner core 322a is not melted and may remain in an initial form, such as a spherical shape. The outer shell 324a is selectively melted and wetted in the redistribution 310, but may not be wetted indefinitely along the redistribution 310 by the connection force with the inner core 322a. Even if the initial shape of the shell 324a is not spherical, it may be melted by the reflow process and deformed into a sphere due to the surface tension. Accordingly, the molten solder ball 320a may remain substantially spherical in the attached position.

Referring to FIG. 7, the solder ball 320a may be heated by Joule heating using an induction heater 500 instead of the above-described convection reflow process. The time for the induction heater 500 to heat the solder ball 320a may be shortened compared to the general reflow time. For example, if the convection reflow time is in the range of about a few minutes (eg, 8 minutes), the Joule heating time may be in the range of a few seconds (eg, within 5 seconds). The latter Joule heating process may not be subject to heating temperature limitations in the former convective reflow process. According to this, the inner core 322a is not melted without limiting the heating temperature, but the outer shell 324a may be selectively melted quickly.

The induction heater 500 may include a generally disk-shaped first heater 510 disposed above the substrate 300 and a second heater 520 disposed below the substrate 300. At least one of the first and second heaters 510 and 520 may include a coil that generates heat by a high frequency or low frequency induction current. The coil may have a size equal to or greater than the aperture of the substrate 300. The number of turns of the coil may be one or more. Induction heater 500 may be adjusted to a frequency of 10MHz or more and power of 2000Watt or more.

Referring to FIG. 3D, at least one external terminal 320 may be formed on the redistribution 310 (S360). The external terminal 320 may be formed by reflowing or Joule heating the solder ball 320a having the dual structure described above with reference to FIG. 3C.

In general, in the reflow process, the molten solder ball 320a is formed on the interlayer insulating layer 306 to form an external terminal 320 having a desired shape at a desired position by defining a region to be wetted on the redistribution 310. It is conventional to form a so-called solder mask by performing a patterning process in which a second interlayer insulating layer is deposited on and a ball land is opened. The solder mask serves as a guide to allow solder balls to settle on the ball lands and prevents indefinite wetting of the solder balls to short-circuit between external terminals, and mainly to protect the rewiring. On the other hand, the solder mask is unnecessary because the molding process is subsequently performed, but it is common to form a solder mask in order to define a ball land and prevent indefinite wetting of the solder ball. However, according to the present exemplary embodiment, the external terminal 320 may be formed by local melting of the solder balls 320a without forming a solder mask. According to the above series of processes, the semiconductor package 350 in a wafer unit may be implemented.

Referring to FIG. 3E, the molding layer 340 may be selectively formed at the wafer level step (S370). The molding layer 340 may be formed to mold the top surface 301 of the substrate 300. Alternatively, the molding layer 340 may be formed to mold the entire semiconductor package 350. The external terminal 320 may be partially exposed from the surface of the molding layer 340. The molding layer 340 may be formed of an insulating resin, for example, an epoxy molding compound (EMC). The molding layer 340 may be cured by heat treatment. The molding layer 340 may serve to protect the redistribution 310, and may further protect the semiconductor package 350 from an external environment. In addition, according to the wafer level molding process, it is possible to implement a robust semiconductor package 350.

Referring to FIG. 3F, a sawing process of selectively separating a semiconductor package 350 (WPF) in a wafer unit into a semiconductor package CSP in a chip unit may be further performed (S380). For example, the sawing process may include separating the wafer 300 on the scribe lane 410 with the cutting wheel 400. As another example, the sawing process may employ a laser instead of the cutting wheel 400. In the semiconductor package in a chip unit, the external terminals 320 are arranged at the edge of the substrate 300 as shown in (I) of FIG. 1B or at the center of the substrate 300 as shown in (II) of FIG. 1B. It may be arranged or in the form of a matrix as in (III) of FIG.

4 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention. The manufacturing method of this embodiment may refer to the manufacturing method described above with reference to FIGS. 3A to 3F and FIG. 7, and redundant descriptions thereof will be omitted below.

Referring to FIG. 4, the process from the substrate providing step S310 to the external terminal forming step S360 may be similar to that described above with reference to FIGS. 3A to 3D. Accordingly, as shown in FIG. 3D, a semiconductor package 350 in a wafer unit may be implemented. Subsequently, as illustrated in FIG. 3F, a sawing process may be performed (S380). Accordingly, the semiconductor package 350 in a wafer unit may be separated into a semiconductor package in a plurality of chip units. Thereafter, the molding layer 340 may be formed in the semiconductor package in a chip unit, unlike the wafer level molding process illustrated in FIG. 3E.

(Example of Semiconductor Module)

5 is a plan view illustrating a semiconductor module according to an embodiment of the present invention.

Referring to FIG. 5, in the semiconductor module 1000 of the present embodiment, a plurality of semiconductor packages 1004 may be mounted on a module substrate 1002. Any edge of the module substrate 1002 may include a terminal 1006 for electrical connection with an external device. For example, the module substrate 1002 may include a printed circuit board (PCB), and the terminal 1006 may include a plurality of connecting pins.

The semiconductor package 1004 may include, for example, a semiconductor package in a chip unit separated from the semiconductor package 350 in a wafer unit implemented by the manufacturing method described above with reference to FIGS. 3A through 3F. The semiconductor package 1004 may be electrically connected to the module substrate 1002 through an external terminal 320 of FIG. 3D. When the semiconductor package 1004 is a memory chip, the semiconductor module 1000 may be adopted as a memory module. The memory chip may include various memories such as DRAM, SRAM, FLASH, PRAM, RRAM, MRAM, FRAM, or a combination thereof. Can be.

(Application example)

6A is a block diagram illustrating a memory card including a semiconductor package and / or a semiconductor module according to an exemplary embodiment of the present invention.

Referring to FIG. 6A, a semiconductor memory 1210 including a semiconductor package (350 of FIG. 1A) and / or a semiconductor module (1000 of FIG. 5) according to various embodiments of the present disclosure described above may include a memory card 1200. It can be applied to. For example, the memory card 1200 may include a memory controller 1220 that controls overall data exchange between the host and the memory 1210. The SRAM 1221 may be used as an operating memory of the CPU 1222. The host interface 1223 may include a data exchange protocol of a host connected to the memory card 1200. The error correction code 1224 may detect and correct an error included in data read from the memory 1210. The memory interface 1225 interfaces with the memory 1210. The CPU 1222 performs various control operations for exchanging data of the memory controller 1220.

6B is a block diagram illustrating an information processing system using a semiconductor package and / or a semiconductor module according to various embodiments of the present disclosure.

Referring to FIG. 6B, the information processing system 1300 may include a memory system 1310 having a semiconductor package and / or a semiconductor module according to an embodiment of the present disclosure. The information processing system 1300 may include a mobile device or a computer. In one example, the information processing system 1300 includes a memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to the system bus 1360, respectively. can do. The memory system 1310 includes a memory 1311 and a memory controller 1312 and may be configured substantially the same as the memory card 1200 of FIG. 6A. The memory system 1310 may store data processed by the CPU 1330 or data input externally. The information processing system 1300 may be provided as a memory card, a solid state disk, a camera image sensor, and other application chipsets. For example, the memory system 1310 may include a semiconductor disk device (SSD), in which case the information processing system 1300 may stably and reliably store a large amount of data in the memory system 1310.

The semiconductor package according to the embodiment of the present invention may be packaged in various forms. For example, a semiconductor package according to an embodiment of the present invention may include a package on package, a ball grid array, a chip scale package, and a plastic leaded chip carrier. ), Plastic Dual In-Line Package, Multi Chip Package, Wafer Level Package, Wafer Level Fabricated Package, Wafer Level Stack Package Level Stack Package, Die On Waffle Package, Die in Wafer Form, Chip On Board, Ceramic Dual In-Line Package, Plastic Kick Metric Quad Flat Pack, Thin Quad Flat Pack, Small Outline Package, Small Small Outline Package The package may be packaged in a manner such as a package, a thin small outline package, a thin quad flat package, a system in package, or the like.

The foregoing detailed description is not intended to limit the invention to the disclosed embodiments, and may be used in various other combinations, modifications, and environments without departing from the spirit of the invention. The appended claims should be construed to include other embodiments.

1A is a cross-sectional view illustrating a semiconductor package in accordance with an embodiment of the present invention.

1B is a cross-sectional view illustrating a semiconductor package in accordance with an embodiment of the present invention.

2 is a flowchart illustrating a method of manufacturing a semiconductor package according to an embodiment of the present invention.

3A to 3F are cross-sectional views showing one example of a method of manufacturing a semiconductor package according to the embodiment of the present invention.

4 is a flowchart illustrating a method of manufacturing a semiconductor package according to another embodiment of the present invention.

5 is a plan view showing a semiconductor module according to an embodiment of the present invention.

6A is a block diagram illustrating a memory card having a semiconductor package and / or a semiconductor module according to an embodiment of the present invention.

6B is a block diagram illustrating an information processing system employing a semiconductor package and / or a semiconductor module according to various embodiments of the present disclosure.

7 is a perspective view showing an induction heater in the method of manufacturing a semiconductor package according to an embodiment of the present invention.

Claims (10)

  1. Providing a substrate comprising at least one bonding pad;
    Forming an insulating layer exposing the bonding pad on the substrate;
    Forming redistribution electrically connected to the bonding pads on the insulating layer;
    Providing a solder ball on the redistribution having a melt of a first melting point and a melt of a second melting point that is smaller than the first melting point; And
    Selectively melting the melt to form external terminals;
    Method for manufacturing a semiconductor package comprising.
  2. The method of claim 1,
    Forming the external terminal is:
    A method of manufacturing a semiconductor package in which the molten melt is selectively melted without limited melting of the non-melt melt and limited to the rewiring.
  3. The method of claim 2,
    Limited wetting of the melt is:
    And wherein said non-fusion melt is not melted and said selectively melted melt is not infinitely wetted to said rewiring by connection force with said non-fusion melt.
  4. The method of claim 1,
    Forming the external terminal is:
    And heating the solder ball at an intermediate temperature between the first and second melting points.
  5. The method of claim 1,
    Providing the solder ball is:
    And attaching a solder ball having a structure in which the molten body surrounds the non-fusion body on the redistribution line.
  6. The method of claim 1,
    And forming a molding layer partially exposing the external terminals.
  7. A substrate having a bonding pad;
    An insulating layer disposed on the substrate and exposing a portion of the bonding pad;
    A redistribution disposed on the insulating layer and electrically connected to the bonding pads; And
    An outer terminal disposed on the redistribution line and having an outer shell having a low melting point surrounding the inner core of a high melting point;
    Semiconductor package containing.
  8. The method of claim 7, wherein
    The inner core comprises a first metal, a heat resistant resin, or a combination thereof;
    The envelope includes a second metal having a lower melting point than the first metal.
  9. The method of claim 7, wherein
    The inner core is copper (Cu), nickel (Ni), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), polyimide, polyamideimide, polyetherimide ( Polyetherimide, polyethersulfone, polyarylate, polyphenylenesulfide, polyetheretherketone, polysulfone, and combinations thereof;
    The sheath is lead (Pb), lead (Pb) / tin (Sn), tin (Sn) / zinc (Zn), tin (Sn) / bismuth (Bi), tin (Sn) / silver (Ag), tin ( Sn) / zinc (Zn) / bismuth (Bi), tin (Sn) / silver (Ag) / copper (Cu), tin (Sn) / bismuth (Bi) / silver (Ag) / indium (In), and these A semiconductor package comprising any one of the combinations.
  10. A module substrate; And
    At least one semiconductor package mounted on the module substrate;
    The at least one semiconductor package is:
    A substrate having at least one bonding pad;
    An insulating layer disposed on the substrate and exposing a portion of the at least one bonding pad;
    At least one redistribution disposed on the insulating layer and electrically connected to the at least one bonding pad;
    At least one outer terminal disposed on the at least one redistribution line and having a low melting envelope covering the inner core of a high melting point; And
    A molding layer disposed on the insulating layer to cover the redistribution and partially exposing the external terminal;
    And the at least one semiconductor package is electrically connected to the module substrate through the at least one external terminal.
KR1020090049948A 2009-06-05 2009-06-05 Semicondoctor package, semiconductor module and method for fabricationg the semiconductor package KR20100131180A (en)

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US12/588,477 US20100096754A1 (en) 2008-10-17 2009-10-16 Semiconductor package, semiconductor module, and method for fabricating the semiconductor package

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US8987058B2 (en) 2013-03-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for wafer separation
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9240387B2 (en) 2011-10-12 2016-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level chip scale package with re-workable underfill
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
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US9240387B2 (en) 2011-10-12 2016-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level chip scale package with re-workable underfill
US9287143B2 (en) 2012-01-12 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus for package reinforcement using molding underfill
US9607921B2 (en) 2012-01-12 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package interconnect structure
US9368398B2 (en) 2012-01-12 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9768136B2 (en) 2012-01-12 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US9082776B2 (en) 2012-08-24 2015-07-14 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having protective layer with curved surface and method of manufacturing same
US9698028B2 (en) 2012-08-24 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US9263839B2 (en) 2012-12-28 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
US10062659B2 (en) 2012-12-28 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved fine pitch joint
KR101476531B1 (en) * 2012-12-28 2014-12-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 System and Method for an Improved Fine Pitch Joint
US9525054B2 (en) 2013-01-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
US9899493B2 (en) 2013-01-04 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. High electron mobility transistor and method of forming the same
US10015888B2 (en) 2013-02-15 2018-07-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect joint protective layer apparatus and method
US9935070B2 (en) 2013-03-11 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9257333B2 (en) 2013-03-11 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9589862B2 (en) 2013-03-11 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US10262964B2 (en) 2013-03-11 2019-04-16 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures and methods of forming same
US9673160B2 (en) 2013-03-12 2017-06-06 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US9401308B2 (en) 2013-03-12 2016-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging devices, methods of manufacture thereof, and packaging methods
US8987058B2 (en) 2013-03-12 2015-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for wafer separation
US9437564B2 (en) 2013-07-09 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of fabricating same
US10014267B2 (en) 2015-06-12 2018-07-03 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof

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