KR20100130801A - Spacer patterning technology using positive-negative photoresist - Google Patents

Spacer patterning technology using positive-negative photoresist Download PDF

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Publication number
KR20100130801A
KR20100130801A KR1020090049503A KR20090049503A KR20100130801A KR 20100130801 A KR20100130801 A KR 20100130801A KR 1020090049503 A KR1020090049503 A KR 1020090049503A KR 20090049503 A KR20090049503 A KR 20090049503A KR 20100130801 A KR20100130801 A KR 20100130801A
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KR
South Korea
Prior art keywords
photoresist
film
pattern
layer
forming
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KR1020090049503A
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Korean (ko)
Inventor
임희열
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090049503A priority Critical patent/KR20100130801A/en
Publication of KR20100130801A publication Critical patent/KR20100130801A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Abstract

In the method of forming a semiconductor device fine pattern of the present invention, depositing a positive photoresist film on a hard mask, forming a negative photoresist film centering on the photoresist film, and exposing the two photoresist films to form a spacer. And forming a fine pattern using the spacers as a mask and simplifying the process and reducing the production cost while forming a fine pattern having the same pitch as compared to the conventional spacer patterning process. It provides a more advantageous effect on the spacer patterning process for implementation.

Description

Spacer patterning technology using positive-negative photoresist using positive-negative photoresist

The present invention relates to a method for manufacturing a semiconductor device, and discloses a technique for further simplifying an existing spacer process for forming a fine pattern and increasing a process yield.

As the integration density of semiconductor devices increases rapidly, the pattern becomes finer and more sophisticated, but the photolithography process technology has not been followed due to its fundamental limitations. In order to integrate as many elements as possible in a small area, the size of the individual elements should be made small. For this purpose, the pitch, which is the sum of the widths of the patterns and the spacing between the patterns, should be made small. Due to the resolution limitation of the photolithography process, there are many difficulties in forming a fine pitch in accordance with the design rule of the semiconductor device which is drastically reduced. In particular, the photolithography process for forming the device isolation region defining the active region of the substrate and the photolithography process for forming a line and space pattern have limitations in implementing a desired fine pattern. Currently, semiconductor technology trends are introducing process technology to realize patterns below 40nm, and recently, high NA (Phase Shift Mask), PSM (Phase Shift Mask), low wavelength, OPC (Optical Proximity Correction) and OAI The company is overcoming optical limitations by applying Resolution Enhancement Technology (RET) such as Off Axis Illumination. In addition, new technologies such as immersion, double patterning, and double exposure are being introduced. However, these techniques are currently only in the research stage to compensate for the problems caused when applied to the actual process, and are difficult to apply to the actual process. In particular, as the size of the pattern decreases, it is inevitable to reduce the thickness of the photoresist in terms of the photolithography process. Thus, reducing the thickness of the photoresist has been proposed as a factor of reducing the process margin in the etching process. It is urgent to introduce new technologies to implement.

Double patterning technology, which is used to overcome the resolution limitations in the photolithography process, is being researched to realize a 40nm-class pattern and has been shown to be mass-produced. The technique is briefly disclosed. After forming a center pattern that is repeatedly formed at a predetermined pitch using a photolithography process, spacers are formed on both sidewalls of the center pattern, and the spacers are removed. It is a method of patterning the etching target by using.

1A-1D disclose a method of reducing pitch using a conventional spacer patterning process.

Referring to FIG. 1A, a first oxide film 102, a first amorphous carbon (a-Carbon) 104, a polysilicon 106, a second oxide film 108, and a second aC may be disposed on a semiconductor substrate 100. (110), silicon oxynitride 112 is sequentially deposited, and an antireflection film 114 is further deposited.

Subsequently, a photoresist (not shown) is coated on the antireflection film 114, and a mask is formed on the upper surface. The photoresist pattern is exposed and developed to have a line line width (CD): space line width (CD) of 1: 3. Form 115.

Referring to FIG. 1B, a second amorphous carbon formed by etching the lower etched layer using the first photoresist pattern 115 as a mask by an etchback process until the second oxide layer 108 is exposed. aC) The material remaining on the pattern 110a is etched and removed. Next, the spacer material 120 is deposited on the entire surface of the second oxide film 108 and the second a-C pattern 110a.

Referring to FIG. 1C, when the spacer material 120 is anisotropically etched and the remaining spacer material on the upper portion of the second oxide layer 108 and the upper portion of the second aC pattern 110a is removed, the spacer 120P is formed on the sidewall of the second oxide layer 108. Is formed. In this case, the spacer material 120 may use a nitride film. Next, the second a-C pattern 110a except for the spacer 120P is etched and removed by an etchback process.

Referring to FIG. 1D, the second oxide layer 108 is etched using the spacer 120P as an etch barrier to form a second oxide layer pattern 108a, and then the spacer 120P is removed.

Referring to FIG. 1E, the lower etched layer is etched using the second oxide film pattern 108a as a mask and then polished to the first aC 104 so that the pitch is twice the pitch of the photoresist pattern 115 in FIG. 1A. The reduced fine pattern may be formed, and in this case, the first oxide layer pattern 102a represents a pad pattern of the ferry region and is patterned by forming a pad mask on the top. The first oxide pattern 102a and the first a-C 104 above the fine pattern may remain for etching margin and then are removed through a strip process.

However, compared to the single process, the process increases the number of hard mask steps by 4-6 and the etching process increases accordingly, which makes the order of the process very complicated, which is very disadvantageous in mass productivity. Therefore, the present invention is to disclose a technology for a process that can be more simple and mass production by supplementing the disadvantage of the spacer patterning process (Spacer Patterning Technology) for implementing the current 40nm pattern.

An object of the present invention is to simplify the existing complex mask and etching process in the spacer patterning process to improve the process yield.

According to an embodiment of the present invention, a first photoresist layer pattern is formed on an etched layer, a second photoresist layer pattern having different physical properties from the first photoresist layer pattern is formed on sidewalls of the first photoresist layer pattern, and the first photoresist layer is exposed through an exposure process. And removing the pattern to form a second photoresist spacer and etching the etched layer using the second photoresist spacer as a mask.

Preferably, the etched layer is formed of a laminated structure of an oxide film, amorphous carbon and polysilicon.

Preferably, the oxide film is characterized in that using PE-TEOS.

Preferably, the method further includes depositing an anti-reflection film on the etched layer.

Preferably, the forming of the first photoresist layer pattern includes applying a first photoresist layer on the etched layer and forming a mask on the first photoresist layer such that a ratio of line line width to space line width is 1: 3. Exposing and developing.

Preferably, the forming of the second photoresist pattern includes applying a second photoresist layer so as to fill the first photoresist pattern, and having a line width three times the center of the first photoresist pattern on the second photoresist layer. Forming an open mask, and exposing and developing the mask.

Preferably, the first photoresist layer is a positive photoresist film, and the second photoresist layer is a negative photoresist film.

Preferably, the first photoresist layer is a negative photoresist layer, and the second photoresist layer is a positive photoresist layer.

Preferably, the forming of the second photoresist film spacer includes etching and developing the upper portion so that the first photoresist pattern is exposed when the second photoresist film covers the first photoresist film.

Preferably, the forming of the second photoresist film spacer includes immediately performing development when the second photoresist film does not cover the first photoresist film.

As described above, the present invention is a further additional process in addition to only two exposure processes compared to the additional four to six hard masks and deposition and etching processes required in the conventional spacer pattern process. Since this does not occur, the process yield is simpler and the yield is greatly increased. In addition, since a pattern of 40 nm or less can be realized by a single etching process using a hard mask as it is, a single process provides an advantageous effect in forming a fine pattern according to a rapidly reduced design rule of a semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The present invention provides a method of manufacturing a semiconductor device for forming a fine pattern using a photosensitive film having different physical properties. Here, the photosensitive film having different physical properties means a reaction property to an exposure light source, and defines a film in which the photosensitive film remains or is removed according to the reaction property.

2A through 2E are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with an embodiment of the present invention.

Referring to FIG. 2A, an oxide layer 202, an amorphous carbon 205, and a polysilicon 207, which are etched layers, are sequentially deposited on the semiconductor substrate 200. At this time, it is preferable to form the anti-reflection film 210 on the top.

Next, a positive photoresist film (not shown) is applied to the entire surface of the anti-reflection film 210, and then a mask is formed on the upper surface so that the ratio of line line width CD to space line width CD is 1: 3. The photosensitive film pattern 215 is formed by exposure and development. The positive photoresist is a photoresist in which light-transmitted light-transmitting regions are dissolved and removed during development.

Referring to FIG. 2B, a negative photoresist film 220 is deposited on the entire surface of the anti-reflection film 210 and the first photoresist pattern 215. In this case, the negative photoresist layer 220 should not react with the first photoresist pattern 215. Here, the negative photoresist film 220 is a photoresist in which light-transmitted light-transmitting regions remain without melting during development.

Referring to FIG. 2C, as a process of performing a second exposure, a mask is formed on the first photoresist pattern 215 to open a mask three times the line width, and is exposed and developed. In this case, since the negative photoresist film is a photoresist in which the light-receiving portion remains undeveloped, the second photoresist pattern 220a in which the negative photoresist film surrounds both sides of the first photoresist pattern 215 when the exposure and development are performed. ) Is formed. Since the second photoresist pattern becomes a spacer for forming a fine pattern in a subsequent process to determine the width of the micropattern, the size of the second photoresist pattern 220a must be expanded by the same ratio around the first photoresist pattern 215. To be exposed. In the present invention, three times the exposure is performed to uniformize the size of the pattern, but it is possible to form a mask intentionally misaligned according to the shape of the desired pattern and to expose it.

Referring to FIG. 2D, even when the negative photoresist is covered as a transparent layer, even when the second photoresist pattern 220a covers the first photoresist pattern 215 because light has already passed through the exposure process performed in FIG. 2C. When the development is performed by exposing the first photoresist pattern 215 to the upper portion through an etchback process, the first photoresist pattern 215 is dissolved and removed, and the second photoresist pattern 220a remains, so that the second photoresist film is left. Spacer 220b is formed. If the first photoresist pattern 215 is exposed, the first photoresist pattern 215 is removed at the same time in the process of FIG. 2C, which is developed to form the second photoresist pattern 220a.

Referring to FIG. 2E, the anti-reflection film 210, the polysilicon 207, the a-Carbon 205, and the oxide film 202 at the bottom of the etched layer are etched using the second photoresist spacer 220b as a mask and then a- The fine pattern can be patterned by polishing up to the carbon 205. In this case, the oxide layer pattern 202a is a pad pattern formed in the ferry region. The oxide layer pattern 202a is patterned by a pad mask on the upper side, and may be arbitrarily formed. At this time, the oxide pattern 202a and the a-C 205 on the fine pattern may remain for the etching margin and then are removed by the strip process.

As described above, in the embodiment according to the present invention, a case in which the first photoresist film is a positive photoresist film and the second photoresist film is a negative photoresist film has been described. Furthermore, in another embodiment according to the present invention, a semiconductor device may be manufactured by using a first photosensitive film as a negative photosensitive film and a second photosensitive film as a positive photosensitive film.

That is, the present invention is a technique that can implement a fine pattern having the same pitch by performing only two exposure processes compared to the conventional spacer patterning process. Therefore, when the present invention is applied, the progress of the process is very simplified, thereby lowering the manufacturing cost and increasing the production yield.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as being in scope.

1A-1E are cross-sectional views illustrating a conventional spacer patterning process.

2A-2E are cross-sectional views illustrating a spacer patterning process of the present invention.

Claims (10)

Forming a first photoresist pattern on the etched layer; Forming a second photoresist pattern having different physical properties from the first photoresist pattern on a sidewall of the first photoresist pattern; Removing the first photoresist pattern through an exposure process to form a second photoresist spacer; And Etching the etched layer using the second photoresist spacer as a mask Semiconductor device manufacturing method comprising a. The method of claim 1, The etching target layer is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of oxide film, amorphous carbon and polysilicon. 3. The method of claim 2, The oxide film is a semiconductor device manufacturing method characterized in that using PE-TEOS. The method of claim 1, And depositing an anti-reflection film on the etched layer. The method of claim 1, The forming of the first photoresist layer pattern may include applying a first photoresist layer on the etched layer; And And exposing and developing a mask on the first photoresist layer so that a ratio of line width to space line width is 1: 3. The method of claim 1, The forming of the second photoresist layer pattern may include applying a second photoresist layer to fill the first photoresist pattern; And And exposing and developing a mask that opens a line width three times around the first photoresist pattern on the second photoresist layer. The method of claim 1, The first photosensitive film is a positive photosensitive film, the second photosensitive film is a semiconductor device manufacturing method, characterized in that the negative (Negative) photosensitive film. The method of claim 1, The first photoresist film is a negative photoresist film, and the second photoresist film is a positive photosensitive film, characterized in that the semiconductor device manufacturing method. The method of claim 1, The forming of the second photoresist film spacer includes etching the upper part to expose the first photoresist pattern when the second photoresist film covers the first photoresist film, and then developing the semiconductor device. The method of claim 1, The forming of the second photoresist film spacer may include performing development directly when the second photoresist film does not cover the first photoresist film.
KR1020090049503A 2009-06-04 2009-06-04 Spacer patterning technology using positive-negative photoresist KR20100130801A (en)

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