KR20100128208A - Liquid crystal display and fabricating method thereof - Google Patents

Abstract

PURPOSE: A liquid crystal display and a method for manufacturing the same are provided to reduce the generation of stains due to external light by forming a common electrode using a single transparent conductive film with an embossing shape. CONSTITUTION: A gate line is formed using a first conductive pattern. A common line is separated from the gate line and is formed using the first conductive pattern. A thin film transistor(6) is formed on an intersection part of the gate line and the data line. A common electrode(19) is formed in a pixel region using a third conductive pattern and is in connection with the common line. The third conductive pattern is composed of a single transparent conductive film with an embossing shape.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY AND FABRICATING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method of manufacturing the same, which can reduce the surface reflection and increase the contrast ratio.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. The liquid crystal display is roughly classified into a vertical electric field application type and a horizontal electric field application type according to the direction of the electric field for driving the liquid crystal.

The vertical field application type liquid crystal display drives a liquid crystal of TN (twisted nematic, hereinafter, "TN") mode by a vertical electric field formed between a pixel electrode and a common electrode disposed to face the upper and lower substrates. Vertical field-applied liquid crystal display devices have an advantage of large aperture ratio while having a narrow disadvantage of reagents.

The horizontal field application type liquid crystal display drives an in-plane switch (“IPS”) liquid crystal by a horizontal electric field formed between a pixel electrode and a common electrode arranged side by side on a lower substrate. Horizontal field-applied liquid crystal displays have a relatively wide viewing angle.

The horizontal field application liquid crystal display device includes a thin film transistor array substrate (bottom plate) and a color filter array substrate (top plate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The thin film transistor array substrate includes a plurality of signal lines and a thin film transistor for forming a horizontal electric field in pixels, and an alignment layer coated thereon for liquid crystal alignment. The color filter array substrate includes a color filter for color implementation, a black matrix for preventing light leakage, and an alignment film coated thereon for liquid crystal alignment. Liquid crystals vary light transmittance by a horizontal electric field formed between the pixel electrode and the common electrode.

In such a liquid crystal display device, the pixel electrode and the common electrode are typically formed of a single transparent conductive film or a single metal film.

When the pixel electrode and the common electrode are formed of a single metal film, the metal has a high reflectance and thus has a strong property of reflecting external light incident on the display surface. The reflected external light passes through the polarizing plate after generating constructive or destructive interference with light incident from the backlight of the liquid crystal display, and thus, diffraction patterns are easily generated on the display image of the part where the external light is reflected.

When the pixel electrode and the common electrode are formed of a transparent conductive film for reducing the reflectance, the reflectance is lowered but the contrast ratio is deteriorated due to the degradation of the black luminance due to the increase in the transmittance.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which reduce the reflectance of the electrode surface to external light and increase the contrast ratio of the display image.

In order to achieve the above object, a liquid crystal display according to an embodiment of the present invention comprises a gate line formed of a first conductive pattern; A common line separated from the gate line and formed of the first conductive pattern; A data line crossing the gate line and the common line so as to be insulated from each other, and defining a pixel area, wherein the data line is formed of a second conductive pattern; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region in a third conductive pattern and connected to the common line; A pixel electrode connected to the thin film transistor and formed in the third conductive pattern to form a horizontal electric field with the common electrode in the pixel region; The third conductive pattern includes a double layer including a metal layer and a low reflection layer formed on the metal layer.

The low reflection film may include a nitride material or an oxide material.

The low reflection film includes at least one of CuNx, MoTiNx, ITO, IZO, TO, CrOx.

The thickness of the low reflection film is 30 kPa to 1000 kPa.

The liquid crystal display includes: a gate pad having a gate pad lower electrode connected to the gate line and a gate pad upper electrode contacting the gate pad lower electrode through a contact hole; A data pad having a data pad lower electrode connected to the data line and a data pad upper electrode contacting the data pad lower electrode through a contact hole; And a common pad having a common pad lower electrode connected to the common line and a common pad upper electrode contacting the common pad lower electrode through a contact hole; The gate pad upper electrode, the data pad upper electrode, and the common pad upper electrode are formed of the third conductive pattern.

In another embodiment, a liquid crystal display includes: a gate line formed of a first conductive pattern; A common line separated from the gate line and formed of the first conductive pattern; A data line crossing the gate line so as to be insulated from the gate line and defining a pixel area, wherein the data line is formed of a second conductive pattern; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode connected to the common line and formed of a third conductive pattern; A pixel electrode connected to the thin film transistor and formed of the third conductive pattern to form an electric field with the common electrode in the pixel region; The third conductive pattern is made of a transparent conductive film whose surface is embossed through a haze treatment.

The transparent conductive film contains ITO or IZO.

The pixel electrode forms a horizontal electric field or a vertical electric field with the common electrode.

According to an exemplary embodiment of the present invention, a method of manufacturing a liquid crystal display device includes forming a gate line, a gate electrode of a thin film transistor connected to the gate line, and a common line separated from the gate line in a first conductive pattern on a substrate. step; Forming a semiconductor pattern on a predetermined region on the gate insulating film after applying the gate insulating film to the entire surface; A data line defining a pixel region crossing the gate line and the common line as a second conductive pattern on the semiconductor pattern, a source electrode of a thin film transistor connected to the data line, and a thin film transistor facing the source electrode. Forming a drain electrode; After applying the passivation layer over the entire surface, patterning the passivation layer and the gate insulating layer to expose part of the common line and part of the drain electrode; Forming a common electrode connected to the exposed common line with a third conductive pattern; And forming a pixel electrode connected to the exposed drain electrode in the third conductive pattern so as to form a horizontal electric field in the pixel area opposite the common electrode; The third conductive pattern is formed of a double layer including a metal film and a low reflection film formed on the metal film.

According to another aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, including forming a gate line, a gate electrode of a thin film transistor connected to the gate line, and a common line separated from the gate line in a first conductive pattern on a substrate. step; Forming a semiconductor pattern on a predetermined region on the gate insulating film after applying the gate insulating film to the entire surface; A data line defining a pixel region crossing the gate line as a second conductive pattern on the semiconductor pattern, a source electrode of a thin film transistor connected to the data line, and a drain electrode of the thin film transistor facing the source electrode; Forming; After applying the passivation layer over the entire surface, patterning the passivation layer and the gate insulating layer to expose part of the common line and part of the drain electrode; Forming a common electrode connected to the exposed common line with a third conductive pattern; And forming a pixel electrode connected to the exposed drain electrode with the third conductive pattern so as to form an electric field in the pixel area opposite the common electrode; The third conductive pattern is formed of a transparent conductive film whose surface is embossed through a haze treatment.

The liquid crystal display according to the present invention and a method of manufacturing the same are formed by forming the third conductive pattern group constituting the electrode portion into a double layer including a metal film and a low reflection film, or by forming a single transparent conductive film having an embossed surface. In addition, while increasing the contrast ratio of the display image, the reflectance at the surface of the electrode with respect to the external light can be reduced, thereby greatly reducing the occurrence of spots caused by the external light.

Referring to Figures 1 to 9 will be described a preferred embodiment of the present invention. In the following embodiments, a thin film transistor array substrate of an in plane switching (IPS) mode manufactured through a four mask process and a method of manufacturing the same will be described as an example, but the technical spirit of the present invention will be described below. It is not limited to the electric field mode for driving.

<First Embodiment>

1 to 5b, a first embodiment of the present invention will be described. In the first embodiment, the pixel portion and the pad portion electrode are formed of a double layer including a metal film and a low reflection film formed on the metal film.

1 is a plan view illustrating a thin film transistor array substrate using a four mask process according to a first exemplary embodiment of the present invention, and FIG. 2 is a thin film transistor array substrate taken along lines II ′ and II-II ′ of FIG. 1. It is a cross section of.

The thin film transistor array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect a gate insulating layer 46 therebetween on a lower substrate 45, and a thin film formed at each intersection thereof. The transistor 6 includes a pixel electrode 14 and a common electrode 19 formed to form a horizontal electric field in a pixel region provided in a cross structure thereof, and a common line 16 connected to the common electrode 19. The thin film transistor substrate includes a storage capacitor 20 formed at an overlapping portion of the common line 16 and the pixel electrode 14, a gate pad 24 connected to the gate line 2, and a data line 4. The data pad 33 connected and the common pad 36 connected to the common line 16 are further provided.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure with the gate insulating film 46 therebetween to define the pixel region. Here, the gate line 2 is formed of a first conductive pattern (gate metal pattern), and the data line 4 is formed of a second conductive pattern (source / drain metal pattern).

The common line 16 and the common electrode 19 supply a reference voltage for driving the liquid crystal. The common line 16 includes an internal common line 16A formed to partially overlap the pixel electrode 14 in the display area, and an external common line 16B which commonly connects the internal common lines 16A in the non-display area. Include. The common line 16 is formed of a first conductive pattern.

The common electrode 19 is formed in parallel with the gate line 2 and is connected to the internal common line 16A through the second contact hole 15 penetrating through the gate insulating layer 46 and the passivation layer 52. 19A and finger-shaped finger portions 19B extending from the horizontal portion 19A to the pixel region. The common electrode 19 is formed of a third conductive pattern made of a double film including the metal film 35A and the low reflection film 35B.

The thin film transistor 6 is switched in response to the gate signal of the gate line 2 to charge the pixel signal of the data line 4 to the pixel electrode 14. To this end, the thin film transistor 6 includes a gate electrode 8 connected to the gate line 2, a source electrode 10 connected to the data line 4, and a drain electrode connected to the pixel electrode 14. 12). In addition, the thin film transistor 6 overlaps the gate electrode 8 and the internal common line 16A with the gate insulating layer 46 therebetween, and forms a channel between the source electrode 10 and the drain electrode 12. 48, an ohmic contact layer 50 formed on the active layer 48 except for the channel for ohmic contact with the source electrode 10 and the drain electrode 12 is further provided. The active layer 48 and the ohmic contact layer 50 are formed to overlap the data line 4 and the data pad lower electrode 32 formed in the second conductive pattern together with the source electrode 10 and the drain electrode 12. .

The pixel electrode 14 forms a horizontal electric field in parallel with the common electrode 19 in the pixel area. The pixel electrode 14 is connected to the drain electrode 12 of the thin film transistor 6 through the first contact hole 13 penetrating the passivation layer 52 and is formed in the pixel region. In particular, the pixel electrode 14 is connected to the drain electrode 12 and is formed in parallel with the adjacent gate line 2 and the horizontal portion 14A, and extends from the horizontal portion 14A to the pixel region to form the common electrode 19. A finger-shaped finger portion 14B formed in parallel with the finger portion 19B is provided. The pixel electrode 14 is formed of a third conductive pattern made of a double film including the metal film 35A and the low reflection film 35B.

In addition, the horizontal portion 14A and the outermost finger portion 14B of the pixel electrode 14 partially overlap the internal common line 16A with the gate insulating layer 46 and the passivation layer 52 interposed therebetween. 20). The storage capacitor 20 maintains the pixel signal of the current frame charged in the pixel electrode 14 until the pixel signal of the next frame is charged.

The gate line 2 is connected to a gate driver (not shown) through the gate pad 24. The gate pad 24 includes a gate pad lower electrode 26 extending from the gate line 2 and a gate pad lower electrode through the third contact hole 27 penetrating the gate insulating layer 46 and the passivation layer 52. And a gate pad upper electrode 28 connected with 26. The gate pad lower electrode 26 is formed of a first conductive pattern, and the gate pad upper electrode 28 is formed of a third conductive pattern composed of a double layer including a metal film 35A and a low reflection film 35B.

The data line 4 is connected to a data driver (not shown) through the data pad 30. The data pad 30 is connected to the data pad lower electrode 32 through the data pad lower electrode 32 extending from the data line 4 and the fourth contact hole 33 penetrating through the passivation layer 52. It consists of the pad upper electrode 34. The data pad lower electrode 32 is formed of a second conductive pattern, and the data pad upper electrode 34 is formed of a third conductive pattern formed of a double layer including a metal film 35A and a low reflection film 35B.

The common line 16 is connected to an external reference voltage source (not shown) through the common pad 36. The common pad 36 includes the common pad lower electrode 38 extending from the external common line 16B, and the common pad lower electrode through the fifth contact hole 39 penetrating through the gate insulating layer 46 and the passivation layer 52. The common pad upper electrode 40 connected with 38 is comprised. The common pad lower electrode 38 is formed of a first conductive pattern, and the common pad upper electrode 40 is formed of a third conductive pattern formed of a double layer including a metal film 35A and a low reflection film 35B.

The third conductive pattern constituting the pixel electrode 14, the common electrode 19, the gate pad upper electrode 28, the data pad upper electrode 34, and the common pad upper electrode 40 includes a metal film 35A. do. Therefore, according to the present invention, as compared with forming the third conductive pattern using only a single transparent conductive film, the increase in transmittance can be suppressed to increase the contrast ratio of the image. However, when the third conductive pattern is formed of only a single metal film, a problem occurs in that the metal film having high reflectance diffuses the external light and degrades the display quality. Therefore, the present invention provides a low reflective film 35B on the metal film 35A. Further forms. The low reflection film 35B includes a nitride material or an oxide material to reduce surface reflectance of external light.

A manufacturing method of a thin film transistor substrate having such a configuration will be described using a four mask process as follows.

Referring to FIG. 3A, a gate line 2, a gate electrode 8, a gate pad lower electrode 26, a common line 16, and a common pad lower electrode may be formed on the lower substrate 45 through a first mask process. A first conductive pattern group including 38) is formed.

In detail, the first conductive material is formed on the lower substrate 45 through a deposition method such as a sputtering method. Subsequently, the first conductive material is patterned by a photolithography process and an etching process using the first mask to form a gate line 2, a gate electrode 8, a gate pad lower electrode 26, a common line 16, and a common pad. A first conductive pattern group including the lower electrode 38 is formed. Here, Cr, MoW, MoTi, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) may be used as the first conductive material.

Referring to FIG. 3B, the gate insulating layer 46 is coated on the lower substrate 45 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating layer 46, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) may be used. Next, the semiconductor pattern including the active layer 48 and the ohmic contact layer 50 on the gate insulating layer 46 using the second mask process, the data line 4, the source electrode 10, and the drain electrode 12. And a second conductive pattern group including the data pad lower electrode 32.

In detail, an amorphous silicon layer, an n + amorphous silicon layer, and a second conductive material are sequentially formed on the lower substrate 45 on which the gate insulating layer 46 is formed through a deposition method such as PECVD or sputtering. Here, as the second conductive material, Cr, MoW, MoTi, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) may be used. Subsequently, a photoresist pattern is formed on the second conductive material by a photolithography process using a second mask. As the second mask, a diffraction exposure mask or a semi-transmissive mask having a diffraction exposure portion in the channel portion of the thin film transistor is used. The second mask has a photoresist pattern of which the channel portion is lower than the photoresist pattern of another portion of the second conductive pattern group. Have a height. Subsequently, the second conductive material is patterned by a wet etching process using a photoresist pattern, such that the data line 4, the source electrode 10, the drain electrode 12 integrated with the source electrode 10, and the lower data pad electrode ( A second conductive pattern group including 32) is formed. Then, the ohmic contact layer 50 and the active layer 48 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern. After the ashing process using the oxygen (O 2) plasma is removed, the photoresist pattern having a relatively low height is removed from the channel portion, and then the source / drain metal pattern and the ohmic contact layer 50 of the channel portion are removed by a dry etching process. Etched. Accordingly, the active layer 48 of the channel portion is exposed to separate the source electrode 10 and the drain electrode 12. Subsequently, all of the photoresist patterns remaining on the second conductive pattern group are removed by the stripping process.

Referring to FIG. 3C, a passivation layer including first to fifth contact holes 13, 15, 27, 33, and 39 may be formed on the gate insulating layer 46 on which the second conductive pattern group is formed by using a third mask process. 52) is formed.

In detail, the protective film 52 is entirely formed on the gate insulating film 46 on which the second conductive pattern group is formed by a deposition method such as PECVD. As the material of the protective film 52, an inorganic insulating material similar to the gate insulating film 46, or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used. Subsequently, the passivation layer 52 is patterned by a photolithography process and an etching process through the third mask to form first to fifth contact holes 13, 21, 27, 33, and 39. The first contact hole 13 penetrates the passivation layer 52 to expose the drain electrode 12, and the second contact hole 15 penetrates the passivation layer 52 and the gate insulating layer 46 to form an internal common line 16A. ). The third contact hole 27 penetrates the passivation layer 52 and the gate insulating layer 46 to expose the gate pad lower electrode 26, and the fourth contact hole 33 penetrates the passivation layer 52 to lower the data pad. The electrode 32 is exposed, and the fifth contact hole 39 passes through the passivation layer 52 and the gate insulating layer 46 to expose the common pad lower electrode 38.

Referring to FIG. 3D, a pixel electrode 14, a common electrode 19, a storage upper electrode 22, and a gate pad upper electrode 28 each configured as a double layer on the passivation layer 52 using a fourth mask process. The third conductive pattern group including the data pad upper electrode 34 and the common pad upper electrode 40 is formed.

In detail, as shown in FIG. 4A, a metal material is coated on the lower substrate 45 on which the passivation layer 52 including the contact holes 13, 15, 27, 33, and 39 is formed. As the metal material, Cr, MoW, MoTi, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) may be used. Subsequently, as shown in FIGS. 4B and 4C, on the lower substrate 45 on which the metal material is formed, reactive reactive metals such as Cu, Cr, and MoTi react with nitrogen (N 2) plasma or oxygen (O 2) plasma. A sputtering process is performed to form a low reflective material. In this case, as the low reflection material, a nitride-based material such as CuNx or MoTiNx is used.

In the reactive reactive sputtering process, a transparent conductive target such as ITO, IZO, or TO may be used instead of the metal target. In this case, an oxide-based material such as ITO, IZO, TO, CrOx, or the like is used as the low reflection material.

The deposition thickness of the low reflective material is preferably 30 kPa to 1000 kPa. If the thickness of the low reflective material is less than 30 GPa, the function of reducing the surface reflectance is reduced. If the thickness of the low reflective material is more than 1000 GPa, the deposition quality decreases with luminance decrease.

Subsequently, the metal material and the low reflection material are simultaneously patched through a photolithography process and an etching process using a fourth mask, thereby respectively providing a pixel electrode 14 having a double layer (metal film 35A + low reflection film 35B), A third conductive pattern group including the common electrode 19, the gate pad upper electrode 28, the data pad upper electrode 34, and the common pad upper electrode 40 is formed. The pixel electrode 14 is electrically connected to the drain electrode 12 through the first contact hole 13. The common electrode 19 is electrically connected to the internal common line 16A through the second contact hole 15. The gate pad upper electrode 28 is electrically connected to the gate pad lower electrode 26 through the third contact hole 27. The data pad upper electrode 34 is electrically connected to the data lower electrode 32 through the fourth contact hole 33. The common pad upper electrode 40 is electrically connected to the common pad lower electrode 38 through the fifth contact hole 39.

Fig. 5A shows the reflectance of the present invention in the case where the third conductive pattern group is formed from a double layer containing a low reflection film of nitride material, and the conventional case in the case of forming the third conductive pattern group from a single metal film. The simulation results are compared with the reflectance of. In FIG. 5A, the vertical axis represents reflectance (%) and the horizontal axis represents wavelength (nm), respectively. The graph 'A' shows the reflectance when the third conductive pattern group is formed of the MoTi single layer, and the graph 'B' shows the reflectance at the middle portion of the third conductive pattern group formed of the double layer of MoTi and CuNx. The graph 'C' represents the reflectances at the edge portions of the third conductive pattern group formed of the double films of MoTi and CuNx, respectively.

As shown in FIG. 5A, it can be seen that the surface reflectances of the present invention of graphs 'B' and 'C' are greatly reduced compared to the conventional reflectivity of graph 'A'.

FIG. 5B shows the reflectance of the present invention in the case where the third conductive pattern group is formed of a double layer containing a low reflection film of an oxide material, and the conventional case in the case where the third conductive pattern group is formed of a single metal film. Show simulation results compared to reflectance. In FIG. 5B, the vertical axis represents reflectance (%) and the horizontal axis represents wavelength (nm), respectively. The graph 'A' shows the reflectance when the third conductive pattern group is formed of a single MoTi film, and the graph 'B' shows the reflectivity when the third conductive pattern group is formed with a double layer of MoTi and ITO (100 kV). The reflectance, graph 'C' is the reflectivity when the third conductive pattern group is formed by the double film of MoTi and ITO (200 mW), and the graph 'D' is the third film of the second film of MoTi and ITO (300 mW). The reflectance at the time of forming a conductive pattern group is shown, respectively.

As shown in FIG. 5B, it can be seen that the surface reflectances of the present invention of graphs 'B' to 'D' are greatly reduced compared to the conventional reflectivity of graph 'A'. Since the low reflection film serves to absorb external light, the effect of reducing the surface reflectance increases as the thickness of the low reflection film is increased within a predetermined range (30 mW to 1000 mW).

As described above, the liquid crystal display device and the manufacturing method thereof according to the first embodiment of the present invention form the third conductive pattern group such as the pixel electrode as a double film including a metal film and a low reflection film, thereby providing contrast of the display image. While increasing the ratio, it is possible to reduce the reflectance of the electrode surface to the external light, thereby greatly reducing the occurrence of spots caused by the external light. The liquid crystal display device and the method of manufacturing the same according to the first embodiment of the present invention, in addition to the liquid crystal display device of the IPS mode described above, any configuration having a finger structure while the pixel electrode and the common electrode form a horizontal electric field, for example, FFS (Fringe) The same applies to the liquid crystal display of the field switching mode.

Second Embodiment

6 to 9, a second embodiment of the present invention will be described. In the second embodiment, the pixel portion and the pad portion electrode are formed of a single transparent conductive film whose surface is embossed through a haze treatment.

FIG. 6 is a plan view illustrating a thin film transistor array substrate using a four mask process according to a second exemplary embodiment of the present invention, and FIG. 7 is a thin film transistor array substrate taken along lines II ′ and II-II ′ of FIG. 6. It is a cross section of.

The thin film transistor array substrate illustrated in FIGS. 6 and 7 includes a gate line 102 and a data line 104 formed to intersect on the lower substrate 145 with a gate insulating layer 146 therebetween, and a thin film formed at each intersection thereof. A transistor 106, a pixel electrode 114 and a common electrode 119 formed so as to form a horizontal electric field in a pixel region provided in an intersecting structure thereof, and a common line 116 connected to the common electrode 119 is provided. The thin film transistor substrate includes a storage capacitor 120 formed at an overlapping portion of the common line 116 and the pixel electrode 114, a gate pad 124 connected to the gate line 102, and a data line 104. The data pad 133 connected and the common pad 136 connected to the common line 116 are further provided.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure with the gate insulating layer 146 therebetween to define the pixel region. Here, the gate line 102 is formed of a first conductive pattern (gate metal pattern), and the data line 104 is formed of a second conductive pattern (source / drain metal pattern).

The common line 116 and the common electrode 119 supply a reference voltage for driving the liquid crystal. The common line 116 includes an internal common line 116A formed to partially overlap the pixel electrode 114 in the display area, and an external common line 116B which commonly connects the internal common lines 116A in the non-display area. Include. The common line 116 is formed of a first conductive pattern.

The common electrode 119 is formed in parallel with the gate line 102 and is connected to the internal common line 116A through the second contact hole 115 passing through the gate insulating layer 146 and the passivation layer 152. 119A and a finger-shaped finger portion 119B extending from the horizontal portion 119A to the pixel region. The common electrode 119 is formed of a third conductive pattern whose surface is a single transparent conductive pattern having an embossing shape.

The thin film transistor 106 is switched in response to the gate signal of the gate line 102 to charge the pixel signal of the data line 104 to the pixel electrode 114. To this end, the thin film transistor 106 may include a gate electrode 108 connected to the gate line 102, a source electrode 110 connected to the data line 104, and a drain electrode connected to the pixel electrode 114. 112). In addition, the thin film transistor 106 overlaps the gate electrode 108 and the internal common line 116A with the gate insulating layer 146 therebetween and forms a channel between the source electrode 110 and the drain electrode 112. And an ohmic contact layer 150 formed on the active layer 148 except for the channel for ohmic contact with the source electrode 110 and the drain electrode 112. The active layer 148 and the ohmic contact layer 150 are formed to overlap the data line 104 and the data pad lower electrode 132 formed in the second conductive pattern together with the source electrode 110 and the drain electrode 112. .

The pixel electrode 114 forms a horizontal electric field in parallel with the common electrode 119 in the pixel area. The pixel electrode 114 is connected to the drain electrode 112 of the thin film transistor 106 through the first contact hole 113 passing through the passivation layer 152 and is formed in the pixel region 105. In particular, the pixel electrode 114 is connected to the drain electrode 112 and is formed in parallel with the adjacent gate line 102. The pixel electrode 114 extends from the horizontal portion 114A to the pixel area and extends from the common electrode 119. A finger-shaped finger portion 114B formed in parallel with the finger portion 119B is provided. The pixel electrode 114 is formed of a third conductive pattern whose surface is a single transparent conductive pattern having an embossing shape.

In addition, the horizontal portion 114A and the outermost finger portion 114B of the pixel electrode 114 partially overlap the internal common line 116A with the gate insulating layer 146 and the passivation layer 152 interposed therebetween. 120). The storage capacitor 120 stably maintains the pixel signal of the current frame charged in the pixel electrode 114 until the pixel signal of the next frame is charged.

The gate line 102 is connected to a gate driver (not shown) through the gate pad 124. The gate pad 124 is formed through the gate pad lower electrode 126 extending from the gate line 102 and the third contact hole 127 penetrating through the gate insulating layer 146 and the passivation layer 152. 126 and a gate pad upper electrode 128 connected thereto. The gate pad lower electrode 126 is formed of a first conductive pattern, and the gate pad upper electrode 128 is formed of a third conductive pattern whose surface is a single transparent conductive pattern having an embossing shape.

The data line 104 is connected to a data driver (not shown) through the data pad 130. The data pad 130 is connected to the data pad lower electrode 132 through the data pad lower electrode 132 extending from the data line 104 and the fourth contact hole 133 penetrating the passivation layer 152. The pad upper electrode 134 is formed. The data pad lower electrode 132 is formed of a second conductive pattern, and the data pad upper electrode 134 is formed of a third conductive pattern whose surface is a single transparent conductive pattern having an embossing shape.

The common line 116 is connected to an external reference voltage source (not shown) through the common pad 136. The common pad 136 has a common pad lower electrode 138 extending from the external common line 116B, and a common pad lower electrode through the fifth contact hole 139 penetrating through the gate insulating layer 146 and the passivation layer 152. And a common pad upper electrode 140 connected to 138. The common pad lower electrode 138 is formed of a first conductive pattern, and the common pad upper electrode 140 is formed of a third conductive pattern whose surface is a single transparent conductive pattern having an embossing shape.

The third conductive pattern constituting the pixel electrode 114, the common electrode 119, the gate pad upper electrode 128, the data pad upper electrode 134, and the common pad upper electrode 140 has an embossed surface. It consists of a single transparent conductive film having. The third conductive pattern scatters incident external light at its embossed surface to significantly reduce the amount of reflection of external light that may cause constructive or destructive interference with light incident from the backlight of the liquid crystal display, thereby reducing Reduce surface reflectance. In addition, the third conductive pattern having the embossed surface suppresses the increase in transmittance as compared with the case where the surface is flat, thereby increasing the contrast ratio of the image.

The manufacturing method of the thin film transistor substrate having such a configuration differs only from forming the third conductive pattern group in comparison with the manufacturing method in FIGS. 3A to 4C, and the rest are substantially the same. Therefore, below, only the method of forming a 3rd conductive pattern group is demonstrated.

After the first to third mask processes, a passivation layer 152 including contact holes 113, 115, 127, 133, and 139 together with the first and second conductive pattern groups is formed on the substrate 145. . The pixel electrode 114, the common electrode 119, the storage upper electrode 122, the gate pad upper electrode 128, and the data pad each having an embossed surface on the passivation layer 152 using a fourth mask process. A third conductive pattern group of the transparent conductive material including the upper electrode 134 and the common pad upper electrode 140 is formed.

In detail, as illustrated in FIG. 8A, a transparent conductive material is coated on the lower substrate 145 on which the protective film 152 is formed by a deposition method such as sputtering. ITO, IZO, or the like may be used as the transparent conductive material. Subsequently, SiH4 or NH3 gas is injected into the process chamber maintained at a predetermined temperature and pressure to plasma-process the transparent conductive material formed on the lower substrate 145. Through the plasma treatment process, the surface of the transparent conductive material is hazed in an embossed form as shown in FIG. 8C. The predetermined pressure for this is less than 500 mmTorr, the predetermined temperature is preferably set to 200 ℃ ~ 700 ℃. In the haze treatment process, the oxygen component of the transparent conductive material and the hydrogen component of the injection gas react with each other in a plasma atmosphere to generate water, and the chemical reaction reduces the indium (In) component of the transparent conductive material. Is generated. In addition, the surface of the transparent conductive material is increased by the reducing action of the indium (In) component to increase the roughness (Roughness) as shown in Figure 9 to have a distinct embossing form.

When the haze treatment is completed, the transparent conductive material is etched through the photolithography process and the etching process using the fourth mask, so that each of the pixel electrode 114, the common electrode 119, and the upper portion of the gate pad having an embossed surface are formed. A third conductive pattern group including the electrode 128, the data pad upper electrode 134, and the common pad upper electrode 140 is formed. The pixel electrode 114 is electrically connected to the drain electrode 112 through the first contact hole 113. The common electrode 119 is electrically connected to the internal common line 116A through the second contact hole 115. The gate pad upper electrode 128 is electrically connected to the gate pad lower electrode 126 through the third contact hole 127. The data pad upper electrode 134 is electrically connected to the data lower electrode 132 through the fourth contact hole 133. The common pad upper electrode 140 is electrically connected to the common pad lower electrode 138 through the fifth contact hole 139.

As described above, the liquid crystal display device and the manufacturing method thereof according to the second embodiment of the present invention form the display image by forming the third conductive pattern group such as the pixel electrode into a single transparent conductive film having an embossed surface. It is possible to reduce the reflectance at the electrode surface to external light while increasing the contrast ratio of the light, thereby greatly reducing the occurrence of spots caused by external light. Compared to the first embodiment, the second embodiment of the present invention has a wider applicable range and is advantageous in terms of processing time and material cost. Since the liquid crystal display device and the manufacturing method thereof according to the second embodiment form the electrode part using only the haze-treated transparent conductive film, the first embodiment is performed due to not only the horizontal electric field mode but also the brightness deterioration problem (because it contains the metal film). It is also sufficiently applicable to the vertical electric field mode, which is difficult to apply in the example. In other words, the technique proposed through the second embodiment may be applied to any mode for forming an electrode part using a transparent conductive film, for example, an IPS mode, a FFS (Fringe Field Switching) mode, a TN mode, a Vertical Alignment (VA) mode, or the like. have. In addition, since the liquid crystal display device and the manufacturing method thereof according to the second embodiment form the electrode portion with a single transparent conductive film, the process time is shorter and the material cost is shorter than that of the first embodiment in which the electrode portion is formed with the double layer. .

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing a thin film transistor array substrate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate taken along lines II ′ and II-II ′ of FIG. 1.

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor substrate.

4a-4c show details of the process of FIG. 3d.

Fig. 5A shows the reflectance of the present invention in the case where the third conductive pattern group is formed from a double layer containing a low reflection film of nitride material, and the conventional case in the case of forming the third conductive pattern group from a single metal film. Graph showing simulation results compared to the reflectance of.

FIG. 5B shows the reflectance of the present invention in the case where the third conductive pattern group is formed of a double layer containing a low reflection film of an oxide material, and the conventional case in the case where the third conductive pattern group is formed of a single metal film. Graph showing simulation results compared to reflectance.

6 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the thin film transistor array substrate taken along lines II ′ and II-II ′ of FIG. 6.

8A to 8C show a haze treatment process.

Figure 9 is an enlarged photograph showing the surface of the transparent conductive material before and after the haze treatment.

<Description of Symbols for Main Parts of Drawings>

2: gate line 4: data line

6: thin film transistor 8: gate electrode

10 source electrode 12 drain electrode

13, 15, 27, 33, 39: contact hole 14: pixel electrode

16 common line 19 common electrode

20: storage capacitor 22: storage upper electrode

24: gate pad 26: gate pad lower electrode

28: gate pad upper electrode 30: data pad

32: data pad lower electrode 34: data pad upper electrode

36: common pad 38: common pad lower electrode

40: common pad upper electrode 45: substrate

46: gate insulating film 48: active layer

50: ohmic contact layer 52: protective film

Claims (18)

A gate line formed of a first conductive pattern; A common line separated from the gate line and formed of the first conductive pattern; A data line crossing the gate line and the common line so as to be insulated from each other, and defining a pixel area, wherein the data line is formed of a second conductive pattern; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode formed in the pixel region in a third conductive pattern and connected to the common line; A pixel electrode connected to the thin film transistor and formed in the third conductive pattern to form a horizontal electric field with the common electrode in the pixel region; And the third conductive pattern comprises a double layer including a metal film and a low reflection film formed on the metal film. The method of claim 1, The low reflection film may include a nitride material or an oxide material. The method of claim 2, The low reflection film comprises at least one of CuNx, MoTiNx, ITO, IZO, TO, CrOx. The method of claim 1, And the thickness of the low reflection film is in the range of 30 mW to 1000 mW. The method of claim 1, A gate pad having a gate pad lower electrode connected to the gate line and a gate pad upper electrode contacting the gate pad lower electrode through a contact hole; A data pad having a data pad lower electrode connected to the data line and a data pad upper electrode contacting the data pad lower electrode through a contact hole; And A common pad having a common pad lower electrode connected to the common line and a common pad upper electrode contacting the common pad lower electrode through a contact hole; And the gate pad upper electrode, the data pad upper electrode, and the common pad upper electrode are formed of the third conductive pattern. A gate line formed of a first conductive pattern; A common line separated from the gate line and formed of the first conductive pattern; A data line crossing the gate line so as to be insulated from the gate line and defining a pixel area, wherein the data line is formed of a second conductive pattern; A thin film transistor formed at an intersection of the gate line and the data line; A common electrode connected to the common line and formed of a third conductive pattern; A pixel electrode connected to the thin film transistor and formed of the third conductive pattern to form an electric field with the common electrode in the pixel region; The third conductive pattern is a liquid crystal display, characterized in that the surface is made of a transparent conductive film having an embossed surface through a haze treatment. The method of claim 6, The transparent conductive film comprises ITO or IZO. The method of claim 6, And the pixel electrode forms a horizontal electric field or a vertical electric field with the common electrode. The method of claim 6, A gate pad having a gate pad lower electrode connected to the gate line and a gate pad upper electrode contacting the gate pad lower electrode through a contact hole; A data pad having a data pad lower electrode connected to the data line and a data pad upper electrode contacting the data pad lower electrode through a contact hole; And A common pad having a common pad lower electrode connected to the common line and a common pad upper electrode contacting the common pad lower electrode through a contact hole; And the gate pad upper electrode, the data pad upper electrode, and the common pad upper electrode are formed of the third conductive pattern. Forming a gate line, a gate electrode of a thin film transistor connected to the gate line, and a common line separated from the gate line on a substrate with a first conductive pattern; Forming a semiconductor pattern on a predetermined region on the gate insulating film after applying the gate insulating film to the entire surface; A data line defining a pixel region crossing the gate line and the common line as a second conductive pattern on the semiconductor pattern, a source electrode of a thin film transistor connected to the data line, and a thin film transistor facing the source electrode. Forming a drain electrode; After applying the passivation layer over the entire surface, patterning the passivation layer and the gate insulating layer to expose part of the common line and part of the drain electrode; Forming a common electrode connected to the exposed common line with a third conductive pattern; And Forming a pixel electrode connected to the exposed drain electrode in the third conductive pattern so as to form a horizontal electric field in the pixel area opposite the common electrode; And the third conductive pattern is formed of a double layer including a metal film and a low reflection film formed on the metal film. The method of claim 10, The low reflection film may include a nitride material or an oxide material. The method of claim 11, The low reflection film comprises at least one of CuNx, MoTiNx, ITO, IZO, TO, CrOx manufacturing method of the liquid crystal display device. The method of claim 10, The thickness of the low reflection film is 30 kW ~ 1000 kW manufacturing method of the liquid crystal display device. The method of claim 10, Forming a gate pad including a gate pad lower electrode formed of the first conductive pattern and connected to the gate line and a gate pad upper electrode contacting the gate pad lower electrode through a contact hole; Forming a data pad including a data pad lower electrode formed of the second conductive pattern and connected to the data line and a data pad upper electrode contacting the data pad lower electrode through a contact hole; And Forming a common pad including the common pad lower electrode formed of the first conductive pattern and connected to the common line, and a common pad upper electrode contacting the common pad lower electrode through a contact hole; The gate pad upper electrode, the data pad upper electrode, and the common pad upper electrode are formed in the third conductive pattern. Forming a gate line, a gate electrode of a thin film transistor connected to the gate line, and a common line separated from the gate line on a substrate with a first conductive pattern; Forming a semiconductor pattern on a predetermined region on the gate insulating film after applying the gate insulating film to the entire surface; A data line defining a pixel region crossing the gate line as a second conductive pattern on the semiconductor pattern, a source electrode of a thin film transistor connected to the data line, and a drain electrode of the thin film transistor facing the source electrode; Forming; After applying the passivation layer over the entire surface, patterning the passivation layer and the gate insulating layer to expose part of the common line and part of the drain electrode; Forming a common electrode connected to the exposed common line with a third conductive pattern; And Forming a pixel electrode connected to the exposed drain electrode with the third conductive pattern so as to form an electric field opposite the common electrode in the pixel region; And the third conductive pattern is formed of a transparent conductive film having an embossed surface on the surface thereof through a haze treatment. The method of claim 15, The transparent conductive film is a manufacturing method of a liquid crystal display device comprising ITO or IZO. The method of claim 15, The gas used for the haze treatment is SiH4 or NH3. The method of claim 15, Forming a gate pad including a gate pad lower electrode formed of the first conductive pattern and connected to the gate line and a gate pad upper electrode contacting the gate pad lower electrode through a contact hole; Forming a data pad including a data pad lower electrode formed of the second conductive pattern and connected to the data line and a data pad upper electrode contacting the data pad lower electrode through a contact hole; And Forming a common pad including the common pad lower electrode formed of the first conductive pattern and connected to the common line, and a common pad upper electrode contacting the common pad lower electrode through a contact hole; The gate pad upper electrode, the data pad upper electrode, and the common pad upper electrode are formed in the third conductive pattern.

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