KR20100124179A - Submount bonding method and the apparatus - Google Patents

Submount bonding method and the apparatus Download PDF

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KR20100124179A
KR20100124179A KR1020090043297A KR20090043297A KR20100124179A KR 20100124179 A KR20100124179 A KR 20100124179A KR 1020090043297 A KR1020090043297 A KR 1020090043297A KR 20090043297 A KR20090043297 A KR 20090043297A KR 20100124179 A KR20100124179 A KR 20100124179A
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substrate
thermal expansion
temperature
bonding
coefficient
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KR1020090043297A
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Korean (ko)
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KR101589897B1 (en
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박기용
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박기용
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for bonding a substrate to a submount during the manufacturing process of a vertical light emitting diode device having excellent luminous efficiency and heat dissipation efficiency. The present invention relates to a difference in coefficient of thermal expansion during cooling by varying a heating temperature of a substrate and a submount. To prevent warpage.

In the submount substrate bonding method of the present invention, a substrate having a low thermal expansion coefficient is heated at a high temperature and a substrate having a high thermal expansion coefficient is cooled or heated at low temperature to form a bonding temperature such as eutectic bonding, welding, brazing, soldering, or the like.

The submount substrate bonding apparatus of this invention is comprised from the 1st heating part which heats the board | substrate with a small thermal expansion coefficient at high temperature, and the 2nd cooling part or heating part which cools or low temperature heats the board | substrate with a large thermal expansion coefficient.

Description

Submount Bonding Method and Apparatus {Submount Bonding Method and the Apparatus}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for bonding a substrate to a submount during the manufacturing process of a vertical light emitting diode device having excellent luminous efficiency and heat dissipation efficiency. The present invention relates to a difference in coefficient of thermal expansion during cooling by varying a heating temperature of a substrate and a submount. To prevent warpage.

A light emitting diode (LED) device is a semiconductor device that generates light by flowing a current in a forward direction to a PN junction. Light emitting diode devices using semiconductors have high efficiency for converting electrical energy into light energy, have a long lifespan of more than 5 to 10 years, and can greatly reduce power consumption and maintenance costs. Is getting.

More specifically, a light emitting diode using a gallium nitride compound semiconductor will be described as an example.

A sapphire substrate is mainly used for growing a gallium nitride compound semiconductor for manufacturing a light emitting diode. Since the sapphire substrate is an insulator, the anode and cathode electrodes of the light emitting diode are formed on the front surface of the wafer.

In general, a top-emitting gallium nitride-based light emitting diode is mainly used for low power, and after raising the sapphire substrate 10 having the crystal structure grown on the lead frame 20 as shown in FIG. 12) is produced by connecting to the top. In this case, in order to improve heat dissipation efficiency, the sapphire substrate is thinned to a thickness of about 100 micrometers or less and attached to the lead frame. However, since the thermal conductivity of the sapphire substrate is about 50 W / mK, even if the thickness is about 100 micrometers, the thermal resistance is very large, so that even if the structure of FIG.

Accordingly, in the case of a high output gallium nitride-based light emitting diode, a flip chip bonding method is mainly used as shown in FIG. In the flip chip bonding method, a chip having a light emitting diode structure is attached to a submount 30 such as a silicon wafer (about 150 W / mK) or an AlN ceramic (about 180 W / mK) substrate having excellent thermal conductivity. In FIG. 1B, reference numeral 10 denotes a sapphire substrate, 11 and 12 electrodes, 13 a light emitting layer, 30 a submount, and 40 a flip chip bonding metal. In this case, since the heat is released through the submount, the heat dissipation efficiency is improved compared with the heat dissipation through the sapphire substrate, but the degree of improvement is not satisfactory.

Recently, a gallium nitride based light emitting diode (GaN LED) method in which a sapphire substrate has been removed has been attracting attention. The method of fabricating a light emitting diode by removing a sapphire substrate is a typical technique of removing a sapphire substrate from a light emitting diode crystal structure by a laser lift-off method and packaging it, and is known to have the best heat dissipation efficiency.

In addition, unlike the flip chip bonding method, the sapphire substrate removal method does not require an elaborate flip chip bonding process, and the manufacturing process is simple as long as the problem related to the removal of the sapphire substrate is solved. In the case of flip chip bonding, the light emitting area is about 60% of the chip area, whereas in the light emitting diode structure in which the sapphire substrate is removed, the light emitting area is about 90% of the chip size.

2 shows a manufacturing process diagram of a thin film gallium nitride based light emitting diode device having a unit chip shape according to a conventional sapphire substrate removal method, specifically, growing a gallium nitride based light emitting diode crystal structure on a sapphire substrate; Mounting a sapphire substrate on which the crystal structure is grown on a submount; Removing the sapphire substrate from the resultant; The resultant is separated into unit chips; The light emitting diode device is manufactured by mounting the formed unit chip on a lead frame.

Hereinafter, the process of bonding the sapphire substrate on the submount substrate will be described in detail.

The submount substrate may use a conductive material or a nonconductive material generally used in the art. In general, high output light emitting diodes use sub-mount substrates such as various metal or inorganic wafers for heat dissipation to improve heat dissipation efficiency. Specifically, metals such as CuW, Al and Cu, Si wafers, AlN Inorganic materials such as ceramics and Al 2 O 3 ceramics can be used.

The size of the submount substrate is more than 1 inch, the size has an advantage of excellent productivity, but the larger the size is required to prevent cracking or bending during handling, the thickness must be increased, in this case, it is disadvantageous for heat dissipation. In consideration of heat dissipation characteristics and mass productivity, it is preferable to select a submount substrate having a wafer size of about 1 to 6 inches in diameter.

The material that can be used for bonding with the submount substrate preferably supplies current to the light emitting diodes through it and easily dissipates the heat generated by the light emitting diodes. Specifically, a low melting point AuSn, AgSn, PbSn, Sn, Ag powder and silver paste (silver paste) or metal bonded at a low temperature of less than 300 ℃, such as In and Pd may be used.

Eutectic bonding is preferred as the bonding method, but other bonding methods such as welding, brazing, and soldering are also possible.

For example, a wafer or module having a polished sapphire substrate is placed upside down on the submount substrate so that the sapphire substrate is placed upside down, and the p-type ohmic contact metal surface of the light emitting diode is attached to the submount substrate by using a thermally adhesive metallic bonding material. Can be bonded.

When attaching two or more modules to a single submount substrate, periodic intervals of several hundred micrometers should be provided between the modules and the modules, taking into account the subsequent dicing process and wire bonding of the submount substrate. It is preferable to arrange as. In addition, when the sapphire substrate is subsequently removed with a laser, it is preferable to adjust the distance between modules so that the unit chip does not hang on the edge of the area where the laser light is irradiated.

3 shows a conventional submount substrate bonding apparatus. The press 50 which applies a constant pressure to the whole sample, and the heater 60 for maintaining the temperature required for joining are comprised, The joining sample 70 is located between heaters. This configuration is not suitable for welding in which the base metal must be melted.

4 shows a configuration of the bonding sample 70. The substrate 10 on which the light emitting diode structure is formed is turned over and pasted onto the submount 30.

In the case where the substrate 10 is sapphire and the submount 30 is conductive silicon, an AuSn eutectic bonding layer is formed at the junction and the eutectic is maintained at a temperature of about 300 ° C. for about 30 minutes using the apparatus of FIG. 3. The junction is formed.

The thermal expansion coefficient of the sapphire substrate is about 8 × 10 −6 / K, and the thermal expansion coefficient of the silicon substrate is about 2.5 × 10 −6 / K. The sample is slowly cooled by bonding at about 300˚C. When it reaches room temperature, the stress due to the difference in thermal expansion coefficient between sapphire and silicon substrate increases. Fig. 5 shows the sapphire substrate side in a concave shape.

As described above, the sample having a 휜 shape is difficult to process later. Therefore, there is an urgent need for the development of a bonding method and apparatus for maintaining flatness even after bonding.

In the submount substrate bonding method of the present invention, a substrate having a low thermal expansion coefficient is heated at a high temperature and a substrate having a high thermal expansion coefficient is cooled or heated at low temperature to form a bonding temperature such as eutectic bonding, welding, brazing, soldering, or the like.

The submount substrate bonding apparatus of this invention is comprised from the 1st heating part which heats the board | substrate with a small thermal expansion coefficient at high temperature, and the 2nd cooling part or heating part which cools or low temperature heats the board | substrate with a large thermal expansion coefficient.

When the submount substrate bonding method or the bonding apparatus according to the present invention is used, the sample does not bend even after bonding, and thus the process proceeds smoothly. That is, using the submount substrate bonding method or the bonding apparatus according to the present invention, it is possible to mass-produce a vertical light emitting diode device having excellent luminous efficiency and heat dissipation efficiency.

Specifically, if the junction temperature of the junction site is required about 220 ℃, the first heating unit is heated to about 335 ℃ and the second cooling unit is cooled to maintain about 105 ℃, the thermal expansion at high temperature in the process of cooling to room temperature after bonding Since the substrate having a small coefficient shrinks in a large temperature range and the substrate having a low thermal expansion coefficient in a low temperature range shrinks in a small temperature range, the degree of shrinkage is similar, so that the stress due to the difference in the coefficient of thermal expansion is significantly reduced and the sample is not bent.

In the submount substrate bonding method of the present invention, a substrate having a low thermal expansion coefficient is heated at a high temperature and a substrate having a high thermal expansion coefficient is cooled or heated at low temperature to form a bonding temperature such as eutectic bonding, welding, brazing, soldering, or the like.

As an embodiment of the present invention, a substrate in which a light emitting diode structure is formed is a sapphire substrate, a submount substrate is conductive silicon, and a bonding method is soldering using solder balls.

The thermal expansion coefficient of the sapphire substrate is about 8 × 10 −6 / K, and the thermal expansion coefficient of the silicon substrate is about 2.5 × 10 −6 / K. The sapphire substrate is about 3.2 times. (This value varies depending on the temperature, so it is necessary to select the proper temperature through rough calculation and then adjust it by experiment.) Therefore, the stress due to the difference in thermal expansion coefficient at room temperature after bonding To avoid this, the silicon substrate must be processed at about 3.2 times the temperature of the sapphire substrate. (For convenience, calculate 0 ° C at room temperature.)

For example, when a substrate having a small thermal expansion coefficient is heated to about 335 ° C. and a substrate having a large thermal expansion coefficient is maintained at about 105 ° C., the stress after bonding is significantly reduced. Of course, this value cannot be an exact value because there is a temperature distribution depending on the thickness of the sapphire substrate or the silicon substrate itself.

Since the thermal conductivity of silicon substrate is about 3 times higher than that of sapphire substrate, when the same thickness of substrate is used, the intermediate temperature (approximately 335˚C and about 105˚C) of both substrates at the interface of both substrates is about 220˚. A higher temperature is formed than C). If you use a solder ball with a melting point of about 220˚C, this is enough temperature.

If the temperature of the junction is lower than the melting point, increase the temperature of the hot zone and recalculate. If the temperature of the junction is too high, lower the temperature of the hot zone and recalculate. Of course, precise adjustments are possible through experimentation.

Although the case where the ratio of the temperature of the hot part to the temperature of the cold part is the same as the ratio of the large coefficient of thermal expansion and the small coefficient of thermal expansion, the temperature ratio of the temperature of the hot part and the temperature of the cold part is proportional to the ratio of the large coefficient of thermal expansion and the small coefficient of thermal expansion, It may be sufficient to set the temperature of the hot zone to try first. Preferably the proportional coefficient is between 0.1 and 10.

The heating of the high temperature part may be performed by a hot plate or the like. When the temperature of the low temperature part due to natural convection is higher than the desired temperature, cooling using a heat sink 80 or a fan is required as shown in FIG. 6, and the low temperature part due to natural convection is required. If the temperature is lower than the desired temperature, heating using a hot air fan or the like is necessary.

It is desirable to apply a constant pressure to improve the bond strength and reduce the bond thickness. In the case of soldering, the effect can be obtained even at a small pressure of several g / cm 2 , but in the case of eutectic bonding, a large pressure of several kg / cm 2 is required.

If possible, it is preferable to use a natural cooling method using a heat sink. This is because not only the maintenance of the junction temperature condition is easy but also the process pressure may be sufficient by the heat sink alone.

In the exemplary embodiment of the present invention, a substrate, a submount substrate, a bonding method, and the like, in which the light emitting diode structure is formed are exemplary, and the technical idea of the present invention is not limited thereto.

In addition, the technical idea of the present invention is not limited to the material used as the bonding layer, it is possible to apply the present invention even if another layer is inserted between the light emitting diode layer and the bonding layer.

The submount substrate bonding apparatus of this invention is comprised from the 1st heating part which heats the board | substrate with a small thermal expansion coefficient at high temperature, and the 2nd cooling part or heating part which cools or low temperature heats the board | substrate with a large thermal expansion coefficient.

In some cases, the first heating unit may be made of a hot plate, the second cooling unit may be made of a heat sink, a fan, or the like, the first heating unit may be made of a hot plate, or the like, and the second heating unit may be made of a hot air heater.

It is desirable to add means to apply a constant pressure to improve the bond strength and reduce the bond thickness. In the case of soldering, the effect can be obtained even at a small pressure of several g / cm 2 , but in the case of eutectic bonding, a large pressure of several kg / cm 2 is required.

If possible, it is preferable to configure a natural cooling method using a heat sink. This is because not only the maintenance of the junction temperature condition is easy but also the process pressure may be sufficient by the heat sink alone.

In order to use the submount substrate bonding method and apparatus according to the present invention, the LED chips must be patterned with an insulating film. This is because when the conductive bonding material comes into contact with the light emitting diode structure, an unwanted leakage current is generated.

Figure 1 shows the structure of a gallium nitride-based light emitting diode, (a) is a top emission type, (b) a flip chip type.

2 illustrates a process of manufacturing a gallium nitride-based light emitting diode device in a unit chip form according to a conventional sapphire substrate removal method.

3 shows a conventional submount substrate bonding apparatus.

4 shows a configuration of the bonding sample 70.

Fig. 5 shows the sapphire substrate side in a concave shape.

6 shows a submount substrate bonding apparatus according to the present invention.

Description of the main parts of the drawing

10: sapphire substrate

11: cathode 12: anode 13: light emitting layer

20: leadframe

30: submount

40: flip chip bonding metal

50: press

60: heater

70: junction sample

80: heat sink

Claims (10)

Substrate bonding method in which the substrate with small thermal expansion coefficient is heated at high temperature and the substrate with large thermal expansion coefficient is formed by cooling or low temperature heating. 2. A substrate bonding method according to claim 1, wherein the ratio of the temperature of the high temperature portion to the temperature of the low temperature portion is proportional to the ratio of the large coefficient of thermal expansion and the small coefficient of thermal expansion. 3. A substrate bonding method according to claim 2, wherein the ratio of the temperature of the high temperature portion to the temperature of the low temperature portion is such that the ratio of the large coefficient of thermal expansion to the small coefficient of thermal expansion. The substrate joining method according to any one of claims 1 to 3, wherein the step of applying a constant pressure is performed in parallel. The substrate joining method according to any one of claims 1 to 3, wherein the substrate having a large coefficient of thermal expansion is cooled by using a heat sink. The method of claim 5, wherein the process pressure is maintained at a heat sink weight. The substrate according to any one of claims 1 to 3, wherein the substrate having a low coefficient of thermal expansion is a conductive silicon submount, the substrate having a high coefficient of thermal expansion is a sapphire substrate having a light emitting diode structure, and a bonding method using solder balls. Solder-in Board Bonding Method Substrate bonding apparatus which consists of the 1st heating part which heats the board | substrate with a low thermal expansion coefficient at high temperature, and the 2nd cooling part or heating part which cools or low temperature heats the board | substrate with a large thermal expansion coefficient. 9. A substrate bonding apparatus according to claim 8, comprising means for applying a constant pressure. The substrate bonding apparatus of claim 8, wherein the second cooling unit is configured of a heat sink.
KR1020090043297A 2009-05-18 2009-05-18 Submount Bonding Method and the Apparatus KR101589897B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018157231A (en) * 2017-02-10 2018-10-04 ルーメンス カンパニー リミテッド Flip-chip bonding method of micro led module and flip-chip bonding module
EP3561870A4 (en) * 2016-12-23 2020-11-25 Lumens Co., Ltd. Micro led module and manufacturing method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307870A (en) * 1998-04-22 1999-11-05 Sony Corp Semiconductor device and its manufacture
JP2005129584A (en) * 2003-10-21 2005-05-19 Sony Corp Semiconductor laser device, packaging method and packaging equipment of semiconductor laser element
US20060154443A1 (en) * 2005-01-07 2006-07-13 Horning Robert D Bonding system having stress control

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11307870A (en) * 1998-04-22 1999-11-05 Sony Corp Semiconductor device and its manufacture
JP2005129584A (en) * 2003-10-21 2005-05-19 Sony Corp Semiconductor laser device, packaging method and packaging equipment of semiconductor laser element
US20060154443A1 (en) * 2005-01-07 2006-07-13 Horning Robert D Bonding system having stress control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3561870A4 (en) * 2016-12-23 2020-11-25 Lumens Co., Ltd. Micro led module and manufacturing method therefor
JP2018157231A (en) * 2017-02-10 2018-10-04 ルーメンス カンパニー リミテッド Flip-chip bonding method of micro led module and flip-chip bonding module

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