KR20100120869A - Chip stacked package and method for manufacturing of it - Google Patents

Chip stacked package and method for manufacturing of it Download PDF

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KR20100120869A
KR20100120869A KR1020090039722A KR20090039722A KR20100120869A KR 20100120869 A KR20100120869 A KR 20100120869A KR 1020090039722 A KR1020090039722 A KR 1020090039722A KR 20090039722 A KR20090039722 A KR 20090039722A KR 20100120869 A KR20100120869 A KR 20100120869A
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chip
bumps
insulating layer
cavity
solder
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KR101002041B1 (en
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이동희
진정기
김동인
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Abstract

PURPOSE: A chip laminated type package and a manufacturing method thereof are provided to stably maintain the lamination balance between chips by maintaining the interval and height of a bump. CONSTITUTION: A conductive bump(14a) is attached to an electrode pad formed in the bottom surface of an upper chip. An upper insulation layer(13a) is spread through the bottom surface of the upper chip(10a). A lower insulation layer(13b) is spread through the upper side of a lower chip. A cavity(12) exposes the electrode pad formed in the upper side of the lower chip. A solder(14b) is filled within the cavity.

Description

칩 적층형 패키지 및 그 제조방법{Chip stacked package and method for manufacturing of it}Chip stacked package and method for manufacturing of it

본 발명은 칩 적층형 패키지 및 그 제조방법에 관한 것으로서, 더욱 상세하게는 기판 상에 복수의 적층 칩이 범프로 통전되는 칩 적층형 패키지 및 그 제조방법에 관한 것이다.The present invention relates to a chip stacked package and a method of manufacturing the same, and more particularly, to a chip stacked package in which a plurality of stacked chips are supplied with a bump on a substrate and a method of manufacturing the same.

반도체 패키지의 크기를 줄이면서도 고집적화를 가능하게 하는 방안으로 복수개의 칩을 적층시킨 적층 칩 패키지가 제조되고 있다.In order to reduce the size of the semiconductor package and enable high integration, a multilayer chip package in which a plurality of chips are stacked is manufactured.

또한, 반도체 칩의 고집적화, 고성능화를 위하여 칩간의 전기적 신호교환수단으로 전도성 와이어를 사용하지 않고, 반도체 칩의 패드들 상에 형성된 솔더 재질이나 금속 재질의 범프를 이용하여 직접적으로 반도체 칩 간의 패드들 또는 칩과 인쇄회로기판의 전극 단자들을 전기적으로 연결시키는 반도체 패키지가 제조되었다.In addition, for high integration and high performance of semiconductor chips, pads between semiconductor chips may be directly formed using solder or metal bumps formed on the pads of the semiconductor chip without using conductive wires as an electrical signal exchange means between the chips. A semiconductor package has been manufactured that electrically connects the electrode terminals of a chip and a printed circuit board.

솔더 범프를 이용한 반도체 패키지는 대표적으로 플립칩 볼 그리드 어레 이(FCBGA: flip chip ball grid array)나 웨이퍼 레벨 칩 스케일(wafer level chip scale package: WLCSP) 패키지 등을 예로 들 수 있다. Typical semiconductor packages using solder bumps include flip chip ball grid array (FCBGA) and wafer level chip scale package (WLCSP).

상기 플립칩 볼 그리드 어레이 방식은 반도체 칩의 패드들과 접촉되는 솔더 범프들을 기판의 패드들과 전기적으로 연결하고, 솔더 범프들을 외부의 환경이나 기계적인 문제로부터 보호하기 위해 언더필(underfill)을 실시한 다음, 상기 반도체 칩이 접촉된 기판의 배면에 솔더 볼들을 부착하여 인쇄회로기판의 전극 단자들과 전기적으로 연결함으로써, 반도체 패키지를 완성한다. The flip chip ball grid array method electrically connects the solder bumps in contact with the pads of the semiconductor chip with the pads of the substrate and underfills to protect the solder bumps from external environmental or mechanical problems. The semiconductor package is completed by attaching solder balls to the rear surface of the substrate to which the semiconductor chip is in contact and electrically connecting the electrode terminals of the printed circuit board.

상기 웨이퍼 레벨 칩 스케일 패키지는 제품의 경박 단소를 위해 전극 패드의 간격을 축소시키고 금속 범프를 통해서 칩과 동일한 크기로 제조된 것을 말한다.The wafer level chip scale package is made of the same size as the chip through the metal bumps and the spacing of the electrode pads for light and thin short of the product.

이와 같은 칩 적층형 반도체 패키지 기술에 있어서, 칩간의 전기적 신호교환수단인 범프의 구조는 반도체 패키지의 경박 단소화 및 미세 피치를 구현함에 있어서 매우 중요하다. In such a chip stacked semiconductor package technology, the bump structure, which is an electrical signal exchange means between chips, is very important in realizing a thin and short and small pitch of the semiconductor package.

여기서, 도 3을 참조로 종래의 칩 적층형 플립칩 패키지의 구조를 살펴보면, 상부칩(10a) 하면의 전극 패드(11a)에 부착되는 범프(14a)가 하부칩(10b)의 전극 패드와 전기적으로 접속된다. 이때, 언더필용 수지(1)가 상기 상부칩(10a)과 하부칩(10b) 사이에 충진되어 외부 환경으로부터 범프를 보호한다.Here, referring to FIG. 3, the structure of a conventional chip stack flip chip package includes a bump 14a attached to an electrode pad 11a on a lower surface of the upper chip 10a and an electrode pad of the lower chip 10b. Connected. At this time, the underfill resin 1 is filled between the upper chip 10a and the lower chip 10b to protect the bumps from the external environment.

그러나, 상기 상부칩과 하부칩이 전기적으로 접속될 때 원형의 범프가 국부적인 융착에 의해 납작하게 변형되어, 인접하는 범프 간의 브릿지(bridge)로 인한 쇼트현상이 발생되거나, 범프 구조물 내지 패키지 구조의 오염과 손상이 발생하여 제조 수율(yield)을 감소시킬 뿐만 아니라, 반도체 장치의 기능을 저하시키는 문제 가 발생하고 있다.However, when the upper chip and the lower chip are electrically connected, the circular bumps are flatly deformed by local fusion, resulting in a short phenomenon due to a bridge between adjacent bumps, or the bump structure or the package structure. Contamination and damage occur to reduce production yields, as well as to reduce the function of semiconductor devices.

즉, 범프(14a)의 원치않는 변형(수평적 퍼짐에 의하여 납작하게 됨)은 주변의 범프(14a)와 연결되어 전기적인 쇼트불량을 야기하여, 이로 인해 반도체 장치의 동작 특성을 저해하는 문제점이 있다.That is, unwanted deformation of the bump 14a (flattened by horizontal spreading) is connected to the surrounding bump 14a and causes an electrical short failure, thereby degrading the operating characteristics of the semiconductor device. .

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 상부칩의 범프가 하부칩에 형성된 캐비티로 들어가 하부절연층의 솔더와 통전가능하게 결합됨으로써, 상부칩과 하부칩이 전기적으로 용이하게 접속될 뿐만 아니라, 상부칩과 하부칩에 도포된 상부절연층 및 하부절연층이 언더필 역할을 수행함에 따라 서로 인접한 범프가 독립적인 공간에 위치된 상태가 되므로, 종래에 범프 간의 연결(bridging)에 의한 쇼트 현상을 방지할 수 있는 칩 적층형 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.The present invention has been made in view of the above, and the bump of the upper chip enters the cavity formed in the lower chip to be electrically coupled with the solder of the lower insulating layer, so that the upper chip and the lower chip can be electrically connected easily. In addition, as the upper insulating layer and the lower insulating layer applied to the upper chip and the lower chip perform the underfill role, bumps adjacent to each other are positioned in independent spaces, and thus, shorts due to bridging between bumps have been conventionally used. It is an object of the present invention to provide a chip stack package and a method of manufacturing the same that can prevent the phenomenon.

상기한 목적은 상부칩과 하부칩이 전기적 신호 교환 가능하게 상호 적층되는 칩 적층형 패키지에 있어서,The above object is in a chip stacked package in which the upper chip and the lower chip are laminated to each other to exchange electrical signals,

상기 상부칩의 저면에 형성된 전극패드에 부착되는 전도성 범프; 상기 범프가 노출되게 상부칩의 저면에 걸쳐 도포된 상부절연층; 상기 하부칩의 상면에 걸쳐 도포되는 하부절연층; 상기 하부칩의 상면에 형성된 전극패드를 노출시키면서 상기 하부절연층에 형성된 캐비티; 및 상기 하부칩의 전극패드에 닿으면서 캐비티 내에 충진되는 솔더;를 포함하여 구성되고, 상기 상부칩에 부착된 전도성 범프가 상기 캐비티 내로 삽입되어 솔더와 통전 가능하게 융착되도록 한 것을 특징으로 하는 칩 적층형 패키지에 의해 달성된다.A conductive bump attached to an electrode pad formed on a bottom surface of the upper chip; An upper insulating layer applied over the bottom surface of the upper chip to expose the bumps; A lower insulating layer applied over the upper surface of the lower chip; A cavity formed in the lower insulating layer while exposing an electrode pad formed on an upper surface of the lower chip; And a solder filled in the cavity while contacting the electrode pad of the lower chip, wherein the conductive bumps attached to the upper chip are inserted into the cavity to be fused to the solder so as to conduct electricity. Achieved by the package.

한편, 본 발명의 다른 측면은 상부칩과 하부칩이 전기적 신호 교환 가능하게 상호 적층되는 칩 적층형 패키지의 제조방법에 있어서,Meanwhile, another aspect of the present invention provides a method of manufacturing a chip stacked package in which an upper chip and a lower chip are laminated to each other to exchange electrical signals.

상부칩의 저면에 형성된 전극패드에 전도성 범프를 부착하는 단계; 상기 범프를 포함하도록 상부칩의 저면에 걸쳐 상부절연층을 도포하는 단계; 상기 범프에 도포된 상부절연층을 제거하여 범프를 노출시키는 단계; 상기 하부칩의 상면에 걸쳐 하부절연층을 도포하는 단계; 상기 하부절연층의 상면에서 상기 범프와 대응되는 위치를 노광시켜 캐비티를 형성하는 단계; 상기 캐비티 내에 소량의 솔더를 하부칩의 전극패드와 통전되도록 채우는 단계; 및 상기 범프가 캐비티 내의 솔더와 결합되도록 상기 상부칩과 하부칩을 리플로우 장치에 넣은 후 가열하여 접합하는 단계;를 포함하는 것을 특징으로 하는 칩 적층형 패키지의 제조방법에 의해 달성된다.Attaching a conductive bump to an electrode pad formed on a bottom surface of an upper chip; Applying an upper insulating layer over the bottom surface of the upper chip to include the bumps; Exposing the bumps by removing the upper insulating layer applied to the bumps; Applying a lower insulating layer over the upper surface of the lower chip; Exposing a position corresponding to the bump on an upper surface of the lower insulating layer to form a cavity; Filling a small amount of solder into the cavity so as to be energized with an electrode pad of a lower chip; And inserting the upper chip and the lower chip into a reflow device so that the bumps are combined with the solder in the cavity, and then heating and bonding the bumps to the bumps.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above problem solving means, the present invention provides the following effects.

본 발명에 따른 칩 적층형 패키지 및 그 제조방법에 의하면, 상부칩의 범프가 하부칩에 형성된 캐비티로 들어가 하부절연층의 솔더와 통전가능하게 결합됨으로써, 상부칩과 하부칩이 전기적으로 용이하게 접속될 뿐만 아니라, 범프의 간격 및 높이가 균일하게 유지되어 칩 간의 적층 밸런스를 안정적으로 유지시킬 수 있다.According to the chip stack package and a method of manufacturing the same according to the present invention, the bumps of the upper chip enter the cavity formed in the lower chip so as to be electrically coupled with the solder of the lower insulating layer, so that the upper chip and the lower chip can be easily connected. In addition, the spacing and height of the bumps may be maintained uniformly, thereby stably maintaining the stacking balance between the chips.

특히, 상기 상부칩과 하부칩에 도포된 상부절연층 및 하부절연층이 언더필 역할을 수행함에 따라 서로 인접한 범프는 독립적인 공간에 위치된 상태가 되므로, 종래에 범프 간의 연결(bridging)에 의한 쇼트 현상을 방지할 수 있다.In particular, as the upper insulating layer and the lower insulating layer applied to the upper chip and the lower chip serve as an underfill role, bumps adjacent to each other are positioned in independent spaces, and thus, shorts due to bridging between bumps are conventionally used. The phenomenon can be prevented.

또한, 기존의 언더필 공정을 제거하여 제조공정이 단순해짐에 따라 제조비용을 절감할 수 있다.In addition, as the manufacturing process is simplified by removing the existing underfill process, the manufacturing cost may be reduced.

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

첨부한 도 1은 본 발명의 일실시예에 따른 칩 적층형 패키지를 나타내는 단면도이다.1 is a cross-sectional view illustrating a chip stacked package according to an exemplary embodiment of the present invention.

본 발명은 두개 이상의 칩(10a,10b)이 범프(14a)를 통해 통전 및 적층되는 칩 적층형 패키지에 관한 것으로서, 특히 언더필이 필요없으면서 범프(14a) 간의 브릿징 문제를 해결할 수 있는 칩 적층형 패키지에 관한 것이다.The present invention relates to a chip stack package in which two or more chips 10a and 10b are energized and stacked through the bumps 14a. In particular, the present invention relates to a chip stack package that can solve a bridging problem between bumps 14a without underfilling. It is about.

본 발명의 일실시예에 따른 칩 적층형 패키지는 상부칩(10a), 하부칩(10b)을 포함한다. The chip stack package according to an embodiment of the present invention includes an upper chip 10a and a lower chip 10b.

상기 상부칩(10a)과 하부칩(10b)은 복수의 칩을 예시한 것으로서, 그 이상의 칩이 적층될 수 있다.The upper chip 10a and the lower chip 10b are examples of a plurality of chips, and more chips may be stacked.

상기 상부칩(10a)의 상면에는 전극패드(11a)가 형성되고, 이 전극패드(11a) 사이에는 유전체가 도포되어, 이 유전체에 의해 전극패드(11a)가 서로 절연된다. 상기 전극패드(11a)에는 상부칩(10a)을 하부칩(10b)에 전기적으로 접속하기 위해 전도성 범프(14a)를 부착한다. 이때, 범프(14a)로 구 형태의 볼이 사용된다.An electrode pad 11a is formed on the upper surface of the upper chip 10a, and a dielectric is coated between the electrode pads 11a, so that the electrode pads 11a are insulated from each other by the dielectric. A conductive bump 14a is attached to the electrode pad 11a to electrically connect the upper chip 10a to the lower chip 10b. At this time, a spherical ball is used as the bump 14a.

상기 상부칩(10a)에는 범프(14a)가 절반 정도 드러날 정도로 상부절연층(13a)이 도포된다. 상기 상부절연층(13a)은 BCB(BenzoCycloButene) 재질을 사용하고, 범프(14a)를 외부환경으로부터 보호하는 언더필의 역할을 수행할 뿐만 아니라, 인접한 범프(14a) 간의 연결을 완전히 차단 및 분리시키는 역할을 한다. The upper insulating layer 13a is coated on the upper chip 10a so that the bump 14a is exposed to about half. The upper insulating layer 13a uses BCB (BenzoCycloButene) material, serves as an underfill to protect the bump 14a from the external environment, and also completely blocks and isolates the connection between adjacent bumps 14a. Do it.

상기 하부칩(10b)의 상면에도 전극 패드(11b)와 유전체가 형성되고, 하부절연층(13b)이 도포된다. 이때, 하부절연층(13b)도 BCB 재질을 사용한다. 상기 하부절연층(13b)에는 상부칩(10a)의 범프(14a) 위치와 대응되게 캐비티(12)가 형성된다. 이때, 상기 상부 및 하부절연층(13a,13b)의 용융온도는 범프(14a) 및 솔더(14b)의 용융온도보다 높다.The electrode pad 11b and the dielectric are formed on the upper surface of the lower chip 10b, and the lower insulating layer 13b is coated. At this time, the lower insulating layer 13b also uses a BCB material. A cavity 12 is formed in the lower insulating layer 13b to correspond to the position of the bump 14a of the upper chip 10a. In this case, melting temperatures of the upper and lower insulating layers 13a and 13b are higher than melting temperatures of the bumps 14a and the solder 14b.

상기 캐비티(12) 내부에는 소량의 솔더(14b)가 하부칩(10b)의 전극패드(11b)와 접촉되도록 채워지고, 캐비티(12)는 상부칩(10a)과 하부칩(10b)의 접합시 상부칩(10a)의 범프(14a)를 일부 수용한다. 이때, 캐비티(12)는 상부칩(10a)의 범프(14a)와 하부칩(10b)의 솔더(14b)가 열에 의해 결합되는 공간이다. 그리고, 열에 의해 상부칩(10a)과 하부칩(10b)의 접합시 범프(14a)가 용융되어 솔더(14b)에 융착되고, 상부절연층(13a)과 하부절연층(13b)이 캐비티(12)를 밀봉한다.A small amount of solder 14b is filled in the cavity 12 so as to contact the electrode pad 11b of the lower chip 10b, and the cavity 12 is bonded to the upper chip 10a and the lower chip 10b. A part of the bump 14a of the upper chip 10a is accommodated. In this case, the cavity 12 is a space in which the bump 14a of the upper chip 10a and the solder 14b of the lower chip 10b are joined by heat. When the upper chip 10a and the lower chip 10b are joined together by heat, the bump 14a is melted and fused to the solder 14b, and the upper insulating layer 13a and the lower insulating layer 13b are formed in the cavity 12. Seal.

따라서, 상기 상부칩(10a)의 범프(14a)가 용융되어 하부칩(10b)의 캐비티(12) 내로 들어가 소량의 솔더(14b)에 융착됨으로써, 상부칩(10a)과 하부칩(10b)이 전기적으로 통전되어 전기적 신호를 교환할 수 있을 뿐만 아니라, 상부칩(10a)과 하부칩(10b)의 접합시 캐비티(12) 내에서 융착된 범프(14a)와 솔더(14b)의 용융물(14)이 상부 및 하부절연층(13a,13b)에 의해 차단되어 인접한 캐비티(12)로 이동 하지 못하므로 범프(14a) 간의 브릿징 문제를 해결할 수 있다.Accordingly, the bump 14a of the upper chip 10a is melted and fused into the cavity 12 of the lower chip 10b to be fused to a small amount of solder 14b, thereby forming the upper chip 10a and the lower chip 10b. In addition to being electrically energized to exchange electrical signals, the melt 14 of the bump 14a and the solder 14b fused in the cavity 12 when the upper chip 10a and the lower chip 10b are bonded to each other. Since it is blocked by the upper and lower insulating layers 13a and 13b and cannot move to the adjacent cavity 12, bridging problems between the bumps 14a can be solved.

이하, 본 발명의 일실시예에 따른 칩 적층형 패키지의 제조방법을 설명하면 다음과 같다. 도 2는 본 발명의 일실시예에 따른 칩 적층형 패키지의 제조방법을 나타내는 공정도이다.Hereinafter, a method of manufacturing a chip stacked package according to an embodiment of the present invention will be described. 2 is a process chart showing a method of manufacturing a chip stacked package according to an embodiment of the present invention.

먼저, 상부칩(10a)을 제작한다. 상부칩(10a)에 전극패드(11a)를 형성하고, 상기 전극패드(11a) 사이에 유전체층을 형성한 후, 전극패드(11a)에 구 형태의 전도성 범프(14a)를 부착한다(도 2a 참조).First, the upper chip 10a is manufactured. An electrode pad 11a is formed on the upper chip 10a, a dielectric layer is formed between the electrode pads 11a, and a spherical conductive bump 14a is attached to the electrode pad 11a (see FIG. 2a). ).

그 다음, 상기 상부칩(10a) 위에 일정한 두께(범프(14a)가 절반정도 드러날 정도)로 언더필용 BCB 재질의 상부절연층(13a)을 스핀 코팅 공정에 의해 도포한다(도 2b 참조). 계속해서, 상기 범프(14a) 위에 코팅된 상부절연층(13a)을 플라즈마 에칭 공정에 의해 제거한다(도 2c 참조).Next, an upper insulating layer 13a of an underfill BCB material is applied by a spin coating process to a predetermined thickness (about half of the bump 14a is exposed) on the upper chip 10a (see FIG. 2B). Subsequently, the upper insulating layer 13a coated on the bump 14a is removed by a plasma etching process (see FIG. 2C).

다음으로 하부칩(10b)을 제작한다.Next, the lower chip 10b is manufactured.

상기 하부칩(10b)의 상면에 전극패드(11b)와 유전체를 형성한다. 그 다음, 하부칩(10b)의 전극패드(11b)와 유전체 위에 일정한 두께로 언더필용 BCB 재질의 하부절연층(13b)을 스핀 코팅 공정에 의해 도포한다(도 2d 참조). An electrode pad 11b and a dielectric are formed on an upper surface of the lower chip 10b. Subsequently, a lower insulating layer 13b of BCB material for underfill is applied to the electrode pad 11b of the lower chip 10b and the dielectric material by a spin coating process (see FIG. 2D).

계속해서 상기 하부절연층(13b)에 범프(14a)의 위치와 대응되게 캐비티(12)를 형성한다. 이때, 상기 캐비티(12)는 포토레지스트를 이용하여 노광에 의해 형성된다(도 2e 참조). 그리고, 상기 캐비티(12)에 소량의 솔더(14b)를 전극패드와 통전되도록 채운다(도 2f 참조). 이때, 솔더(14b)는 상기 상부칩(10a)의 범프(14a)와 동일한 재질로 이루어진다.Subsequently, a cavity 12 is formed in the lower insulating layer 13b to correspond to the position of the bump 14a. At this time, the cavity 12 is formed by exposure using a photoresist (see FIG. 2E). Then, a small amount of solder 14b is filled into the cavity 12 so as to be energized with the electrode pad (see FIG. 2F). At this time, the solder 14b is made of the same material as the bump 14a of the upper chip 10a.

그 다음, 상부칩(10a)의 범프(14a)가 캐비티(12)에 삽입되어 소량의 솔더(14b)와 결합되도록 상부칩(10a)을 하부칩(10b) 위에 올려 놓은 후(도 2g 참조), 상부칩(10a)과 하부칩(10b)의 전기적 접속을 위하여 상부칩(10a)과 하부칩(10b)을 리플로우 장비에 넣어 열을 가한다. 이때, 리플로우 장비에서의 가열 온도는 상기 범프(14a) 및 솔더(14b)의 용융온도보다 높고 절연층(13a,13b)의 용융온도보다 작다.Then, after placing the upper chip 10a on the lower chip 10b so that the bump 14a of the upper chip 10a is inserted into the cavity 12 and combined with a small amount of solder 14b (see FIG. 2G). In order to electrically connect the upper chip 10a and the lower chip 10b, the upper chip 10a and the lower chip 10b are put in a reflow apparatus and heated. At this time, the heating temperature in the reflow equipment is higher than the melting temperature of the bumps 14a and the solder 14b and smaller than the melting temperatures of the insulating layers 13a and 13b.

상기 상부칩(10a)과 하부칩(10b)은 리플로우 장비에서 발생된 열을 받아 범프(14a)가 녹으면서 캐비티(12) 안으로 흘러 들어가 소량의 솔더(14b)와 결합된다. 이때, 상기 상부절연층(13a)과 하부절연층(13b)은 상부칩(10a)과 하부칩(10b)의 접합시 캐비티(12)를 밀봉하여 인접한 범프(14a) 사이의 연결을 완전히 차단한다(도 2h 참조).The upper chip 10a and the lower chip 10b receive heat generated from the reflow equipment, flow into the cavity 12 while the bumps 14a are melted, and are combined with a small amount of solder 14b. At this time, the upper insulating layer 13a and the lower insulating layer 13b seal the cavity 12 when the upper chip 10a and the lower chip 10b are bonded to completely block the connection between the adjacent bumps 14a. (See FIG. 2H).

이와 같이, 상기 상부칩(10a)과 하부칩(10b)에 상부절연층(13a)과 하부절연층(13b)을 각각 미리 절반씩 도포하고, 상기 절연층(13a,13b) 내부에 캐비티(12)를 각각 별개로 형성한 후, 상기 절연층(13a,13b)에 의해 밀봉된 캐비티(12) 내에서 열에 의해 상부칩(10a)의 범프(14a)와 하부칩의 솔더(14b)가 용융 및 결합됨으로써, 상부칩(10a)과 하부칩(10b)이 전기적으로 접속된다.In this way, the upper insulating layer 13a and the lower insulating layer 13b are applied in half to the upper chip 10a and the lower chip 10b, respectively, and the cavity 12 is disposed inside the insulating layers 13a and 13b. ) Are formed separately, and the bumps 14a of the upper chip 10a and the solder 14b of the lower chip are melted by heat in the cavity 12 sealed by the insulating layers 13a and 13b. By being coupled, the upper chip 10a and the lower chip 10b are electrically connected.

따라서, 상기와 같은 방법에 의해 상부칩(10a)의 범프(14a)가 하부칩(10b)에 형성된 캐비티(12)로 들어가 하부절연층(13b)의 솔더(14b)와 통전가능하게 결합됨으로써, 상부칩(10a)과 하부칩(10b)이 전기적으로 용이하게 접속될 뿐만 아니라, 범프(14a)의 간격 및 높이가 균일하게 유지되어 칩 간의 적층 밸런스를 안정적으로 유지시킬 수 있다.Therefore, the bump 14a of the upper chip 10a enters the cavity 12 formed in the lower chip 10b by the above method, and is electrically coupled to the solder 14b of the lower insulating layer 13b. The upper chip 10a and the lower chip 10b are not only electrically connected easily, but the spacing and height of the bumps 14a are uniformly maintained, so that the stacking balance between the chips can be stably maintained.

특히, 상기 상부칩(10a)과 하부칩(10b)에 도포된 상부절연층(13a) 및 하부절연층(13b)이 언더필 역할을 수행함에 따라 서로 인접한 범프(14a)는 독립적인 공간에 위치된 상태가 되므로, 종래에 범프(14a) 간의 연결(bridging)에 의한 쇼트 현상을 방지할 수 있다.In particular, as the upper insulating layer 13a and the lower insulating layer 13b applied to the upper chip 10a and the lower chip 10b play an underfill role, bumps 14a adjacent to each other are positioned in independent spaces. In this state, it is possible to prevent a short phenomenon due to bridging between the bumps 14a.

또한, 기존의 언더필 공정을 제거하여 제조공정이 단순해짐에 따라 제조비용을 절감할 수 있다.In addition, as the manufacturing process is simplified by removing the existing underfill process, the manufacturing cost may be reduced.

도 1은 본 발명의 일실시예에 따른 칩 적층형 패키지를 나타내는 단면도1 is a cross-sectional view showing a chip stack package according to an embodiment of the present invention.

도 2는 본 발명의 일실시예에 따른 칩 적층형 패키지의 제조방법을 나타내는 공정도2 is a process chart showing a method of manufacturing a chip stacked package according to an embodiment of the present invention.

도 3은 종래기술에 따른 칩 적층형 패키지를 나타내는 단면도Figure 3 is a cross-sectional view showing a chip stack package according to the prior art

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10a : 상부칩 10b : 하부칩10a: upper chip 10b: lower chip

11a,11b : 전극패드 12 : 캐비티11 a and 11 b: electrode pad 12: cavity

13a : 상부절연층 13b : 하부절연층13a: upper insulating layer 13b: lower insulating layer

14 : 범프 및 솔더의 용융물 14a : 범프14: melt of bump and solder 14a: bump

14b : 솔더14b: solder

Claims (5)

상부칩과 하부칩이 전기적 신호 교환 가능하게 상호 적층되는 칩 적층형 패키지에 있어서,In the chip stack package in which the upper chip and the lower chip are laminated to each other to exchange electrical signals, 상기 상부칩의 저면에 형성된 전극패드에 부착되는 전도성 범프(14a); A conductive bump 14a attached to an electrode pad formed on a bottom surface of the upper chip; 상기 범프(14a)가 노출되게 상부칩(10a)의 저면에 걸쳐 도포된 상부절연층(13a);An upper insulating layer 13a applied over the bottom surface of the upper chip 10a to expose the bumps 14a; 상기 하부칩의 상면에 걸쳐 도포되는 하부절연층(13b); A lower insulating layer 13b applied over the upper surface of the lower chip; 상기 하부칩의 상면에 형성된 전극패드를 노출시키면서 상기 하부절연층에 형성된 캐비티(12); 및A cavity 12 formed in the lower insulating layer while exposing an electrode pad formed on an upper surface of the lower chip; And 상기 하부칩의 전극패드에 닿으면서 캐비티(12) 내에 충진되는 솔더(14b);를 포함하여 구성되고, 상기 상부칩에 부착된 전도성 범프(14a)가 상기 캐비티(12) 내로 삽입되어 솔더(14b)와 통전 가능하게 융착되도록 한 것을 특징으로 하는 칩 적층형 패키지.A solder 14b filled in the cavity 12 while touching the electrode pad of the lower chip, wherein the conductive bump 14a attached to the upper chip is inserted into the cavity 12 to insert the solder 14b. Chip laminated package, characterized in that to be fused to enable electricity. 청구항 1에 있어서, 상기 상부 및 하부절연층(13a,13b)의 재질은 BCB(BenzoCycloButene)인 것을 특징으로 하는 칩 적층형 패키지.The chip stack package of claim 1, wherein the upper and lower insulating layers (13a, 13b) are made of BenzoCycloButene (BCB). 상부칩과 하부칩이 전기적 신호 교환 가능하게 상호 적층되는 칩 적층형 패키지의 제조방법에 있어서,In the manufacturing method of the chip stacked package in which the upper chip and the lower chip are laminated to each other so as to exchange electrical signals, 상부칩(10a)의 저면에 형성된 전극패드(11a)에 전도성 범프(14a)를 부착하는 단계;Attaching the conductive bumps 14a to the electrode pads 11a formed on the bottom surface of the upper chip 10a; 상기 범프(14a)를 포함하도록 상부칩(10a)의 저면에 걸쳐 상부절연층(13a)을 도포하는 단계;Applying an upper insulating layer (13a) over the bottom of the upper chip (10a) to include the bump (14a); 상기 범프(14a)에 도포된 상부절연층(13a)을 제거하여 범프(14a)를 노출시키는 단계;Exposing the bumps (14a) by removing the upper insulating layer (13a) applied to the bumps (14a); 상기 하부칩(10b)의 상면에 걸쳐 하부절연층(13b)을 도포하는 단계;Applying a lower insulating layer (13b) over the upper surface of the lower chip (10b); 상기 하부절연층(13b)의 상면에서 상기 범프(14a)와 대응되는 위치를 노광시켜 캐비티(12)를 형성하는 단계;Exposing a position corresponding to the bump (14a) on the upper surface of the lower insulating layer (13b) to form a cavity (12); 상기 캐비티(12) 내에 솔더(14b)를 하부칩(10b)의 전극패드(11b)와 통전되도록 채우는 단계; 및Filling a solder (14b) into the cavity (12) so as to be energized with the electrode pad (11b) of the lower chip (10b); And 상기 범프(14a)가 캐비티(12) 내의 솔더(14b)와 결합되도록 상기 상부칩(10a)과 하부칩(10b)을 리플로우 장치에 넣은 후 가열하여 접합하는 단계;를 포함하는 것을 특징으로 하는 칩 적층형 패키지의 제조방법.And inserting the upper chip 10a and the lower chip 10b into a reflow apparatus so that the bumps 14a are coupled to the solder 14b in the cavity 12, and then heating and joining the bumps 14a to the bumps 14a. Method of manufacturing a chip stacked package. 청구항 3에 있어서, 상기 상부 및 하부절연층(13a,13b)은 스핀코팅공정에 의해 상부칩(10a) 및 하부칩(10b)에 각각 도포되는 것을 특징으로 하는 칩 적층형 패 키지의 제조방법.The method according to claim 3, wherein the upper and lower insulating layers (13a, 13b) are applied to the upper chip (10a) and the lower chip (10b) by a spin coating process, respectively. 청구항 3에 있어서, 상기 범프(14a)에 도포된 상부절연층(13a)은 플라즈마 에칭공정에 의해 제거되는 것을 특징으로 하는 칩 적층형 패키지의 제조방법.The method according to claim 3, wherein the upper insulating layer (13a) applied to the bumps (14a) is removed by a plasma etching process.
KR20090039722A 2009-05-07 2009-05-07 Chip stacked package and method for manufacturing of it KR101002041B1 (en)

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US9024439B2 (en) 2012-04-16 2015-05-05 SK Hynix Inc. Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

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EP1732127B1 (en) 2005-06-08 2016-12-14 Imec Method for bonding and device manufactured according to such method
KR100713928B1 (en) 2006-02-08 2007-05-07 주식회사 하이닉스반도체 Semiconductor chip package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9024439B2 (en) 2012-04-16 2015-05-05 SK Hynix Inc. Substrates having bumps with holes, semiconductor chips having bumps with holes, semiconductor packages formed using the same, and methods of fabricating the same

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