KR20100120080A - Stacked memory devices - Google Patents

Abstract

PURPOSE: A laminated memory device is provided to reduce the length of a connection line between an X decoder or Y decoder and a memory layer by arranging an X decoder array and a Y decoder array with a lattice shape in the same level of a plurality of memory blocks. CONSTITUTION: A plurality of memory layers(120) are formed on a substrate(110). A plurality of Y decoder layers(141,142,143) are interposed between a plurality of first basic laminate structures(10). An X decoder layer(131) electrically transmits and receives a signal to and from the memory layers of memory groups. First and second front connection lines are arranged on the front of the X decoder layer and the memory layers. First and second rear connection lines are arranged on the rear of the memory layers and the X decoder layer.

Description

Stacked memory devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly to memory devices stacked in a multilayer structure.

Semiconductor products are getting smaller and require higher data throughput. Accordingly, there is a need to increase the degree of integration of nonvolatile memory devices used in such semiconductor products. In this regard, a memory device having a multilayer structure formed by stacking memory layers in three dimensions is considered.

However, since the arrangement of circuits for supporting the operation of the memory device having a multilayer structure is not easy, there is a limit in increasing the degree of integration.

Accordingly, an object of the present invention is to provide a stacked memory device that can be easily integrated.

However, the above technical problem of the present invention is presented by way of example, and the present invention is not limited thereto.

A stacked memory device of one embodiment of the present invention is provided. A substrate is provided. A plurality of memory groups are stacked on each other on the substrate, each of which includes at least one memory layer. A plurality of X-decoder layers are interposed at least one layer across one of the plurality of adjacent memory groups of the plurality of memory groups. A plurality of Y-decoder layers are interposed with the plurality of X-decoder layers at least one layer across one layer between the plurality of adjacent two memory groups.

According to another example of the stacked memory device, the plurality of X-decoder layers and the plurality of Y-decoder layers may be alternately arranged one by one between the plurality of adjacent memory groups.

According to another example of the stacked memory device, each X-decoder layer is coupled to two memory groups disposed above and below a corresponding X-decoder layer of the plurality of adjacent memory groups and / or each Y- The decoder layer may be coupled to two memory groups disposed above and below the corresponding Y-decoder layer among the plurality of adjacent memory groups.

According to another example of the stacked memory device, the plurality of Y-decoder layers may include a plurality of pairs of the first Y-decoder layer and the second Y-decoder layer, which are arranged in pairs with the plurality of X-decoder layers. Each pair of first Y-decoder layers and second Y-decoder layers are stacked adjacent one another, and the plurality of X-decoder layers are interposed one layer across the plurality of adjacent two memory groups. Can be.

According to another example of the stacked memory device, the plurality of X-decoder layers may include a plurality of pairs of the first X-decoder layer and the second X-decoder layer, which are arranged in pairs with the plurality of Y-decoder layers. Each pair of first X-decoder layers and a second X-decoder layer are stacked adjacent to each other, and the plurality of Y-decoder layers are interposed one layer across the plurality of adjacent two memory groups. Can be.

According to another example of the stacked memory device, each X-decoder layer includes the same number of X-decoder pairs as the number of memory layers included in each memory group, and each Y-decoder layer is included in each memory group. The number of Y-decoder pairs equal to the number of memory layers may be included. In this case, the memory cells included in each memory layer are classified into a first group and a second group, and the X-decoders included in each X-decoder pair are connected to the first and second groups of the corresponding memory layer, respectively. The Y-decoders included in each Y-decoder pair may be connected to the first and second groups of the corresponding memory layers, respectively.

According to another example of the stacked memory device, each X-decoder layer includes the same number of X-decoders as the number of memory layers included in each memory group, and each Y-decoder layer is a memory included in each memory group. And the same number of Y-decoders as the number of layers. A stacked memory device according to another aspect of the present invention is provided. A plurality of stacked memory blocks is arranged on the substrate. Each of the stacked memory blocks may include: a plurality of memory groups stacked on the substrate and each including at least one memory layer; A plurality of X-decoder arrays interspersed one by one in the plurality of memory groups; And a plurality of Y-decoder arrays interposed with the plurality of X-decoder arrays one by one in the plurality of memory groups.

According to an example of the stacked memory device, the plurality of X-decoder arrays of each stacked memory block may be disposed at the same level as the plurality of Y-decoder arrays of the stacked memory block adjacent to the stacked memory block.

According to another example of the stacked memory device, each X-decoder array includes X-decoder pairs corresponding to half of the number of memory layers included in each memory group, and each X-decoder pair includes at least two Commonly connected to the memory layers, each Y-decoder array includes a number of Y-decoder pairs corresponding to half of the number of memory layers included in each memory group, and each Y-decoder pair includes at least two memories. May be commonly connected to the layers. In this case, the memory cells included in each memory layer are classified into a first group and a second group, and the X-decoders included in each X-decoder pair are connected to the first and second groups of the corresponding memory layer, respectively. The Y-decoders included in each Y-decoder pair may be connected to the first and second groups of the corresponding memory layers, respectively.

According to another example of the stacked memory device, each X-decoder array includes a number of X-decoders corresponding to half of the number of memory layers included in each memory group, and each X-decoder includes at least two memory layers. Connected to each other, each Y-decoder array includes a number of Y-decoders corresponding to half of the number of memory layers included in each memory group, and each Y-decoder is common to at least two memory layers. Can be connected. A stacked memory device according to another aspect of the present invention is provided. A substrate is provided. A plurality of memory groups each including at least one memory layer and stacked on the substrate are provided. At least one decoder layer is provided between the plurality of memory groups. The at least one decoder layer comprises: an X-decoder array comprising at least one X-decoder; And a Y-decoder array comprising at least one Y-decoder. The at least one X-decoder array and the at least one Y-decoder array in each decoder layer are arranged in a grid form.

According to an example of the stacked memory device, the at least one X-decoder array may include a plurality of X-decoder arrays, and the at least one Y-decoder array may include a plurality of Y-decoder arrays. Furthermore, the plurality of X-decoder arrays and the plurality of Y-decoder arrays may be alternately arranged.

According to the stacked memory device according to example embodiments, X-decoders and Y-decoders may be stacked on different layers to be spaced apart from each other. Therefore, since the X-decoders and the Y-decoders do not need to be arranged together in one layer, the area occupied by the X-decoder or Y-decoder of each layer can be greatly reduced. With such a decoder arrangement, the limitation on the number of stacked layers of the memory layers is reduced, and the degree of integration of the stacked memory elements can be increased.

In addition, according to the stacked memory device according to example embodiments, the X-decoder array and the Y-decoder array may be arranged in a lattice form at the same level of the plurality of memory blocks. Therefore, the memory layers may be connected to not only the X-decoder array or the Y-decoder array of the corresponding memory block, but also the same level of the X-decoder array or the Y-decoder array of adjacent memory blocks. With this decoder arrangement, the length of the connection line between the X-decoder or Y-decoder and the memory layer can be reduced.

In addition, according to the stacked memory device according to example embodiments, the memory cells included in each memory layer are classified into at least two groups, and a plurality of pairs of X-decoders or a plurality of Y- corresponding to each memory layer are classified. May include decoder pairs. Therefore, since the number of memory cells decoded in each X-decoder or Y-decoder is reduced, the complexity of each X-decoder or Y-decoder can be reduced, thereby simplifying the implementation.

1 is a cross-sectional view illustrating a stacked memory device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an example of an X-decoder array of X-decoder layers included in the stacked memory device of FIG. 1; FIG.
3 is a schematic diagram illustrating an example of a Y-decoder array of Y-decoder layers included in the stacked memory device of FIG. 1;
4 is a schematic diagram showing the connection of memory layers with X-decoder arrays and Y-decoder array in the stacked memory device of FIG. 1;
5 is a sectional view showing a stacked memory device according to another embodiment of the present invention;
6 is a sectional view showing a stacked memory device according to another embodiment of the present invention;
7 is a cross-sectional view illustrating a stacked memory device according to still another embodiment of the present invention;
8 is a plan view showing a stacked memory device according to an embodiment of the present invention;
FIG. 9 is an example of a cross-sectional view taken along line AA ′ of the stacked memory device of FIG. 8; FIG.
FIG. 10 is an example of a cross-sectional view taken along line BB ′ of the stacked memory device of FIG. 8; FIG.
FIG. 11 is another example of a cross-sectional view taken along line AA ′ of the stacked memory device of FIG. 8; FIG.
FIG. 12 is another example of a cross-sectional view taken along the line BB ′ of the stacked memory device of FIG. 8; FIG.
13 is a plan view showing a stacked memory device according to another embodiment of the present invention;
FIG. 14 is an example of a cross-sectional view taken along line CC ′ of the stacked memory device of FIG. 13; FIG.
FIG. 15 is an example of a cross-sectional view taken along the line D-D 'of the stacked memory device of FIG. 13; FIG.
FIG. 16 is another example of a cross-sectional view taken along line CC ′ of the stacked memory device of FIG. 13; FIG.
FIG. 17 is another example of a cross-sectional view taken along the line D-D 'of the stacked memory device of FIG. 13; FIG.
18-21 are schematic cross-sectional views showing physical connections of memory layers and an X-decoder array in a stacked memory device in accordance with some embodiments of the present invention;
22 is a schematic diagram showing a memory card according to an embodiment of the present invention; And
23 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the principle of the present invention through a preferred embodiment according to the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. In the drawings, the components may be exaggerated in size for convenience of description.

1 is a cross-sectional view illustrating a stacked memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the stacked memory device 1 may include a substrate 110, a plurality of memory layers 120, a plurality of X-decoder layers 131 and 132, and a plurality of Y-decoder layers 141 and 142. , 143). In FIG. 1, two X-decoder layers 131 and 132 and three Y-decoders 141, 142 and 143 are illustrated for convenience of illustration, but the stacked memory device 1 has a larger number of X-decoders. Layers and Y-decoder layers. Hereinafter, respective components included in the stacked memory device 1 will be described in detail.

A plurality of memory layers 120 may be stacked on the substrate 110. For example, the substrate 110 may include a semiconductor wafer. The stacked structure of the memory layers 120 is effective in increasing the integration degree of the memory device and increasing its capacity. Each memory layer 120 may include memory cell arrays (not shown) arranged in a matrix. The number of memory layers 120 included in the stacked memory device 1 may be appropriately selected according to the memory capacity, and this embodiment is not limited. The memory layer 120 may have various types of memory, such as DRAM, SRAM, flash, PRAM, ReRAM, FeRAM, or MRAM. It may be configured as.

The plurality of memory layers 120 may be grouped into a plurality of memory groups MG1, MG2, MG3, and MG4, and each of the memory groups MG1, MG2, MG3, and MG4 may have the same number of memory layers ( 120). In this embodiment, each memory group MG1, MG2, MG3, and MG4 includes four memory layers 120, but the memory layers included in each memory group MG1, MG2, MG3, and MG4 ( The number of 120 is shown by way of example and does not limit the scope of this embodiment. In a modified example of this embodiment, the memory groups may include different numbers of memory layers 120.

An X-decoder layer and a Y-decoder layer may be alternately disposed between the plurality of memory groups MG1, MG2, MG3, and MG4. Specifically, in the stacked memory device 1, the Y-decoder layer 141, the memory group MG1, the X-decoder layer 131, the memory group MG2, the Y-decoder layer 142, and the memory group ( MG3), the X-decoder layer 132, the memory group MG4 and the Y-decoder layer 143 are sequentially stacked on the substrate 110. In this case, the memory groups MG1 and MG2 disposed up and down about the X-decoder layer 131 and the X-decoder layer 131 are referred to as a first basic stacked structure 10 and the Y-decoder layer 142 ) And the memory groups MG2 and MG3 disposed up and down with respect to the Y-decoder layer 142 will be referred to as a second basic stacked structure 20. Hereinafter, the first and second basic laminated structures 10 and 20 will be described in detail.

First, the stacked memory device 1 includes a plurality of first basic stacked structures 10 stacked on the substrate 110, and a plurality of Y-decoder layers between the plurality of first basic stacked structures 10. Fields 141, 142, and 143 are interposed. In the first basic stacked structure 10, the X-decoder layer 131 may include the memory layers 120 and the first front connection line 135F ′ of the memory group MG2 stacked adjacent to the upper portion thereof. And the memory layers 120 and the second front connection line 135F ″ of the memory group MG1 which are connected to each other through the first back connection line 135B ′ and are stacked adjacent to the bottom of the first back connection line 135B ′. 2 may be connected via the rear connection line 135B ″. Specifically, the first and second front connection lines 135F 'and 135F "and the first and second rear connection lines 135B' and 135B" are for X-decoder connected to each memory layer 120, respectively. The wiring for the X-decoder may be a word line.

As a result, the X-decoder layer 131 may electrically exchange signals with the memory layers 120 of the memory groups MG1 and MG2. For example, the X-decoder layer 131 may decode X-axis address information about memory cells included in each memory layer and transmit the decoded X-axis address information to the memory layers 120. The X-decoder layer 131 may be further electrically connected to an X-buffer or X-driver (not shown) on the substrate 110.

Here, the first and second front connection lines 135F 'and 135F ″ indicated by solid arrows are disposed on the front surface of the X-decoder layer 131 and the memory layers 120 to penetrate the surface of the drawing. The first and second rear connection lines 135B 'and 135B ″ indicated by dotted arrows may be disposed on the rear surface of the X-decoder layer 131 and the memory layers 120. To indicate a connection relationship in a direction penetrating the ground of the drawing. Therefore, since the first and second rear connection lines 135B 'and 135B ″ are not visible in the cross-sectional direction of FIG. 1, they are shown by dotted arrows. FIG. 2 is an X-decoder layer included in the stacked memory device of FIG. 1. A schematic diagram showing an example of an X-decoder array.

1 and 2, the X-decoder layer 131 may include at least one X-decoder array 131A, and the X-decoder array 131A may include a plurality of X-decoders 1311 and 1312. , 1311 ', 1312'). Although four X-decoders 1311, 1312, 1311 ', and 1312' are shown in FIG. 2 for convenience, the X-decoder array 131A may include a larger number of X-decoders.

Memory cells included in each memory layer 120 may be classified into two groups. For example, odd-numbered memory cells among the memory cells included in each memory layer 120 may be classified into a first group, and even-numbered memories may be classified into two groups. The cells may be classified into a second group. However, this is merely an example, and memory cells included in each memory layer 120 may be classified in different ways. In order to decode the X-axis address information of the memory cells classified into two groups as described above, the X-decoder array 131A includes a plurality of X- corresponding to each of the memory layers 120 included in each memory group. May include decoder pairs. Therefore, the X-decoder array 131A may include twice as many X-decoders as the number of memory layers 120 included in each memory group.

In this embodiment, each memory group MG1, MG2, MG3, and MG4 includes four memory layers 120, so that the X-decoder array 131A has four X-decoder pairs, that is, eight It may include X-decoders. Specifically, two first X-decoders 1311 and 1311 'included in the X-decoder array 131A form a first X-decoder pair and two second X-decoders 1312 and 1312'. ) May form a second X-decoder pair. Hereinafter, the connection relationship between each pair of X-decoders and the memory layers 120 will be described in detail.

The first X-decoders 1311 and 1311 ′ may be connected in common to the memory layer 120 positioned closest to the top of the X-decoder layer 131 and the memory layer 120 positioned closest to the bottom. Can be. Here, the first X-decoder 1311 is connected to the first group of the memory layer 120 which is most adjacent to the upper portion of the X-decoder layer 131 through the first front connection line 135F '. The second front connection line 135F ″ may be connected to the first group of the memory layers 120 that are most adjacent to the lower portion of the X-decoder layer 131. The first X-decoder 1311 ' ) Is connected to the second group of memory layers 120 most closely located above the X-decoder layer 131 via the first rear connection line 135B ', and the second rear connection line 135B ". Through the X-decoder layer 131 may be connected to the second group of the memory layer 120 that is most adjacent to the bottom.

Similarly, the second X-decoders 1312 and 1312 'may include the memory layer 120 which is secondly adjacent to the upper portion of the X-decoder layer 131 and the memory layer which is secondly adjacent to the lower portion of the X-decoder layer 131. 120 may be commonly connected. Here, the second X-decoder 1311 is connected to the first group of the memory layers 120 located second adjacent to the upper portion of the X-decoder layer 131 through the first front connection line 135F '. The second X-decoder may be connected to the first group of the memory layer 120 which is secondly located below the X-decoder layer 131 through the second front connection line 135F ″. 1312 ′ is connected to a second group of memory layers 120 secondly adjacent to the upper portion of the X-decoder layer 131 through a first rear connection line 135B ′, and a second rear connection. The line 135B ″ may be connected to a second group of the memory layers 120 which are secondly located below the X-decoder layer 131.

According to the present exemplary embodiment, the memory cells included in the memory layer 120 are classified into two groups, and a pair of X-decoders are symmetrically positioned above and below the X-decoder layer 131. Are connected in common. In this case, one of the pair of X-decoders may be connected to the first group of the corresponding memory layer 120, and the other may be connected to the second group of the corresponding memory layer 120. As a result, since the number of memory cells to be decoded in the X-decoder layer 131 is reduced, the complexity of the X-decoder layer 131 can be reduced, thereby simplifying the implementation thereof.

Referring back to FIG. 1, the stacked memory device 1 includes a plurality of second basic stacked structures 20 stacked on the substrate 110, and a plurality of second basic stacked structures 20 is disposed between the plurality of second basic stacked structures 20. Are interposed between the X-decoder layers 131 and 132. In the second basic stacked structure 20, the Y-decoder layer 142 may include first left connection lines 145L ′ to the memory layers 120 of the memory group MG3 stacked adjacent to the top of the Y-decoder layer 142. ) And the second left connection lines (I) to the memory layers 120 included in the memory group MG2 stacked adjacent to the lower portion thereof and connected to the first right connection lines 145R ′. 145L ″) and second right connection lines 145R ″. Specifically, the first and second left connection lines 145L 'and 145L "and the first and second right connection lines 145R' and 145R" are Y-decoder wires connected to the memory layers 120, respectively. It may be connected to (not shown), where the wiring for the Y-decoder may be a bit line.

As a result, the Y-decoder layer 142 may electrically exchange signals with the memory layers 120 of the memory groups MG2 and MG3. For example, the Y-decoder layer 142 may decode and transmit Y-axis address information of memory cells included in each memory layer to the memory layers 120. The Y-decoder layer 142 may be further electrically connected to a Y-buffer or Y-driver (not shown) on the substrate 110.

Here, the first and second left connection lines 145L 'and 145L ″ and the first and second right connection lines 145R' and 145R ″ indicated by solid lines are connected in a direction parallel to the ground of the drawing. Can be indicated. Thus, the first and second front connection lines 135F 'and 135F "indicated by the solid arrows and the first and second rear connection lines 135B' and 135B" indicated by the dashed arrows are indicated by the first shown by the solid lines. And a connection relationship between the second left connection lines 145L 'and 145L ″ and the first and second right connection lines 145R' and 145R ″ intersecting with each other.

3 is a schematic diagram illustrating an example of a Y-decoder array of a Y-decoder layer included in the stacked memory device of FIG. 1.

1 and 3, the Y-decoder layer 142 may include at least one Y-decoder array 142A, and the Y-decoder array 142A may include a plurality of Y-decoders 1421 and 1422. , 1421 ', and 1422'. Although four Y-decoders 1421, 1422, 1421 ′ and 1422 ′ are shown in FIG. 3 for convenience, the Y-decoder array 142A may include a greater number of Y-decoders.

Memory cells included in each memory layer 120 may be classified into two groups. For example, odd-numbered memory cells among the memory cells included in each memory layer 120 may be classified into a first group, and even-numbered memories may be classified into two groups. The cells may be classified into a second group. However, this is merely an example, and memory cells included in each memory layer 120 may be classified in different ways. In order to decode the Y-axis address information of the memory cells classified into the two groups as described above, the Y-decoder array 142A includes a plurality of Y- corresponding to each of the memory layers 120 included in each memory group. May include decoder pairs. Therefore, the Y-decoder array 142A may include twice as many Y-decoders as the number of memory layers 120 included in each memory group.

In this embodiment, each memory group MG1, MG2, MG3, MG4 includes four memory layers 120, so that the Y-decoder array 142A has four Y-decoder pairs, that is, eight It can include Y-decoders. Specifically, two first Y-decoders 1421 and 1421 'included in the Y-decoder array 142A form a first Y-decoder pair, and two second Y-decoders 1422 and 1422'. ) May form a second Y-decoder pair. Hereinafter, the connection relationship between each pair of Y-decoders and the memory layers 120 will be described in detail.

The first Y-decoders 1421 and 1421 ′ may be commonly connected to the memory layer 120 disposed closest to the upper portion of the Y-decoder layer 142 and the memory layer 120 positioned nearest to the lower portion. Can be. Here, the first Y-decoder 1421 is connected to the first group of the memory layer 120 which is most adjacent to the upper portion of the Y-decoder layer 142 through the first left connection line 145L '. The second left connection line 145L ″ may be connected to the first group of the memory layers 120 that are most adjacent to the lower portion of the Y-decoder layer 142. The first Y-decoder 1421 ' ) Is connected to the second group of the memory layers 120 most adjacent to the top of the Y-decoder layer 142 via the first right connection line 145R ', and the second right connection line 145R ". It may be connected to the second group of the memory layer 120 that is most adjacent to the lower portion of the Y-decoder layer 142 through.

Similarly, the second Y-decoders 1422 and 1422 'may include a memory layer 120 that is secondly adjacent to the upper portion of the Y-decoder layer 142 and a memory layer that is secondly adjacent to the lower portion ( 120 may be commonly connected. Here, the second Y-decoder 1422 is connected to the first group of the memory layers 120 located second adjacent to the upper portion of the Y-decoder layer 142 through the first left connection line 145L '. The second left-side connection line 145L ″ may be connected to a first group of the memory layer 120 which is secondly adjacent to the lower portion of the Y-decoder layer 142. 1422 'is connected to a second group of memory layers 120 which are secondly adjacent to the top of the Y-decoder layer 142 via a first right connection line 145R', and a second right connection A line 145R ″ may be connected to a second group of the memory layers 120 which are secondly adjacent to the lower portion of the Y-decoder layer 142.

According to the present exemplary embodiment, the memory cells included in the memory layer 120 are classified into two groups, and a pair of Y-decoders are symmetrically positioned above and below the Y-decoder layer 142. Are connected in common. In this case, one of the pair of Y-decoders may be connected to the first group of the corresponding memory layer 120, and the other may be connected to the second group of the corresponding memory layer 120. As a result, since the number of memory cells to be decoded in the Y-decoder layer 142 is reduced, the complexity of the Y-decoder layer 142 can be reduced, thereby simplifying the implementation thereof.

4 is a schematic diagram illustrating a connection between memory layers and X-decoder arrays and a Y-decoder array in the stacked memory device of FIG. 1.

1 and 4, the lower memory layer 120a and the upper memory layer 120b may have cell arrays, respectively. The Y-decoder array 142A between the lower and upper memory layers 120a and 120b may be covalently connected to the lower and upper memory layers 120a and 120b. For example, the select bit line BL of the lower and upper memory layers 120a and 120b may be connected to the decoding transistor Td of the Y-decoder array 142A.

The lower X-decoder array 131A below the lower memory layer 120a may be connected to the selection word line WL of the lower memory layer 120a. The upper X-decoder array 132A on the upper memory layer 120b may be connected to the selection word line WL of the upper memory layer 120b.

5 is a cross-sectional view illustrating a stacked memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 5, the stacked memory device 1 ′ may include a substrate 110, a plurality of memory layers 120, a plurality of X-decoder layers 131 and 132, and a plurality of pairs of first Y− Decoder layers 141a, 142a, and 143a and second Y-decoder layers 141b, 142b, and 143b. The stacked memory device 1 'of this embodiment is a modification of some configurations in the stacked memory device 1 of Figs. 1 to 4, and thus, redundant description is omitted.

An X-decoder layer, a pair of first Y-decoder layers, and a second Y-decoder layer may be alternately disposed between the plurality of memory groups MG1, MG2, MG3, and MG4. Specifically, in the stacked memory device 1 ', a pair of first Y-decoder layers 141a and second Y-decoder layers 141b, memory groups MG1, X-decoder layers 131, and memories Group MG2, a pair of first Y-decoder layers 142a and second Y-decoder layers 142b, memory group MG3, X-decoder layer 132, memory group MG4, and one The pair of first Y-decoder layers 143a and second Y-decoder layers 143b are sequentially stacked on the substrate 110. In this case, the memory groups MG1 and MG2 disposed up and down about the X-decoder layer 131 and the X-decoder layer 131 are referred to as a first basic stacked structure 10, and a pair of Y-decoder layers ( The memory groups MG2 and MG3 disposed up and down around the 142a and 142b and the Y-decoder layer pairs 142a and 142b will be referred to as a second basic stacked structure 20 '. Since the first basic stacked structure 10 is substantially the same as the configuration included in FIG. 1, description thereof will be omitted.

The stacked memory device 1 ′ includes a plurality of second basic stacked structures 20 ′ stacked on the substrate 110, and a plurality of X-decoders between the plurality of second basic stacked structures 20 ′. Layers 131, 132 are interposed. In the second basic stacked structure 20 ', the first Y-decoder layer 142a is connected to the first left connection line 145L' and the memory layers 120 of the memory group MG3 stacked adjacent to the upper portion. The second Y-decoder layer 142b may be connected through the first right connection line 145R ', and the second left connection line may be connected to the memory layers 120 of the memory group MG2 stacked adjacent to the bottom of the second Y-decoder layer 142b. 145L ″ and the second right connection line 145R ″.

As a result, the first Y-decoder layer 142a may electrically transmit and receive signals to and from the memory layers 120 of the memory group MG3 stacked adjacent to the upper portion of the first Y-decoder layer 142a. The signal may electrically transmit and receive signals to the memory layers 120 of the memory group MG2 stacked adjacent to the lower portion thereof.

According to this embodiment, two adjacent memory groups share an X-decoder layer disposed therebetween, but do not share a Y-decoder layer disposed therebetween. In other words, an X-decoder layer and a pair of Y-decoder layers are alternately arranged between a plurality of memory groups so that one X-decoder layer exists between two adjacent memory groups and two adjacent memory groups. There are two Y-decoder layers in between. As a result, the Y-axis address may be separately decoded for the memory layers included in two adjacent memory groups.

6 is a cross-sectional view illustrating a stacked memory device according to still another embodiment of the present invention.

Referring to FIG. 6, the stacked memory device 1 ″ may include a substrate 110, a plurality of memory layers 120, a plurality of pairs of first X-decoder layers 131a, 132a, and 133a and a second X. -Decoder layers 131b, 132b, 133b and a plurality of Y-decoder layers 141, 142. The stacked memory device 1 "of this embodiment is the stacked memory device 1 of Figs. ), Some configurations have been modified, and thus redundant descriptions are omitted.

A Y-decoder layer and a pair of first X-decoder layers and a second X-decoder layer may be alternately disposed between the memory groups MG1, MG2, MG3, and MG4. Specifically, in the stacked memory device 1 ", a pair of first X-decoder layer 131a and second X-decoder layer 131b, memory group MG1, Y-decoder layer 141, and memory Group MG2, a pair of first X-decoder layers 132a and second X-decoder layers 132b, memory group MG3, Y-decoder layer 142, memory group MG4, and one A pair of first X-decoder layers 133a and second X-decoder layers 133b are sequentially stacked on the substrate 110. At this time, the Y-decoder layer 141 and the Y-decoder layer 141 are stacked. The memory groups MG1 and MG2 arranged up and down with the center are referred to as the second basic stacked structure 20, and center the X-decoder layer pairs 132a and 132b and the X-decoder layer pairs 132a and 132b. The memory groups MG2 and MG3 disposed up and down are referred to as a first basic stacked structure 10 '. The second basic stacked structure 20 is substantially the same as the configuration included in FIG. The description will be omitted.

The stacked memory device 1 "includes a plurality of first basic stacked structures 10 'stacked on the substrate 110, and a plurality of Y-decoders between the plurality of first basic stacked structures 10'. Intervening layers 141 and 142. In the first basic stacked structure 10 ', the first X-decoder layer 132a is stacked adjacent to the top of the memory layers 120 of the memory group MG3. May be connected to the first front connection line 135F 'and the first rear connection line 135B', and the second X-decoder layer 132b may be stacked adjacent to the memory of the memory group MG2. The layers 120 may be connected through the second front connection line 135F ″ and the second rear connection line 135B ″.

As a result, the first X-decoder layer 132a may electrically transmit and receive signals to and from the memory layers 120 of the memory group MG3 stacked adjacent to the upper portion of the first X-decoder layer 132a. The signal may electrically transmit and receive signals to the memory layers 120 of the memory group MG2 stacked adjacent to the lower portion thereof.

According to this embodiment, two adjacent memory groups share the Y-decoder layer disposed therebetween, but do not share the X-decoder layer disposed therebetween. In other words, a Y-decoder layer and a pair of X-decoder layers are alternately arranged between a plurality of memory groups so that one Y-decoder layer exists between two adjacent memory groups, and two adjacent memory groups. There are two X-decoder layers in between. As a result, the X-axis address may be separately decoded for the memory layers included in two adjacent memory groups.

7 is a cross-sectional view illustrating a stacked memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 7, the stacked memory device 2 may include a substrate 210, a plurality of memory layers 220, a plurality of X-decoder layers 231 and 232, and a plurality of Y-decoder layers 241. 242, 243). In FIG. 7, two X-decoder layers 231 and 232 and three Y-decoder layers 241, 242 and 243 are illustrated for convenience of illustration, but the stacked memory device 2 has a larger number of X−. It may include decoder layers and Y-decoder layers. The stacked memory element 2 of this embodiment is a modification of some configurations in the stacked memory element 1 of FIG. 1, and therefore, redundant description is omitted.

A plurality of memory layers 220 may be stacked on the substrate 110, and the plurality of memory layers 220 may be grouped into a plurality of memory groups MG1, MG2, MG3, and MG4. The Y-decoder layers 241, 242, and 243 and the X-decoder layers 231 and 232 may be alternately disposed between the plurality of memory groups MG1, MG2, MG3, and MG4. In this case, the memory groups MG1 and MG2 disposed up and down around the X-decoder layer 231 and the X-decoder layer 231 are referred to as a first basic stacked structure 30 and the Y-decoder layer 242 ) And the memory groups MG2 and MG3 disposed up and down with respect to the Y-decoder layer 242 will be referred to as a second basic stacked structure 40. Hereinafter, the first and second basic laminated structures 30 and 40 will be described in detail.

First, the stacked memory device 2 includes a plurality of first basic stacked structures 30 stacked on the substrate 220, and a plurality of Y-decoder layers between the plurality of first basic stacked structures 30. Fields 241, 242, and 243 are interposed. In the first basic stacked structure 30, the X-decoder layer 231 may include the memory layers 220, the first front connection line 235F ′, and the first front connection lines of the memory group MG2 stacked adjacent to the upper portion thereof. Memory layers 220, a second front connection line 235F ″, and a second rear connection line 235B of the memory group MG1 stacked adjacent to a lower portion thereof may be connected through the rear connection line 235B ′. Can be connected via ")".

In this case, some of the memory layers 220 included in each memory group may share an X-decoder wire, and the X-decoder wire may be a word line. In the present embodiment, the second memory layer and the third memory layer of the memory layers 220 included in each memory group may share the X-decoder wiring. Accordingly, the X-decoder layer 231 has three first front connection lines 235F 'and three first layers for connection with the memory layers 220 of the memory group MG2 stacked adjacent to the upper portion thereof. 1 may require rear connection lines 235B '. In addition, the X-decoder layer 231 is connected to the memory layers 220 of the memory group MG1 stacked adjacent to the bottom of the second second front connection lines 235F ″ and three thirds. 2 may require rear connection lines 235B ″.

Next, the stacked memory device 2 includes a plurality of second basic stacked structures 40 stacked on the substrate 210, and a plurality of X-decoders between the plurality of second basic stacked structures 40. Layers 231 and 232 are interposed. In the second basic stacked structure 40, the Y-decoder layer 242 may include the memory layers 220 and the first left connection line 245L ′ and the first layers of the memory group MG3 stacked adjacent thereto. The memory layers 220, the second left connection line 245L ″, and the second right connection line 245R of the memory group MG2 stacked adjacent to the bottom thereof and connected through the right connection line 245R ′. Can be connected via ")".

In this case, some of the memory layers 220 included in each memory group may share the Y-decoder wire, and the Y-decoder wire may be a bit line. In the present embodiment, among the memory layers 220 included in each memory group, the first memory layer and the second memory layer may share a Y-decoder wire, and the third memory layer and the fourth memory layer are Y Decoder wiring can be shared. Accordingly, the Y-decoder layer 242 has two first left connection lines 245L 'and two first layers for connection with the memory layers 220 of the memory group MG3 stacked adjacent to the top thereof. 2 may require right connection lines 245R '. In addition, the Y-decoder layer 242 may include two second left connection lines 245L ″ and two second layers for connection with the memory layers 220 of the memory group MG2 stacked adjacent to the bottom thereof. 2 may require right connection lines 245R ″.

According to the present exemplary embodiment, some of the memory layers 220 included in each memory group share the X-decoder wiring / Y-decoder wiring, so that the X-decoder layer 231 / Y-decoder layer 242 ) And the number of connection lines between the memory layers 220 included in each memory group is reduced. In addition, since the number of memory cells decoded in the X-decoder layer 231 / Y-decoder layer 242 is reduced, the complexity of the X-decoder layer 231 / Y-decoder layer 242 can be reduced. The implementation can also be simplified.

Further, according to the modified embodiment of the present embodiment, in the stacked memory device, an X-decoder layer and a pair of Y-decoder layers may be alternately interposed between the plurality of memory groups. At this time, the X-decoder layer is commonly connected to memory groups stacked above and below, but a pair of Y-decoder layers may be connected to memory groups stacked above and memory groups stacked below. Further, according to another modified embodiment of the present embodiment, in the stacked memory device, a Y-decoder layer and a pair of X-decoder layers may be alternately interposed between a plurality of memory groups. At this time, the Y-decoder layer is commonly connected to the memory groups stacked on the upper and lower portions thereof, but the pair of X-decoder layers may be connected to the memory groups stacked on the top and the memory groups stacked on the bottom.

8 is a plan view illustrating a stacked memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the stacked memory device 3 may include first to ninth memory blocks MB1 to MB9, which are a plurality of stacked memory blocks disposed on a substrate (not shown). Although nine memory blocks MB1 to MB9 are illustrated in FIG. 8 for convenience, the stacked memory device 3 may include a larger number of memory blocks.

Each of the memory blocks MB1 to MB9 may include a plurality of memory layers and a plurality of decoder layers, and the decoder layer disposed at a predetermined level of each memory block MB1 to MB9 may be disposed at the same level of the adjacent memory block. It may be arranged alternately with the decoder layer. In detail, when the X-decoder layer 330 is disposed at a predetermined level of each of the memory blocks MB1 to MB9, the Y-decoder layer 340 may be disposed at the same level of the adjacent memory block. As a result, the X-decoder layer 330 and the Y-decoder layer 340 may form a lattice structure at the same level of the plurality of memory blocks MB1 to MB9.

Memory cells included in each memory layer in each memory block MB1 through MB9 may be classified into first and second groups. Here, each X-decoder layer 330 may include a plurality of X-decoder arrays, where the X-decoder array may have a structure similar to that of the X-decoder array shown in FIG. 2. In addition, each Y-decoder layer 340 may include a plurality of Y-decoder arrays, where the Y-decoder array may have a structure similar to that of the Y-decoder array shown in FIG. 3.

Specifically, the first and second groups of each memory layer in the second memory block MB2 may be connected to the Y-decoder layer 340 included in the second memory block MB2, and the second memory block MB2. The first group of each memory layer in X is connected to the X-decoder layer 330 included in the first memory block MB1, and the second group of each memory layer is X included in the third memory block MB3. May be connected to the decoder layer 330. As such, the memory layers in each of the memory blocks MB1 to MB9 are connected to the decoder layer included in the corresponding memory block and the decoder layer included in the adjacent memory block, thereby providing the X-axis address and the Y-axis address required for the operation of the memory layer. Can be decoded.

Meanwhile, the first and second groups of each memory layer in the first memory block MB1 may be connected to the X-decoder layer 330 included in the first memory block MB1, and the first memory block MB1 may be connected. The first group of each memory layer within is connected to the Y-decoder layer 340 included in the fourth memory block MB4, and the second group of each memory layer is adjacent to the left side of the first memory block MB1. It may be connected to the disposed Y-decoder layer 340 '. In addition, the first and second groups of each memory layer in the fourth memory block MB4 may be connected to the Y-decoder layer 340 included in the fourth memory block MB4, and the fourth memory block MB4. The first group of each memory layer in the circuit is connected to the X-decoder layer 330 included in the fifth memory block MB5, and the second group of each memory layer is adjacent to the upper side of the fourth memory block MB4. It may be connected to the disposed X-decoder layer 330 '. As described above, in the case of memory blocks disposed at the outermost part of the stacked memory device 3 and having no adjacent memory blocks, additional decoder layers 330 'and 340' for receiving X-axis address information or Y-axis address information. ) Is required.

FIG. 9 is an example of a cross-sectional view taken along the line AA ′ of the multilayer memory device of FIG. 8. FIG. 10 is an example of a cross-sectional view taken along the line BB ′ of the stacked memory device of FIG. 8.

9 and 10, the second, fifth and eighth memory blocks MB2, MB5, and MB8 are disposed adjacent to each other on the substrate 310 in the direction of line A-A ', and line B-B'. The seventh, eighth, and ninth memory blocks MB7, MB8, and MB9 are disposed adjacent to each other in the direction. Here, each memory block may correspond to the stacked memory device 1 shown in FIG. 1. In the stacked memory device 3, the plurality of first basic stacked structures 50 may be repeatedly formed on the substrate 310, and the plurality of second basic stacked structures 55 may be repeatedly formed. can see. Meanwhile, for the sake of understanding, the X decoder connection line is omitted in FIG. 9 and the Y decoder connection line is omitted in FIG. 10. The combination of the Y decoder connection state of FIG. 9 and the X decoder connection state of FIG. 10 becomes the overall structure of the memory device according to the present embodiment.

First, a memory structure associated with a Y decoder connection structure will be described with reference to FIG. 9.

The first basic stacked structure 50 includes the Y-decoder layer 340 and the X-decoder layer 330 alternately disposed at the same level, and the Y-decoder layer 340 and the X-decoder layer 330, respectively. Memory layers 320 disposed adjacent to the upper and lower sides of the substrate. In detail, the first basic stacked structure 50 includes the Y-decoder layer 340 and the upper and lower portions of the Y-decoder layer 340 included in the second memory block MB2. Included in the X-decoder layer 330 included in the fifth memory block MB5, the memory layers 320 disposed adjacent to the upper and lower portions of the X-decoder layer 330, and the eighth memory block MB8. And the memory layers 320 disposed adjacent to upper and lower portions of the Y-decoder layer 340 and the Y-decoder layer 340. In the present exemplary embodiment, two memory layers 320 may be disposed above and below each decoder layer 330 and 340 in the first basic stacked structure 50.

In the first basic stacked structure 50, a Y-decoder layer 340 is included between the memory layers 320 of the second and eighth memory blocks MB2 and MB8 and the memory of the fifth memory block MB5. Between layers 320 is an X-decoder layer 330. Accordingly, the memory layers 320 of the second and eighth memory blocks MB2 and MB8 may be connected to the Y-decoder layer 340 included in the memory block to receive Y-axis address information. The memory layers 320 of the memory block MB5 may be connected to the Y-decoder layer 340 included in adjacent memory blocks to receive Y-axis address information.

In detail, the first and second groups of the memory layers 320 included in the second memory block MB2 may include the Y-decoder layer 340 and the first connection lines included in the second memory block MB2. The first and second groups of the memory layers 320 included in the eighth memory block MB2 may be connected to each other through the Y-decoder layer 340 included in the eighth memory block MB8. And may be connected through first connection lines 345. Meanwhile, a first group of each memory layer 320 included in the fifth memory block MB5 may connect the Y-decoder layer 340 and the second connection lines 347 included in the second memory block MB2. The second group may be connected through the Y-decoder layer 340 and the second connection lines 347 included in the eighth memory block MB8.

Next, a memory structure associated with an X decoder connection structure will be described with reference to FIG. 10.

The second basic stacked structure 55 includes the X-decoder layer 330 and the Y-decoder layer 340 and the X-decoder layer 330 and the Y-decoder layer 340 which are alternately arranged at the same level. Memory layers 320 disposed adjacent to the upper and lower sides of the substrate. In detail, the second basic stacked structure 55 may include the X-decoder layer 330 and the upper and lower portions of the X-decoder layer 330 included in the seventh memory block MB7. Included in the Y-decoder layer 340 included in the eighth memory block MB8, the memory layers 320 disposed adjacent to the upper and lower portions of the Y-decoder layer 340, and the ninth memory block MB9. The X-decoder layer 330 and the memory layers 320 disposed adjacent to upper and lower portions of the X-decoder layer 330 may be included. In the present exemplary embodiment, two memory layers 320 may be disposed above and below each decoder layer 330 and 340 in the second basic stacked structure 55.

In the second basic stacked structure 55, an X-decoder layer 330 is included between the memory layers 320 of the seventh and ninth memory blocks MB7 and MB9, and the memory of the eighth memory block MB8 is included. A layer Y-decoder 340 is included between the layers 320. Accordingly, the memory layers 320 of the seventh and ninth memory blocks MB7 and MB9 may be connected to the X-decoder layer 330 included in the memory block to receive X-axis address information. The memory layers 320 of the memory block MB8 may be connected to the X-decoder layer 330 included in adjacent memory blocks to receive X-axis address information.

In detail, the first and second groups of the memory layers 320 included in the seventh memory block MB7 may include the X-decoder layer 330 and the third connection lines included in the seventh memory block MB7. The first and second groups of the memory layers 320 included in the ninth memory block MB9 may be connected to each other through the 335, and the X-decoder layer 330 included in the ninth memory block MB9. And the third connection lines 335 may be connected. Meanwhile, the first group of each memory layer 320 included in the eighth memory block MB8 may connect the X-decoder layer 330 and the fourth connection lines 337 included in the seventh memory block MB7. The second group may be connected to the X-decoder layer 330 included in the ninth memory block MB9 through the fourth connection lines 337.

In this embodiment, the X-decoder layer and the Y-decoder layer may be alternately interposed between the plurality of memory groups in each memory block, and the X-decoder layer and the Y-decoder are located at the same level of the plurality of memory blocks. The layers can be arranged alternately. As such, the X-decoder layer of each memory block may be arranged to be surrounded by Y-decoder layers located at the same level in adjacent memory blocks. Similarly, the Y-decoder layer of each memory block may be arranged to be surrounded by X-decoder layers located at the same level in adjacent memory blocks. Thus, X-decoder layers and Y-decoder layers may be staggered across the memory blocks at the same level on the substrate 310.

According to the present embodiment, in the first or second basic stacked structures 50 and 55, the memory layers 320 included in each memory block are located at the same level in the decoder layer and adjacent memory blocks in the memory block. May be connected to the decoder layer. Therefore, since the length of the connection lines can be shortened, the interference of the signal can be reduced and the connection efficiency can be improved.

In addition, since the memory cells included in each memory layer 320 are classified into two groups, each decoder layer 330, 340 in the first or second basic stacked structure 50, 55 is a memory layer in a corresponding memory block. And a plurality of decoder pairs corresponding to one half of the number of fields 320. One decoder pair may be connected to each memory layer 320 through one connection line pair, thereby dividing the memory cells included in each memory layer 320 into two groups. Therefore, since the complexity of the decoders included in each decoder layer 330 and 340 can be reduced, consequently, the integration efficiency of the stacked memory device 3 can be improved.

FIG. 11 is another example of a cross-sectional view taken along the line AA ′ of the multilayer memory device of FIG. 8. FIG. 12 is another example of a cross-sectional view taken along the line BB ′ of the stacked memory device of FIG. 8.

11 and 12, the second, fifth and eighth memory blocks MB2 ′, MB5 ′, and MB8 ′ are disposed adjacent to each other on the substrate 310 ′ in the line A-A ′, and B is disposed adjacent to each other. The seventh, eighth, and ninth memory blocks MB7 ', MB8', and MB9 'are disposed adjacent to each other in the -B' line direction. Here, each memory block may correspond to the stacked memory device 2 shown in FIG. 7. In the stacked memory device 3 ′, the plurality of first basic stacked structures 60 may be repeatedly formed on the substrate 310 ′, and the plurality of second basic stacked structures 65 may be repeatedly formed. It can also be seen as. Meanwhile, for the sake of understanding, the X decoder connection line is omitted in FIG. 11 and the Y decoder connection line is omitted in FIG. 12. Combining the Y decoder connection state of FIG. 11 and the X decoder connection state of FIG. 12 becomes the overall structure of the memory device according to the present embodiment.

First, a memory structure associated with a Y decoder connection structure will be described with reference to FIG. 11.

The first basic stacked structure 60 has a Y-decoder layer 340 and an X-decoder layer 330 alternately disposed at the same level, and a Y-decoder layer 340 and an X-decoder layer 330, respectively. Memory layers 320 disposed adjacent to the upper and lower sides of the substrate. In detail, the first basic stacked structure 60 may include the Y-decoder layer 340 and the upper and lower portions of the Y-decoder layer 340 included in the second memory block MB2 ′. ), Memory layers 320 disposed adjacent to upper and lower portions of the X-decoder layer 330 and the X-decoder layer 330 included in the fifth memory block MB5 ', and the eighth memory block MB8'. ) May include a Y-decoder layer 340 and memory layers 320 adjacent to upper and lower portions of the Y-decoder layer 340. In the present exemplary embodiment, two memory layers 320 may be disposed above and below each decoder layer 330 and 340 in the first basic stacked structure 60.

In the first basic stacked structure 60, the Y-decoder layer 340 is included between the memory layers 320 of the second and eighth memory blocks MB2 ′ and MB8 ′, and the fifth memory block MB5 ′. X-decoder layer 330 is included between the memory layers 320. Therefore, the memory layers 320 of the second and eighth memory blocks MB2 'and MB8' may be connected to the Y-decoder layer 340 included in the memory block to receive Y-axis address information. The memory layers 320 of the fifth memory block MB5 ′ may be connected to the Y-decoder layer 340 included in adjacent memory blocks to receive Y-axis address information.

In detail, the first and second groups of the memory layers 320 included in the second memory block MB2 'are connected to the Y-decoder layer 340 included in the second memory block MB2'. The first and second groups of each memory layer 320 included in the eighth memory block MB8 'may be connected through the lines 345', and Y− may be included in the eighth memory block MB8 '. The decoder layer 340 may be connected through the first connection lines 345 ′. The first group of each memory layer 320 included in the fifth memory block MB5 ′ is the Y-decoder layer 340 and the second connection lines 347 included in the second memory block MB2 ′. ') May be connected, and the second group may be connected to the Y-decoder layer 340 included in the eighth memory block MB8' through the second connection lines 347 '.

At this time, the first memory layer 320 and the second memory layer 320 of each memory group share the Y-decoder wiring, and the third memory layer 320 and the fourth memory layer 320 are Y-decoder. You can share the wiring. Therefore, in the second memory block MB2 ', the Y-decoder layer 340 is connected to the Y-decoder between the memory layers 320 disposed thereon through the pair of first connection lines 345'. It may be connected in common to the first connection line 345 ′, and may be commonly connected to the Y-decoder wiring between the memory layers 320 disposed thereunder. In addition, the Y-decoder layer 340 of the second memory block MB2 'is disposed on the X-decoder layer 330 in the fifth memory block MB5' through one second connection line 347 '. Memory layers disposed in a lower portion of the X-decoder layer 330 through the second connection line 347 ', which are commonly connected to the Y-decoder wiring between the memory layers 320 disposed therein. It may be commonly connected to the Y-decoder wiring between 320). In addition, the Y-decoder layer 340 of the eighth memory block MB8 'is disposed on the X-decoder layer 330 in the fifth memory block MB5' through one second connection line 347 '. Memory layers disposed in a lower portion of the X-decoder layer 330 through the second connection line 347 ', which are commonly connected to the Y-decoder wiring between the memory layers 320 disposed therein. It may be commonly connected to the Y-decoder wiring between 320).

Next, a memory structure associated with an X decoder connection structure will be described with reference to FIG. 12.

The second basic stacked structure 65 has an X-decoder layer 330 and a Y-decoder layer 340 alternately arranged at the same level, and an X-decoder layer 330 and a Y-decoder layer 340, respectively. Memory layers 320 disposed adjacent to the upper and lower sides of the substrate. In detail, the second basic stacked structure 65 may include the X-decoder layer 330 and the upper and lower portions of the X-decoder layer 330 included in the seventh memory block MB7 ′. ), The Y-decoder layer 340 included in the eighth memory block MB8 ′, the memory layers 320 disposed adjacent to the upper and lower portions of the Y-decoder layer 340, and the ninth memory block MB9 ′. ) May include an X-decoder layer 330 and memory layers 320 adjacent to upper and lower portions of the X-decoder layer 330. In the present exemplary embodiment, two memory layers 320 may be disposed above and below each decoder layer 330 and 340 in the second basic stacked structure 65.

In the second basic stacked structure 65, an X-decoder layer 330 is included between the memory layers 320 of the seventh and ninth memory blocks MB7 ′ and MB9 ′, and the eighth memory block MB8 ′. The Y-decoder layer 340 is included between the memory layers 320. Therefore, the memory layers 320 of the seventh and ninth memory blocks MB7 'and MB9' may be connected to the X-decoder layer 330 included in the memory block to receive X-axis address information. The memory layers 320 of the eighth memory block MB5 ′ may be connected to the X-decoder layer 330 included in adjacent memory blocks to receive X-axis address information.

In detail, the first and second groups of the memory layers 320 included in the seventh memory block MB7 ′ are connected to the X-decoder layer 330 included in the seventh memory block MB7 ′. The first and second groups of the memory layers 320 included in the ninth memory block MB9 'may be connected through the lines 335', and X− included in the ninth memory block MB9 '. The decoder layer 330 may be connected to the third connection lines 335 ′. Meanwhile, the first group of each memory layer 320 included in the eighth memory block MB8 'is the X-decoder layer 330 and the fourth connection lines 337 included in the seventh memory block MB7'. ') May be connected, and the second group may be connected to the X-decoder layer 330 included in the ninth memory block MB9' through the fourth connection lines 337 '.

In this case, the second memory layer 320 and the third memory layer 320 of each memory group may share the X-decoder wiring. Therefore, in the seventh memory block MB7 ', the X-decoder layer 330 is connected to the X-decoder between the memory layers 320 disposed thereon through a pair of third connection lines 335'. Are commonly connected to the X-decoder wiring between the memory layers 320 disposed under the pair of third connection lines 335 '. In addition, the X-decoder layer 330 of the seventh memory block MB7 'is disposed on the upper portion of the Y-decoder layer 330 in the eighth memory block MB8' through one fourth connection line 337 '. Memory layers disposed in a lower portion of the Y-decoder layer 330 through the other fourth connection line 337 ', which are commonly connected to the X-decoder wiring between the memory layers 320 disposed therein. It may be commonly connected to the X-decoder wiring between 320). In addition, the X-decoder layer 330 of the ninth memory block MB9 'is disposed on the Y-decoder layer 340 in the eighth memory block MB8' through one fourth connection line 337 '. Memory layers disposed in a lower portion of the Y-decoder layer 340 through the other fourth connection line 337 ', which are commonly connected to the X-decoder wiring between the memory layers 320 disposed therein. It may be commonly connected to the X-decoder wiring between 320).

Although not shown in FIG. 12, in the second basic stacked structure 65, the memory layers 320 included in the seventh and ninth memory blocks MB7 ′ and MB9 ′ may be formed of seventh and ninth memory blocks, respectively. Y-axis address information may be received from a Y-decoder layer included in a memory block (not shown) disposed at the rear of MB7 'and MB9'.

In this embodiment, the X-decoder layer and the Y-decoder layer may be alternately interposed between the plurality of memory groups in each memory block, and the X-decoder layer and the Y-decoder are located at the same level of the plurality of memory blocks. The layers can be arranged alternately. As such, the X-decoder layer of each memory block may be arranged to be surrounded by Y-decoder layers located at the same level in adjacent memory blocks. Similarly, the Y-decoder layer of each memory block may be arranged to be surrounded by X-decoder layers located at the same level in adjacent memory blocks. Thus, X-decoder layers and Y-decoder layers may be staggered across the memory blocks at the same level on the substrate 310 '.

According to the present embodiment, in the first or second basic stacked structure 60.65, the memory layers 320 included in each memory block are located at the same level in the decoder layer and adjacent memory blocks in the memory block. May be connected to the decoder layer. Therefore, since the length of the connection lines can be shortened, the interference of the signal can be reduced and the connection efficiency can be improved.

In addition, since the memory cells included in each memory layer 320 are classified into two groups, each decoder layer 330 or 340 in the first or second basic stacked structure 60 or 65 may be a memory layer in the corresponding memory group. And a plurality of decoder pairs corresponding to one half of the number of fields 320. One decoder pair may be connected to each memory layer 320 through one connection line pair, thereby dividing the memory cells included in each memory layer 320 into two groups. Therefore, since the complexity of the decoders included in each decoder layer 330 and 340 can be reduced, consequently, the integration efficiency of the stacked memory device 3 can be improved.

13 is a plan view illustrating a stacked memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 13, the stacked memory device 4 may include first to fourth memory blocks MB1 to MB4 which are a plurality of stacked memory blocks disposed on a substrate (not shown). Although four memory blocks MB1 to MB4 are shown in FIG. 13 for convenience, the stacked memory device 4 may include a larger number of memory blocks. This embodiment is a modification of a part of the configuration in the stacked memory element 3 of FIG. 8, and therefore, redundant description is omitted.

Each of the memory blocks MB1 to MB4 may include a plurality of memory layers and a plurality of decoder layers. The decoder layers disposed at predetermined levels of each of the memory blocks MB1 to MB4 may be disposed at the same level of adjacent memory blocks. It may be arranged alternately with the decoder layer. In detail, when the X-decoder layer 430 is disposed at a predetermined level of each of the memory blocks MB1 to MB4, the Y-decoder layer 440 may be disposed at the same level of the adjacent memory block. As a result, the X-decoder layer 430 and the Y-decoder layer 440 may form a lattice structure at the same level of the plurality of memory blocks MB1 to MB4.

Here, each X-decoder layer 430 may include one or more X-decoder arrays, and each Y-decoder layer 440 may include one or more Y-decoder arrays.

In detail, each memory layer in the first memory block MB1 may be connected to an X-decoder layer 430 included in the first memory block MB1, and each memory layer in the first memory block MB1 may be formed of a first memory block MB1. 3 may be connected to the Y-decoder layer 440 included in the memory block MB1. In addition, each memory layer in the second memory block MB2 may be connected to the Y-decoder layer 440 included in the second memory block MB2, and each memory layer in the second memory block MB2 may be connected to the fourth memory block MB4. It may be connected to the X-decoder layer 430 included in the memory block MB4. Therefore, even in the case of a memory block disposed at the outermost part of the stacked memory element 4 and without an adjacent memory block, the arrangement of additional decoder layers for receiving X-axis address information or Y-axis address information is not required. As a result, the overall implementation area of the stacked memory device 4 may be reduced.

FIG. 14 is an example of a cross-sectional view taken along the line CC ′ of the stacked memory device of FIG. 13. FIG. 15 is an example of a cross-sectional view taken along the line D-D 'of the stacked memory device of FIG. 13.

14 and 15, the first and third memory blocks MB1 and MB3 are disposed adjacent to each other on the substrate 410 in the C-C 'line direction, and the third and the third and third memory blocks MB1 and MB3 in the D-D' line direction. Fourth memory blocks MB3 and MB4 are adjacent to each other. Here, each memory block may correspond to the stacked memory device 1 shown in FIG. 1. In the stacked memory device 4, the plurality of first basic stacked structures 70 may be repeatedly formed on the substrate 410, and the plurality of second basic stacked structures 75 may be repeatedly formed. can see. Meanwhile, for the sake of understanding, the X decoder connection line is omitted in FIG. 14 and the Y decoder connection line is omitted in FIG. 15. The combination of the Y decoder connection state of FIG. 14 and the X decoder connection state of FIG. 15 becomes the overall structure of the memory device according to the present embodiment.

First, a memory structure associated with a Y decoder connection structure will be described with reference to FIG. 14.

The first basic stacked structure 70 has a Y-decoder layer 440 and an X-decoder layer 430 alternately disposed at the same level, and a Y-decoder layer 440 and an X-decoder layer 430, respectively. Memory layers 420 disposed adjacent to the upper and lower sides of the substrate. In detail, the first basic stacked structure 70 may include the Y-decoder layer 440 included in the first memory block MB1 and the memory layers 420 adjacent to the upper and lower portions of the Y-decoder layer 440. And an X-decoder layer 430 included in the third memory block MB3 and memory layers 420 disposed adjacent to upper and lower portions of the X-decoder layer 430. In the present exemplary embodiment, two memory layers 420 may be disposed above and below each decoder layer 430 and 440 in the first basic stacked structure 70.

In the first basic stacked structure 70, the Y-decoder layer 440 is included between the memory layers 420 of the first memory block MB1, and the memory layers 420 of the third memory block MB3. An X-decoder layer 430 is included in between. Therefore, the memory layers 420 of the first memory block MB1 may be connected to the Y-decoder layer 440 included in the memory block to receive Y-axis address information, and the third memory block MB3 may be used. The memory layers 420 may be connected to the Y-decoder layer 440 included in adjacent memory blocks to receive Y-axis address information.

In detail, each memory layer 420 included in the first memory block MB1 may be connected to the Y-decoder layer 440 included in the first memory block MB1 through the first connection lines 445. Each memory layer 420 included in the third memory block MB3 may be connected to the Y-decoder layer 440 included in the first memory block MB1 through the second connection lines 447. .

Next, a memory structure associated with an X decoder connection structure will be described with reference to FIG. 15.

The second basic stacked structure 75 has an X-decoder layer 430 and a Y-decoder layer 440 alternately arranged at the same level, and an X-decoder layer 430 and a Y-decoder layer 440, respectively. Memory layers 420 disposed adjacent to the upper and lower sides of the substrate. In detail, the second basic stacked structure 75 includes the X-decoder layer 430 and the upper and lower portions of the X-decoder layer 430 included in the third memory block MB3. And a Y-decoder layer 440 included in the fourth memory block MB4 and memory layers 420 disposed adjacent to upper and lower portions of the Y-decoder layer 440. In the present exemplary embodiment, two memory layers 420 may be disposed above and below each decoder layer in the second basic stacked structure 75.

The X-decoder layer 430 is included between the memory layers 420 of the third memory block MB3 in the second basic stacked structure 75, and the memory layers 420 of the fourth memory block MB4. A Y-decoder layer 440 is included in between. Therefore, the memory layers 420 of the third memory block MB3 may be connected to the X-decoder layer 430 included in the corresponding memory block to receive X-axis address information, and the fourth memory block MB4 may be used. The memory layers 420 may be connected to the X-decoder layer 430 included in adjacent memory blocks to receive X-axis address information.

In detail, each memory layer 420 included in the third memory block MB3 may be connected to the X-decoder layer 430 included in the first memory block MB1 through the third connection lines 435. Each memory layer 420 included in the fourth memory block MB4 may be connected to the X-decoder layer 430 included in the third memory block MB3 through the fourth connection lines 437. .

In this embodiment, the X-decoder layer and the Y-decoder layer may be alternately interposed between the plurality of memory groups in each memory block, and the X-decoder layer and the Y-decoder are located at the same level of the plurality of memory blocks. The layers can be arranged alternately. As such, the X-decoder layer of each memory block may be arranged to be surrounded by Y-decoder layers located at the same level in adjacent memory blocks. Similarly, the Y-decoder layer of each memory block may be arranged to be surrounded by X-decoder layers located at the same level in adjacent memory blocks. Thus, X-decoder layers and Y-decoder layers may be staggered across the memory blocks at the same level on the substrate 410.

According to the present embodiment, in the first or second basic stacked structure 70.75, the memory layers 420 included in each memory block are located at the same level in the decoder layer and the adjacent memory block in the memory block. May be connected to the decoder layer. Therefore, since the length of the connection lines can be shortened, the interference of the signal can be reduced and the connection efficiency can be improved.

FIG. 16 is another example of a cross-sectional view taken along the line CC ′ of the stacked memory device of FIG. 13. 17 is another example of a cross-sectional view taken along the line D-D 'of the stacked memory device of FIG. 13.

16 and 17, the first and third memory blocks MB1 ′ and MB3 ′ are disposed adjacent to each other on the substrate 410 ′ in the C-C ′ line direction and in the D-D ′ line direction. The third and fourth memory blocks MB3 'and MB4' are disposed adjacent to each other. Here, each memory block may correspond to the stacked memory device 2 shown in FIG. 7. In the stacked memory device 4, the plurality of first basic stacked structures 80 may be repeatedly formed on the substrate 410 ′, and the plurality of second basic stacked structures 85 may be repeatedly formed. Can also be seen. Meanwhile, for the sake of understanding, the X decoder connection line is omitted in FIG. 16 and the Y decoder connection line is omitted in FIG. 17. The combination of the Y decoder connection state of FIG. 16 and the X decoder connection state of FIG. 16 becomes the overall structure of the memory device according to the present embodiment.

First, a memory structure associated with a Y decoder connection structure will be described with reference to FIG. 16.

The first basic stacked structure 80 has a Y-decoder layer 440 and an X-decoder layer 430 alternately disposed at the same level, and a Y-decoder layer 440 and an X-decoder layer 430, respectively. Memory layers 420 disposed adjacent to the upper and lower sides of the substrate. In detail, the first basic stacked structure 80 may include memory layers 420 disposed adjacent to upper and lower portions of the Y-decoder layer 440 and the Y-decoder layer 440 included in the first memory block MB1 ′. ) And the X-decoder layer 430 included in the third memory block MB3 ′ and the memory layers 420 disposed adjacent to upper and lower portions of the X-decoder layer 430. In the present exemplary embodiment, two memory layers 420 may be disposed above and below each decoder layer 430 and 440 in the first basic stacked structure 80.

In the first basic stacked structure 80, the Y-decoder layer 440 is included between the memory layers 420 of the first memory block MB1 ′, and the memory layers of the third memory block MB3 ′ ( An X-decoder layer 430 is included between the 420s. Accordingly, the memory layers 420 of the first memory block MB1 ′ may be connected to the Y-decoder layer 440 included in the corresponding memory block to receive Y-axis address information, and the third memory block MB3 may be used. ') May be connected to the Y-decoder layer 440 included in adjacent memory blocks to receive Y-axis address information.

Specifically, each of the memory layers 420 included in the first memory block MB1 ′ may connect the Y-decoder layer 440 and the first connection lines 445 ′ included in the first memory block MB1 ′. Each memory layer 320 included in the third memory block MB3 ′ may be connected to each other through the Y-decoder layer 440 and the second connection lines 447 ′ included in the first memory block MB1. Can be connected via.

Although not shown in FIG. 16, in each memory group of the second memory block MB2 ′, a second memory layer and a third memory layer are disposed on a rear surface of the second memory block MB2 ′ (not shown). X-axis address information may be received from the X-decoder layer included in the. In addition, in each memory group of the eighth memory block MB8 ', the second memory layer and the third memory layer are X- included in a memory block (not shown) disposed behind the eighth memory block MB8'. X-axis address information may be received from the decoder layer.

Next, a memory structure associated with an X decoder connection structure will be described with reference to FIG. 17.

The second basic stacked structure 85 has the X-decoder layer 430 and the Y-decoder layer 440 alternately disposed at the same level, and the X-decoder layer 430 and the Y-decoder layer 440, respectively. Memory layers 420 disposed adjacent to the upper and lower sides of the substrate. In detail, the second basic stacked structure 85 includes memory layers 420 disposed adjacent to upper and lower portions of the X-decoder layer 430 and the X-decoder layer 430 included in the third memory block MB3 ′. And the Y-decoder layer 440 included in the fourth memory block MB4 ′ and the memory layers 420 disposed adjacent to upper and lower portions of the Y-decoder layer 440. In the present exemplary embodiment, two memory layers 420 may be disposed above and below each decoder layer in the second basic stacked structure 85.

In the second basic stacked structure 85, the X-decoder layer 430 is included between the memory layers 420 of the third memory block MB3 ′, and the memory layers of the fourth memory block MB4 ′ ( Between the 420 is a Y-decoder layer 440. Accordingly, the memory layers 420 of the third memory block MB3 ′ may be connected to the X-decoder layer 430 included in the corresponding memory block to receive X-axis address information, and the fourth memory block MB4. The memory layers 420 of ') may be connected to the X-decoder layer 430 included in adjacent memory blocks to receive X-axis address information.

In detail, each memory layer 420 included in the third memory block MB3 ′ may connect the X-decoder layer 430 and the third connection lines 435 ′ included in the third memory block MB3 ′. Each memory layer 420 included in the fourth memory block MB4 'may be connected to the X-decoder layer 430 and the fourth connection lines 437' included in the third memory block MB3 '. ) Can be connected.

Although not shown in FIG. 17, in the second basic stacked structure 85, the memory layers 420 included in the seventh and ninth memory blocks MB7 ′ and MB9 ′ may be formed of the seventh and ninth memory blocks, respectively. Y-axis address information may be received from a Y-decoder layer included in a memory block (not shown) disposed at the rear of MB7 'and MB9'.

In this embodiment, the X-decoder layer and the Y-decoder layer may be alternately interposed between the plurality of memory groups in each memory block, and the X-decoder layer and the Y-decoder are located at the same level of the plurality of memory blocks. The layers can be arranged alternately. As such, the X-decoder layer of each memory block may be arranged to be surrounded by Y-decoder layers located at the same level in adjacent memory blocks. Similarly, the Y-decoder layer of each memory block may be arranged to be surrounded by X-decoder layers located at the same level in adjacent memory blocks. Thus, X-decoder layers and Y-decoder layers may be staggered across the memory blocks at the same level on the substrate 410.

According to the present embodiment, in the first or second basic stacked structures 80 and 85, the memory layers 420 included in each memory block are located at the same level in the decoder layer and adjacent memory blocks in the memory block. May be connected to the decoder layer. Therefore, since the length of the connection lines can be shortened, the interference of the signal can be reduced and the connection efficiency can be improved.

FIG. 18 is a schematic cross-sectional view illustrating physical connection of memory layers and an X-decoder array in a stacked memory device according to an exemplary embodiment of the present invention. The stacked memory devices according to the embodiments of FIGS. 1 to 6 may be physically implemented as shown in FIG. 18.

Referring to FIG. 18, a plurality of memory cells MC may be arranged in a plurality of layers, for example, three layers. For example, each memory cell MC may include a variable resistor R and a diode D. FIG. The variable resistor R may have a high resistance state and a low resistance state according to the applied voltage, and thus may be used as a data storage medium. Memory cells MC of each layer may be arranged in an array structure.

The word lines WL may extend in one direction to couple with the memory cells MC of the corresponding layer. Therefore, memory cells MC of another layer may be coupled to other word lines WL. The bit lines BL may extend to cross the word lines WL with the memory cells MC interposed therebetween. According to the present exemplary embodiment, corresponding word lines WL and bit lines BL are connected to one memory cell MC, respectively.

The word lines WL may be combined with the X-decoder array X-DEC. The X-decoder array X-DA may include X-decoders X-DEC equal to the number of stacked layers of the memory cells MC. Each X-decoder X-DEC may include a decoding transistor Td. The X-decoders X-DEC included in the X-decoder array X-DA may be coupled one-to-one with the word lines WL.

19 is a schematic cross-sectional view illustrating a physical connection between memory layers and an X-decoder array in a stacked memory device according to another exemplary embodiment of the present invention. The stacked memory devices according to the embodiments of FIGS. 8 to 10 and 13 to 15 may be physically implemented as shown in FIG. 19.

Referring to FIG. 19, memory cells MC in the memory blocks MBn-1 and MBn may be stacked in a plurality of layers, for example, three layers. This embodiment is partially modified by extending the stacked memory device of FIG. 18 in units of memory blocks, and thus redundant description is omitted.

The word lines WL may extend in one direction to couple with the memory cells MC of the corresponding layer. The bit lines BL may extend to cross the word lines WL with the memory cells MC interposed therebetween. In this case, the word lines WL included in the adjacent memory blocks MBn-1 and MBn may be connected to one, and the word lines WL connected to the one may be coupled to the X-decoder array X-DA. Can be.

The X-decoder array X-DA may include one X-decoder X-DEC, and may be connected to one X-decoder X-DEC by connecting word lines WL connected to each other. The memory cells MC may be decoded. Therefore, the implementation of the X-decoder X-DEC is simple, and the decoding speed for each of the memory cells MC can be greatly improved.

20 is a schematic cross-sectional view illustrating a physical connection between memory layers and an X-decoder array in a stacked memory device according to another exemplary embodiment of the present invention. As illustrated in FIG. 20, the stacked memory device according to the exemplary embodiment of FIG. 7 may be physically implemented.

Referring to FIG. 20, a plurality of memory cells MC may be arranged in a plurality of layers, for example, four layers. This embodiment is a modification of the configuration of the stacked memory device of FIG. 18, and thus redundant description is omitted.

The word lines WL may extend in one direction to covalently couple with the memory cells MC of two adjacent layers. For example, the memory cells MC included in the second and third layers may share one word line WL. In addition, the bit lines BL may extend to cross the word lines WL with the memory cells MC interposed therebetween. For example, the memory cells MC included in the first and second layers may share the bit lines BL, and the memory cells MC included in the third and fourth layers may be the bit lines. Each BL can be shared. According to the present exemplary embodiment, the number of word lines WL and bit lines BL may be reduced as a whole due to sharing of the word line WL and the bit line BL. Therefore, the process cost can be reduced, and the area occupied by the decoders can be reduced.

The word lines WL may be combined with the X-decoder array X-DA. The X-decoder array X-DA may include a smaller number of X-decoders X-DEC than a stacked number of memory cells MC. The X-decoders X-DEC may be combined with the word lines WL. According to this embodiment, the number of X-decoders X-DEC can be reduced by using a shared structure.

FIG. 21 is a schematic cross-sectional view illustrating physical connection between memory layers and an X-decoder array in a stacked memory device according to still another embodiment of the inventive concept. The stacked memory devices according to the embodiments of FIGS. 8, 11 through 13, 16, and 17 may be physically implemented as shown in FIG. 21.

Referring to FIG. 21, the memory cells MC in the memory blocks MBn-1, MBn, and MBn + 1 may be stacked in a plurality of layers, for example, four layers. This embodiment is partially modified by extending the stacked memory of FIG. 20 in units of memory blocks, and thus redundant description is omitted.

The word lines WLe and WLo may be alternately arranged to covalently couple with the memory cells MC of two adjacent layers. For example, the memory cells MC of the second and third layers may be covalently coupled to the word lines WLe therebetween. On the other hand, memory cells MC of the first and fourth layers may be covalently coupled to word lines WLo adjacent thereto. The bit lines BL may extend to cross the word lines WLe and WLo with the memory cells MC interposed therebetween.

The word lines WLe and WLo may be combined with the X-decoder array X-DA. The X-decoder array X-DA may include X-decoders X-DEC. For example, the word lines WLo in the adjacent memory blocks MBn-1 and MBn may be connected to each other and covalently coupled to the X-decoder X-DEC. The word lines WLe in the other adjacent memory blocks MBn and MBn + 1 may be connected to each other and covalently coupled to the X-decoder X-DEC. Here, the X-decoder array X-DA is shown to be located at the same level, but the X-decoders X-DEC included in the X-decoder array X-DA may be located at different layers. It may be included in different memory blocks MBn-1, MBn, and MBn + 1.

22 is a schematic diagram illustrating a memory card according to an embodiment of the present invention.

Referring to FIG. 22, the memory card 2200 may include a controller 2210 and a memory unit 2220 in a housing 2230. The controller 2210 and the memory unit 2220 may exchange electrical signals. For example, according to a command of the controller 2210, the memory unit 2220 and the controller 2210 may exchange data. Accordingly, the memory card 2200 may store data in the memory unit 2220 or output data from the memory unit 2220 to the outside.

For example, the memory unit 2220 may include at least one of the stacked memory devices of FIGS. 1 to 21. The memory card 2200 may be used as a data storage medium of various portable devices. For example, the memory card 2200 may include a multi media card (MMC) or a secure digital (SD) card.

23 is a block diagram illustrating an electronic system according to an embodiment of the present invention.

Referring to FIG. 23, the electronic system 2300 may include a processor 2310, an input / output device 2330, and a memory unit 2320, which communicate data with each other using a bus 2340. can do. The processor 2310 may execute a program and control the electronic system 2300. The input / output device 2330 may be used to input or output data of the electronic system 2300. The electronic system 2300 may be connected to an external device, such as a personal computer or a network, by using the input / output device 2330 to exchange data with the external device. The memory unit 2320 may store code and data for operating the processor 2310. For example, the memory unit 2320 may include at least one of the stacked memory devices of FIGS. 1 to 21.

For example, such an electronic system 2300 may constitute various electronic control devices requiring a memory unit 2320, for example, a mobile phone, an MP3 player, navigation, a solid disk. state disk (SSD) or household appliances.

The foregoing description of specific embodiments of the invention has been presented for purposes of illustration and description. Therefore, the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit of the present invention in combination with the above embodiments. Do.

1, 2, 3, 4: stacked memory devices
110, 210, 310, 410: substrate
120, 220, 320, 420: memory layer
131, 132, 231, 232, 330, 430: X-decoder layer
141, 142, 143, 241, 242, 243, 340, 440: Y-decoder layer
MG: memory group
MB: block of memory

Claims (29)

Board;
A plurality of memory groups stacked on each other on the substrate and each including at least one memory layer;
A plurality of X-decoder layers interposed at least one layer across a plurality of adjacent two memory groups among the plurality of memory groups; And
And a plurality of Y-decoder layers interposed with the plurality of X-decoder layers by at least one layer across the plurality of adjacent two memory groups. The stacked memory device of claim 1, wherein at least one memory group of the plurality of memory groups is interposed between each X-decoder layer and each Y-decoder layer. The stacked memory device of claim 1, wherein each of the plurality of memory groups comprises an equal number of memory layers. The stacked memory device of claim 1, wherein the plurality of X-decoder layers and the plurality of Y-decoder layers are alternately arranged one by one between the plurality of adjacent two memory groups. 5. The stacked memory device of claim 4, wherein each X-decoder layer is coupled to two memory groups disposed above and below a corresponding X-decoder layer of the plurality of adjacent memory groups. 6. The stacked memory device of claim 5, wherein each of the Y-decoder layers is coupled to two memory groups disposed above and below a corresponding Y-decoder layer of the plurality of adjacent memory groups. 2. The apparatus of claim 1, wherein the plurality of Y-decoder layers comprises a plurality of pairs of a first Y-decoder layer and a second Y-decoder layer, each pair being arranged alternately with the plurality of X-decoder layers. The pair of first Y-decoder layers and the second Y-decoder layers are stacked adjacent to each other,
And the plurality of X-decoder layers are interposed one by one across the plurality of adjacent two memory groups. 8. The stacked memory device of claim 7, wherein each pair of first and second decoder layers is coupled to corresponding two memory groups of the plurality of adjacent memory groups, respectively. 8. The stacked memory device of claim 7, wherein each X-decoder layer is coupled to two adjacent memory groups disposed above and below the corresponding X-decoder layer among the plurality of adjacent memory groups. 2. The apparatus of claim 1, wherein the plurality of X-decoder layers comprises a plurality of pairs of first and second X-decoder layers, arranged in pairs staggered with the plurality of Y-decoder layers, respectively. The pair of first X-decoder layers and second X-decoder layers are stacked adjacent to each other,
And the plurality of Y-decoder layers are interposed one by one across the plurality of adjacent two memory groups. 11. The stacked memory device of claim 10, wherein each pair of first and second X-decoder layers is coupled to corresponding two memory groups of the plurality of adjacent two memory groups, respectively. 11. The stacked memory device of claim 10, wherein each Y-decoder layer is coupled to two adjacent memory groups disposed above and below a corresponding Y-decoder layer among the plurality of adjacent memory groups. The method of claim 1, wherein each X-decoder layer includes the same number of X-decoder pairs as the number of memory layers included in each memory group.
Wherein each Y-decoder layer includes the same number of pairs of Y-decoders as the number of memory layers included in each memory group. The method of claim 13,
Memory cells included in each memory layer are classified into a first group and a second group,
X-decoders included in each X-decoder pair are respectively connected to the first and second groups of corresponding memory layers,
The Y-decoders included in each Y-decoder pair are connected to the first and second groups of the corresponding memory layers, respectively. The method of claim 1, wherein each X-decoder layer includes the same number of X-decoders as the number of memory layers included in each memory group,
Wherein each Y-decoder layer includes the same number of Y-decoders as the number of memory layers included in each memory group. A plurality of stacked memory blocks arranged on a substrate, each stacked memory block,
A plurality of memory groups stacked on each other on the substrate and each including at least one memory layer;
A plurality of X-decoder arrays interspersed one by one in the plurality of memory groups; And
And a plurality of Y-decoder arrays interleaved with the plurality of X-decoder arrays one by one in the plurality of memory groups. 17. The stacked memory device of claim 16, wherein the plurality of X-decoder arrays of each stacked memory block are disposed at the same level as the plurality of Y-decoder arrays of the stacked memory block adjacent to the stacked memory block. 17. The memory device of claim 16, wherein each memory group is covalently coupled to at least one word line,
And each X-decoder array of each stacked memory block includes at least one X-decoder coupled to the at least one word line. 17. The memory device of claim 16, wherein each memory group is coupled to at least one pair of word lines,
Wherein each X-decoder array of each stacked memory block includes at least one pair of X-decoders coupled to the at least one pair of word lines. 17. The apparatus of claim 16, wherein each X-decoder array includes a number of pairs of X-decoders corresponding to half of the number of memory layers included in each memory group, each pair of X-decoder being in at least two memory layers. Connected in common,
Each Y-decoder array includes a number of Y-decoder pairs corresponding to half of the number of memory layers included in each memory group, and each Y-decoder pair is commonly connected to at least two memory layers. Multilayer memory device. The method of claim 20,
Memory cells included in each memory layer are classified into a first group and a second group,
X-decoders included in each X-decoder pair are respectively connected to the first and second groups of corresponding memory layers,
The Y-decoders included in each Y-decoder pair are connected to the first and second groups of the corresponding memory layers, respectively. 17. The apparatus of claim 16, wherein each X-decoder array comprises a number of X-decoders corresponding to half of the number of memory layers included in each memory group, each X-decoder being common to at least two memory layers. Connected,
Each Y-decoder array includes a number of Y-decoders corresponding to half of the number of memory layers included in each memory group, and each Y-decoder is connected to at least two memory layers in common. Stacked memory devices. Board;
A plurality of memory groups each including at least one memory layer and stacked on the substrate; And
At least one decoder layer in the plurality of memory groups, wherein the at least one decoder layer comprises:
An X-decoder array comprising at least one X-decoder; And
A Y-decoder array comprising at least one Y-decoder,
And the at least one X-decoder array and the at least one Y-decoder array in each decoder layer are arranged in a lattice form. The apparatus of claim 23, wherein the at least one X-decoder array comprises a plurality of X-decoder arrays,
And said at least one Y-decoder array comprises a plurality of Y-decoder arrays. 25. The stacked memory device of claim 24, wherein the plurality of X-decoder arrays and the plurality of Y-decoder arrays are alternately arranged. 24. The stacked memory device of claim 23, wherein the at least one decoder layer comprises a plurality of decoder layers in the plurality of memory groups. 27. The stacked memory device of claim 26, wherein the pair of decoder layers in adjacent memory groups of the plurality of decoder layers have decoder arrangements of opposite structures to each other. 27. The stacked memory device of claim 26, wherein the plurality of decoder layers alternately have two types of decoder arrangements opposite to each other. 24. The stacked memory device of claim 23, wherein each memory layer uses a variable resistor as a storage medium.

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