KR20100119164A - Erasing method of a non-volatile memory device - Google Patents

Abstract

PURPOSE: A method for erasing a nonvolatile memory device is provided to prevent a memory device from being damaged due to charges in a junction area by efficiently discharging the charges from the junction area. CONSTITUTION: A source selection transistor(SST) is connected to a common source line(CSL). A drain selection transistor(DST) is connected to a bit line(BL). A memory cell is serially connected between the source selection transistor and the drain selection transistor through a junction area(106). An erasing bias is applied to erase the memory cells. The charges is discharged from the junction area by the erasing bias.

Description

Erasing method of a non-volatile memory device

The present invention relates to a method of erasing a nonvolatile memory device, and more particularly, to a method of erasing a nonvolatile memory device capable of effectively releasing charges charged in a junction region.

Electrically erasable and programmable nonvolatile memory devices are capable of preserving data even when power is not supplied. In particular, since a NAND flash memory device has a string structure in which several memory cells are connected in series, not only is it easy to integrate, but it can also be supplied at a low price. For this reason, NAND flash memory devices are being used as data memories of various portable products.

The memory cells constituting the NAND flash memory device are programmed or erased by the F-N tunneling mechanism. The erase operation of the memory cell is performed by applying a ground voltage (for example, 0 V) to the control gate of the cell transistor and applying a high voltage (for example, 20 V) higher than the power supply voltage to the semiconductor substrate (or well). According to this erase bias condition, a strong electric field is formed between them due to the large voltage difference between the floating gate and the well, and as a result, electrons present in the floating gate are emitted in bulk by the F-N tunneling effect. At this time, the threshold voltage of the erased memory cell is moved in a negative direction (for example, -3V or less).

6 is a timing diagram illustrating a method of erasing a nonvolatile memory device according to the related art.

Referring to FIG. 6, when an erase voltage is applied to the semiconductor substrate and a ground voltage is applied to the memory cell, the junction region may be charged during the erase operation. Charged charges only delay the time that the channel voltage drops to 0V even when the well voltage drops to 0V at the end of the erase operation. In this process, the charges are generated near the edges of the tunnel oxide layer and the junction region due to hot carriers. It can damage the performance of the flash memory device.

The present invention electrically connects the junction regions with the ground terminal to discharge the charges charged in the junction regions of the memory cells after applying an erase bias to perform the erase operation of the memory cells.

According to an aspect of the present invention, a method of erasing a nonvolatile memory device includes a source select transistor connected to a common source line, a drain select transistor connected to a bit line, and a junction region between the source select transistor and the drain select transistor. A memory device comprising a series of memory cells connected in series is provided, applying an erase bias in bulk to perform an erase operation of the memory cells, and emitting charges charged in the junction region by the erase bias. Steps.

The gate bias applied to the drain select transistor may turn on the drain select transistor. The gate bias applied to the source select transistor may turn on the source select transistor. The gate bias applied to the memory cell may turn on the memory cell. Emitting the charges may include connecting the bit line with a ground terminal and applying gate biases to the drain select transistor and the memory cells, respectively, when stopping the erase bias and stopping the application of the erase bias. It may further comprise a step. The discharging of the other charges may include connecting the common source line with a ground terminal and applying a gate bias to the source select transistor and the memory cells, respectively, when stopping the erase bias, and applying the erase bias. It may further comprise the step of stopping.

According to another aspect of an exemplary embodiment, an erase method of a nonvolatile memory device may include performing an erase operation of memory cells and discharging charges charged in junction regions of the memory cells when the erase operation is terminated. Electrically connecting the junction regions with a ground terminal and disconnecting the electrical connection between the junction regions and the ground terminal.

The erase method of the nonvolatile memory device according to the present invention can effectively discharge the charges charged in the junction region during the erase operation, thereby preventing damage to the memory device due to the charges charged in the junction region. . Thus, the operation of a more reliable and high performance memory device is possible.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

FIG. 1 is a diagram of a nonvolatile memory device for explaining a method of programming a nonvolatile memory device according to an exemplary embodiment of the present invention. Hereinafter, a flash memory device among nonvolatile memory devices will be described as an example.

Referring to FIG. 1, a flash memory device includes a memory cell array 100. In the memory cell array 100, a plurality of memory cells capable of storing and erasing data are arranged in a matrix. The memory cell array 100 includes a plurality of bit lines BL and a plurality of word lines WL.

The word lines WL are selected by a row address decoded by the X decoder 400, and the selected word lines WL supply voltages from the voltage providing unit 500 for reading, programming or erasing. Receive. The bit lines BL transfer data programmed into the memory cells of the memory cell array 100 or data read from the memory cells.

The page buffer unit 200 connected to the bit lines BL transmits and receives data of the bit lines BL corresponding to the column address decoded by the Y decoder 300. The controller 600 generates control signals according to an external command with an appropriate voltage, and provides the control signals to the page buffer unit 200, the Y decoder 300, the X decoder 400, and the voltage providing unit 500. In addition, the controller 600 buffers an externally input address to a row address or a column address and provides the buffer to the X decoder 400 or the Y decoder 300.

2 is a diagram illustrating a unit cell array included in a memory cell array 100 of a flash memory device.

Referring to FIG. 2, a well 104 is disposed near the surface of the semiconductor substrate 102, and the well 104 has a source select transistor SST, a drain select transistor DST, a source select transistor SST, Memory cells MC0 to MC31 connected in series through the junction regions 106 are disposed between the drain select transistors DST. The source select transistor SST is connected to the common source line CSL and shares the source select line SSL. The drain select transistor DST is connected to the bit line BL to share the drain select line DSL. The memory cells MC0 to MC31 share a word line WL.

On the other hand, in the case of a flash memory device, if the semiconductor substrate 102 is a p-type substrate, n wells (not shown) are formed near the surface of the semiconductor substrate 102 and are included in the n wells (not shown). Place the well 104 as a p well. In this case, the junction region 106 may be formed of n-type impurities.

In an erase operation according to an exemplary embodiment, the first gate voltage V1 is applied to the memory cells MC0 to MC31 through corresponding word lines. In addition, the second gate voltage V2 is applied to the source select transistor SST through the source select line SSL. The third gate voltage V3 is applied to the drain select transistor DST through the drain select line DSL. Fourth and fifth voltages V4 and V5 may be applied to the common source line CSL and the bit line BL, respectively, and an erase voltage V6 may be applied to the well 106 through a well pickup contact plug. .

Hereinafter, a method of erasing a nonvolatile memory device according to the present invention will be described in the first to third embodiments.

3 is a timing diagram illustrating an erase method of a nonvolatile memory device according to a first embodiment of the present invention.

2 and 3, first, during a first period T1 during which an erase operation of the memory cells MC0 to MC31 is performed, an erase voltage V6 may be formed in a bulk through a well pickup contact plug connected to the well 104. The first gate voltage V1 is applied to the memory cells MC0 to MC31 through the word lines WL. The erase voltage V6 may be 20V and the first gate voltage V1 may be 0V.

At this time, since the well 104 includes p-type impurities and the junction region 106 includes n-type impurities, a PN junction is formed between the well 104 and the junction region 106. Accordingly, the channel voltage may increase while the voltage corresponding to the difference between the erase voltage V6 and the threshold voltage Vdth of the PN junction is applied to the junction region 106. As a result, charges may be charged in the junction region 106.

At the same time, the source select transistor SST and the drain select transistor DST remain in a floating state. In this case, the fourth voltage V4 of the common source line CSL and the fifth voltage V5 of the bit line BL may increase along the erase voltage V6 applied to the well 104.

During the second period T2 before the erase operation of the memory cells MC0 to MC31 is terminated, the first gate voltage V1 and the second gate voltage are respectively applied to the word line WL and the source select line SSL. (V2) is applied. The first gate voltage V1 and the second gate voltage V2 are voltages that can turn on the memory cells MC0 to MC31 and the source select transistor SST, respectively. For example, the first gate voltage V1 may be the sum of the erase voltage V6 and the threshold voltage Vcth of the memory cell, and the second gate voltage V2 may be the erase voltage V6 and the source select transistor SST. May be the sum of the threshold voltages Vsth.

Subsequently, during the third period T3 for discharging the charges charged in the junction region 106, the well 104 and the common source line CSL are connected to the ground terminal to apply a ground voltage (0V). In this case, since the memory cells MC0 to MC31 are all turned on to form a channel, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to each other. Similarly, since the source select transistor SST is turned on to form a channel, the junction regions 106 at both sides of the source select transistor SST may be electrically connected to each other. As a result, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to the common source line CSL to which the ground voltage 0V is applied. Accordingly, the charges charged in the junction regions 106 may be effectively discharged along the common source line CSL, and the channel voltage may drop in the same trend as the well 104 voltage drops.

Subsequently, during the fourth period T4 in which the erase operation of the memory cell is terminated, the first gate voltage V1 and the second gate voltage V2 are respectively applied to the word line WL and the source select line SSL. The application is interrupted to break the electrical connection to the ground terminal.

4 is a timing diagram illustrating an erase method of a nonvolatile memory device according to a second embodiment of the present invention.

2 and 4, first, during a first period T1 during which an erase operation of the memory cells MC0 to MC31 is performed, an erase voltage V6 is formed in a bulk through a well pickup contact plug connected to the well 104. The first gate voltage V1 is applied to the memory cells MC0 to MC31 through the word lines WL. The erase voltage V6 may be 20V and the first gate voltage V1 may be 0V.

At this time, since the well 104 includes p-type impurities and the junction region 106 includes n-type impurities, a PN junction is formed between the well 104 and the junction region 106. Accordingly, the channel voltage may increase while the voltage corresponding to the difference between the erase voltage V6 and the threshold voltage Vdth of the PN junction is applied to the junction region 106. As a result, charges may be charged in the junction region 106.

At the same time, the source select transistor SST and the drain select transistor DST remain in a floating state. In this case, the fourth voltage V4 of the common source line CSL and the fifth voltage V5 of the bit line BL may increase along the erase voltage V6 applied to the well 104.

During the second period T2 before the erase operation of the memory cells MC0 to MC31 is terminated, the first gate voltage V1 and the third gate voltage are respectively applied to the word line WL and the drain select line DSL. (V3) is applied. The first gate voltage V1 and the third gate voltage V3 are voltages that can turn on the memory cells MC0 to MC31 and the drain select transistor DST, respectively. For example, the first gate voltage V1 may be the sum of the erase voltage V6 and the threshold voltage Vcth of the memory cell, and the third gate voltage V3 may be the erase voltage V6 and the drain select transistor DST. May be the sum of the threshold voltages Vsth.

Subsequently, during the third period T3 for discharging the charges charged in the junction region 106, the well 104 and the bit line BL are connected to the ground terminal to apply the ground voltage 0V. In this case, since the memory cells MC0 to MC31 are all turned on to form a channel, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to each other. Similarly, since the drain select transistor DST is turned on to form a channel, the junction regions 106 at both sides of the drain select transistor DST may be electrically connected to each other. As a result, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to the bit line BL to which the ground voltage 0V is applied. Accordingly, the charges charged in the junction regions 106 may be effectively discharged along the bit line BL, and the channel voltage may drop in the same trend as the well 104 voltage drops.

Subsequently, the first gate voltage V1 and the third gate voltage V3 are applied to the word line WL and the drain select line DSL, respectively, during the fourth period T4 when the erase operation of the memory cell is terminated. Break the electrical connection to the ground terminal.

5 is a timing diagram illustrating a method of erasing a nonvolatile memory device according to a third embodiment of the present invention.

2 and 5, first, during a first period T1 during which an erase operation of the memory cells MC0 to MC31 is performed, an erase voltage V6 may be formed in a bulk through a well pickup contact plug connected to the well 104. Is applied, and the first gate voltage V1 is applied to the word lines WL. The erase voltage V6 may be 20V and the first gate voltage V1 may be 0V.

At this time, since the well 104 includes p-type impurities and the junction region 106 includes n-type impurities, a PN junction is formed between the well 104 and the junction region 106. Accordingly, the channel voltage may increase while the voltage corresponding to the difference between the erase voltage V6 and the threshold voltage Vdth of the PN junction is applied to the junction region 106. As a result, charges may be charged in the junction region 106.

At the same time, the source select transistor SST and the drain select transistor DST remain in a floating state. In this case, the fourth voltage V4 of the common source line CSL and the fifth voltage V5 of the bit line BL may increase along the erase voltage V6 applied to the well 104.

In addition, during the second period T2 before the erase operation of the memory cells MC0 to MC31 is terminated, the first gate voltages may be applied to the word line WL, the source select line SSL, and the drain select line DSL, respectively. V1), a second gate voltage V2, and a third gate voltage V3 are applied. The first gate voltage V1, the second gate voltage V2, and the third gate voltage V3 may turn on the memory cells MC0 to MC31, the source select transistor SST, and the drain select transistor DST, respectively. That is the voltage. For example, the first gate voltage V1 may be the sum of the erase voltage V6 and the threshold voltage Vcth of the memory cell, and the second gate voltage V2 may be the erase voltage V6 and the source select transistor SST. ) May be the sum of the threshold voltage Vsth, and the third gate voltage V3 may be the sum of the erase voltage V6 and the threshold voltage Vsth of the drain select transistor DST.

Subsequently, during the third period T3 for discharging the charges charged in the junction region 106, the well 104, the common source line CSL, and the bit line BL are connected to the ground terminal to connect the ground voltage (0V). ) Is applied. In this case, since the memory cells MC0 to MC31 are all turned on to form a channel, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to each other. Similarly, the source select transistor SST and the drain select transistor DST are also turned on to form a channel, so that the junction region 106 on both sides of the source select transistor SST and the junction region 106 on both sides of the drain select transistor DST are formed. Can be electrically connected. As a result, the junction regions 106 adjacent to the memory cells MC0 to MC31 may be electrically connected to the common source line CSL and the bit line BL to which the ground voltage 0V is applied. Accordingly, the charges charged in the junction regions 106 can be effectively discharged along the common source line CSL or the bit line BL, and the channel voltage decreases in the same trend as the well 104 voltage drops. Can be descended.

Subsequently, during the fourth period T4 when the erase operation of the memory cell is terminated, the first gate voltage V1 and the second are respectively applied to the word line WL, the source select line SSL, and the drain select line DSL. Application of the gate voltage V2 and the third gate voltage V3 is stopped to cut off the electrical connection of the ground terminal.

As described above, since the charges charged in the junction region may be effectively discharged during the erase operation, the memory device may be prevented from being damaged by the charges charged in the junction region.

FIG. 1 is a diagram of a nonvolatile memory device for explaining a method of programming a nonvolatile memory device according to an exemplary embodiment of the present invention.

2 is a diagram illustrating a unit cell array included in a memory cell array of a flash memory device.

3 is a timing diagram illustrating an erase method of a nonvolatile memory device according to a first embodiment of the present invention.

4 is a timing diagram illustrating an erase method of a nonvolatile memory device according to a second embodiment of the present invention.

5 is a timing diagram illustrating a method of erasing a nonvolatile memory device according to a third embodiment of the present invention.

Claims (7)

Providing a memory device including a source select transistor connected to a common source line, a drain select transistor connected to a bit line, and memory cells connected in series through junction regions between the source select transistor and the drain select transistor; Applying an erase bias in bulk to perform an erase operation of the memory cells; And And discharging charges charged in the junction region by the erase bias. The method of claim 1, And the gate bias applied to the drain select transistor can turn on the drain select transistor. The method of claim 1, And a gate bias applied to the source select transistor can turn on the source select transistor. The method of claim 1, And the gate bias applied to the memory cell can turn on the memory cell. The method of claim 1, wherein releasing the charges comprises: Connecting the bit line with a ground terminal and applying gate biases to the drain select transistor and the memory cells, respectively, when the erase bias is stopped; And And stopping the application of the erase bias. The method of claim 1, wherein releasing the charges comprises: Connecting the common source line with a ground terminal and applying a gate bias to the source select transistor and the memory cells, respectively, when the erase bias is stopped; And And stopping the application of the erase bias. Performing an erase operation on the memory cells; Electrically coupling the junction regions with a ground terminal to discharge the charges charged in the junction regions of the memory cells when the erase operation ends; And And disconnecting electrical connections between the junction regions and the ground terminal.

Images