KR20100116937A - Programming method of nonvolatile memory device - Google Patents

Abstract

PURPOSE: A method for programming a nonvolatile memory device is provided to prevent a non-selected memory cell from being programmed by increasing self-boosting efficiency in a program operation. CONSTITUTION: A memory cell array(110) is comprised of memory cells arranged in a matrix of a word line and a bit line. A control logic circuit(120) controls operations related to a program. A voltage generator(130) is controlled by a control logic circuit. A row decoder(140) is controlled by the control logic circuit. A page buffer(150) operates as a sensing amplifier or writing driver.

Description

PROGRAMMING METHOD OF NONVOLATILE MEMORY DEVICE

The present invention relates to a nonvolatile memory device, and more particularly, to a program method of a nonvolatile memory device.

There is an increasing demand for electrically erasable and programmable semiconductor memory devices that do not require refresh to maintain data. In addition, increasing the storage capacity of the semiconductor memory device is also required. Flash memory devices provide large storage capacity without refreshing. Since flash memory devices retain data even when power is cut off, they are widely used in electronic devices (eg, portable electronic devices) in which power may be cut off suddenly.

Flash memory devices, also known as flash electrically erasable programmable read only memory (EEPROM), comprise a memory cell array consisting of floating gate transistors. The memory cell array is divided into a plurality of memory blocks. A plurality of bit lines are arranged in parallel in the plurality of memory blocks. Each memory block is provided with a plurality of strings (or called "NAND strings") corresponding to the bit lines, respectively.

Each string includes a string select transistor (SST) and a ground select transistor (GST), and a plurality of floating gate transistors are connected between the string select transistor and the ground select transistor. Leads to. Each floating gate transistor shares an adjacent floating gate transistor with a source-drain terminal.

Each string is arranged such that a plurality of word lines cross each other. Control gates of the plurality of floating gate transistors are commonly connected to each word line.

In order to program memory cells consisting of floating gate transistors, the memory cells are first erased to have a predetermined threshold voltage (eg, -3V). Thereafter, a high voltage (for example, 20 V) is applied to a word line connected to the selected memory cell for a predetermined time to perform a program for the selected memory cell. The threshold voltage of the selected memory cell is high for accurate program operation, and the threshold voltages of the unselected memory cells should not be changed.

However, the program voltage applied to the selected word line is applied not only to the selected memory cell but also to the unselected memory cell connected to the selected word line. As a result, there may be a problem that an unselected memory cell connected to the selected word line is programmed. Unintended programs of unselected memory cells connected to selected word lines are called "program disturb". In particular, program disturb may be more problematic in a multi level cell to which a high program voltage is applied.

An object of the present invention is to provide a method of programming a nonvolatile memory device having improved reliability by preventing program disturb.

In the method of programming a nonvolatile memory device according to the present invention, the nonvolatile memory device may be configured to separate a memory cell string into a first region including a selection word line and a second region without the selection word line. And a word line, said program method comprising driving word lines in said first region at a first pass voltage and driving word lines in said second region at a second pass voltage higher than said first pass voltage; Turning off a cell transistor corresponding to the local word line after application of the first pass voltage and the second pass voltage; And after turning off the cell transistor, driving the selected word line to a program voltage.

The method may further include driving the non-selected word line or the selected word line in the first region to the second pass voltage after turning off the cell transistor. To turn off the cell transistor, a local voltage higher than the ground voltage and lower than the first pass voltage is applied to the local word line. Driving the unselected word lines in the first region to a voltage lower than the first pass voltage after the word lines in the first region are driven to the first pass voltage.

In the method of programming a nonvolatile memory device according to the present invention, the nonvolatile memory device may be configured to separate a memory cell string into a first region including a selection word line and a second region without the selection word line. And a word line, said program method comprising driving word lines in said first region at a first pass voltage and driving word lines in said second region at a second pass voltage higher than said first pass voltage; After application of the first pass voltage and the second pass voltage, each of the first local voltage and the second local line and the second local line included in the first region and adjacent to the first local word line Driving to a local voltage; And after applying the first local voltage and the second local voltage, driving the select word line to a program voltage.

The method may further include driving an unselected word line or the selected word line in the first region to the second pass voltage after the application of the first local voltage and the second local voltage. The cell transistor corresponding to the first local word line is turned off by applying to the second local voltage, and the level of the second local voltage is higher than the ground voltage and lower than the first local voltage. Driving the unselected word lines in the first region to a voltage lower than the first pass voltage after the word lines in the first region are driven to the first pass voltage.

According to the present invention, self-boosting efficiency is increased during a program operation, thereby preventing programming of unselected memory cells.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a nonvolatile memory device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein, and the present invention may also be implemented or applied through other embodiments. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention.

One technique for preventing program disturb is a program banning method using a self-boosting scheme. Program banning method using self-boosting scheme is described in U.S. Patent No. 5,677,873 entitled "METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN" and U.S. Patent No. 5,991,202, entitled " METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MMEORY ", incorporated by reference.

In a program prohibition method using a self-boosting scheme, the ground path is blocked by applying a voltage of 0V to the gate of the ground select transistor. A voltage of 0 V is applied to the selected bit line, and a power supply voltage Vcc is applied as a program inhibition voltage to the unselected bit line.

At the same time, after the source of the string select transistor is charged (Vcc-Vth, Vth is the threshold voltage of the string select transistor) by applying a power supply voltage Vcc to the gate of the string select transistor, the string select transistor is practically cut off (or , Shut off).

The channel voltage of the program inhibited cell transistor is then boosted by applying the program voltage Vpgm to the selected word line and the pass voltage Vpass to the unselected word lines. This avoids F-N tunneling between the floating gate and the channel, as a result of which the program inhibited cell transistor remains in an initial erase state.

Another technique is a program banning method using a local self-boosting scheme. Program banning using local self-boosting scheme is described in U.S. Patent No. 5,715,194 entitled "BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY" and U.S. Patent No. 6,061,270, entitled "METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL," incorporated by reference.

In the program prohibition method using a local self-boosting scheme, a voltage of 0V is applied to two unselected word lines adjacent to the selected word line. After the pass voltage Vpass is applied to other unselected word lines, for example, 10V, a program voltage Vpgm is applied to the selected word line.

Under this bias condition, the channel of the self-boosted cell transistor is limited to the selected word line and the channel boosting voltage of the program inhibited cell transistor is increased compared to the program inhibit method using the self-boosting scheme. Therefore, F-N tunneling does not occur between the floating gate and the channel of the program inhibited cell transistor, and as a result, the program inhibited cell transistor remains in an initial erase state.

1 is a block diagram illustrating a nonvolatile memory device according to the present invention. Referring to FIG. 1, a nonvolatile memory device 100 according to the present invention may include a memory cell array 110, a control logic circuit 120, a voltage generator 130, a row decoder 140, a page buffer 150, And a column decoder 160.

Although not shown in the drawing, the memory cell array 110 is composed of memory cells arranged in a matrix form of rows (or word lines) and columns (or bit lines). The memory cells may be arranged to have a NAND or NOR structure. In a NAND structure, each memory cell string includes transistors connected in series.

The control logic circuit 120 is configured to control the overall operation of the nonvolatile memory device 100. In an embodiment, the control logic circuit 120 controls a series of operations related to the program operation. For example, the control logic circuit 120 may be a state machine that stores program sequences. However, it will be apparent to those skilled in the art that the control logic circuit 120 is not limited to the disclosure herein. For example, the control logic circuit 120 may be configured to control an erase operation, a read operation, or the like of the nonvolatile memory device 100.

The voltage generator 130 is controlled by the control logic circuit 120 and includes a selected word line, an unselected word line, a string select line SSL, a ground select line GSL, Then, voltages applied to a common source line CSL are generated. In addition, the voltage generator 130 may generate a program voltage Vpgm, a pass voltage Vpass, a read voltage Vread, a verify read voltage Vvfy, and the like.

The row decoder 140 is controlled by the control logic circuit 120, and the selected word line and the unselected word lines, the string select line SSL, the ground select line GSL, in response to the row address, Each common source line CSL is driven.

The row decoder 140 drives the lines using the voltages generated by the voltage generator 130. For example, during a program operation, the row decoder 140 may apply a program voltage Vpgm to a selected word line and a pass voltage Vpass to an unselected word line.

The page buffer 150 operates as a sense amplifier or as a write driver. In a read operation, the page buffer 150 reads data from the memory cell array 110. In detail, the page buffer 150 senses the bit line voltage and distinguishes data according to the level of the bit line voltage. The distinguished data is stored in the page buffer 150.

In the program operation, the page buffer 150 drives the bit lines to the power supply voltage Vcc or the ground voltage 0V, respectively, according to the data input through the column decoder 160. For example, a ground voltage may be applied to a bit line connected to a memory cell to be programmed, and a power supply voltage may be applied to a bit line connected to a memory cell not to be programmed. The principle that the page buffer 150 operates as a sense amplifier or a write driver is well known to those skilled in the art to which the present invention pertains, and a description thereof will be omitted for the sake of brevity.

The column decoder 160 reads data latched in the page buffer 150 or transfers data to the page buffer 150 in response to a column address. For example, the column decoder 160 may receive data from an external device (eg, a host) during the program operation, and latch the input data in the page buffer 150.

FIG. 2 is a detailed view of the memory cell array shown in FIG. 1. Referring to FIG. 2, the memory cell array 110 includes a plurality of word lines WL1 to WLm, a plurality of bit lines BL1 to BLn, and a plurality of memory cells M1 to Mm. Word lines WL1 to WLm of the memory cell array 110 are connected to the row decoder 140.

The row decoder 140 includes a string select line SSL, word lines WL1 to WLm, and. It is connected to the ground select line GSL. The row decoder 140 may select one or more word lines among the plurality of word lines in correspondence with the row address, which is not shown.

The bit lines BL1 to BLn of the memory cell array 110 are connected to the page buffer 150. The page buffer 150 drives the bit lines BL1 to BLn. In an embodiment, during a program operation, the page buffer 150 applies a ground voltage (0V) to a selected bit line and applies a program prohibition voltage (Vcc) to an unselected bit line.

3 is a diagram for describing capacitances in a memory cell. Referring to FIG. 3, there is a tunnel oxide capacitance Ctun between the floating gate FG and the channel. An Oxide Nitride Oxide (ONO) capacitance Cono exists between the control gate CG and the floating gate FG. There is a depletion capacitance Cdep between the channel and the bulk (substrate, Si-Sub).

As the voltage is applied to the control gate CG, the channel voltage Vch rises due to the capacitances Cono, Cox, and Cdep. As a result, the memory cells connected to the unselected bit lines are not programmed. The channel voltage (Vch) must rise to a sufficient level for program prohibition.

However, as shown, the channel voltage Vch is inversely proportional to the depletion capacitance Cdep. That is, under constant voltage, when the depletion capacitance Cdep decreases, the channel voltage Vch increases. This can be explained by the law of charge conservation (Q = CV, Q is charge amount, C is capacitance, V is voltage). As a result, in order to increase the channel voltage Vch to a sufficient level, it is required to reduce the depletion capacitance Vdep.

However, the depletion capacitance Vdep is inversely proportional to the electron density Ech in the channel. In other words, when the electron density Ech in the channel is lowered, the depletion capacitance Vdep is increased. As a result, it is possible to increase the channel voltage Vch by lowering the electron density Ech in the channel.

In the present invention, the channel voltage Vch of the unselected string can be increased by lowering the channel electron density Ech of the unselected string. The channel electron density can be lowered by the movement of electrons. As the channel voltage Vch rises, program disturb due to the program voltage may be prevented. In particular, program disturb may be more problematic in a multi level cell to which a high program voltage is applied. As a result, the program method according to the present invention will have a great effect in multi-level cells.

4 is a view for explaining an electron movement method according to the present invention. In the present invention, electrons move by the voltage difference. The electrons move from the low voltage to the high voltage direction. Referring to FIG. 4A, as the voltage applied to the word line WL transitions from the low voltage Low to the high voltage High, electrons move in the direction of the word line WL. As the electrons move in the direction of the word line WL, the electron density of the channel corresponding to the word line WL will increase.

Referring to FIG. 4B, as the voltage applied to the word line WL transitions from the high voltage High to the low voltage Low, the electrons move away from the word line WL. As the electrons move away from the word line WL, the electron density of the channel corresponding to the word line WL will decrease. As described above, it is possible to control the movement of electrons by controlling the voltage applied to the word line WL.

5 is a view for explaining another embodiment of the electron movement method according to the present invention. In the present invention, electrons move by the voltage difference. The electrons move from the low voltage to the high voltage direction. Referring to FIG. 5A, bias voltages Vbias1 and Vbias2 having different magnitudes are applied to the first and second word lines WL1 and WL2 at the same potential. For example, the second bias voltage Vbias2 has a level higher than the first bias voltage Vbias1. As a result, the electrons move in the direction of the second word line WL2 to which the second bias voltage Vbias2 is applied. As the electrons move in the direction of the second word line WL2, the electron density of the channel corresponding to the first word line WL1 may decrease.

In addition, referring to FIG. 5B, bias voltages Vbias3 and Vbias4 having different magnitudes are applied to the first and second word lines WL1 and WL2 at the same potential. For example, the third bias voltage Vbias3 has a higher level than the fourth bias voltage Vbias4. As a result, the electrons move in the direction of the third word line WL3 to which the third bias voltage Vbias3 is applied. As the electrons move toward the third word line WL3, the electron density of the channel corresponding to the fourth word line WL4 may decrease.

As described above, electrons in the channel may be moved by applying different biases to the word lines. The movement of electrons changes the electron density. The boosting efficiency of channels with low electron density can be improved.

6 is a flowchart illustrating an electronic movement method during a program operation according to the present invention. Referring to FIG. 6, in step S110, electrons in a channel move according to a bias condition. As already described with reference to FIGS. 4 and 5, the electrons will move from the selection word line toward the source due to the voltage difference. The movement of electrons will change the electron density of the channel.

In step S120, the channel is separated. For example, the channels may be separated by transistors connected to local word lines. As the channels are separated, the channel containing the select word line will have a lower electron density. In operation S130, a program voltage is applied to the selected word line. The channel voltage corresponding to the select word line rises sufficiently because of the low electron density. As a result, the program is inhibited by the rise of the channel voltage.

As described above, the boosting efficiency may be improved by reducing the electron density of the channel including the selected word line. As the boosting efficiency improves, program disturb will be prevented.

Hereinafter, with reference to the drawings to be described below, embodiments of a program method according to the present invention will be described. However, the scope of the present invention is not limited to these embodiments. The main feature of the present invention is to increase the boosting efficiency by lowering the electron density in the channel. In particular, program disturb may be more problematic in a multi level cell to which a high program voltage is applied. A plurality of data may be stored in one multi-level cell. As a result, the program method according to the present invention will have a great effect in multi-level cells.

FIG. 7 is a diagram for describing a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention. Referring to FIG. 7, a case where the memory cell MC1 is programmed and the memory cell MC2 is not programmed will be described. The memory cell MC1 is connected to the selected word line WL28 and the selected bit line BL1. The memory cell MC2 is connected to the selected word line WL28 and the unselected bit line BL2.

When memory cell MC1 is programmed, memory cell MC2 should not be programmed. In order to prevent the memory cell MC2 from being programmed, the program inhibit voltage Vcc may be applied to the unselected bit line BL2.

In the present invention, a local self-boosting scheme is applied. In the program prohibition method according to the present invention, the ground voltage 0V is applied to the unselected word line WL24, thereby turning off the transistor connected to the unselected word line WL24. As the transistor is turned off, the channel is disconnected.

As a result, the channel is divided into a first area and a second area. As shown in FIG. 7, the selected word line WL28 is included in a first area. In the present embodiment, the unselected word line WL24 separating the channel may be referred to as a local word line.

In the present invention, pass voltages of different magnitudes are applied to the first area and the second area. For example, a first pass voltage may be applied to the first area, and a second pass voltage having a level higher than the first pass voltage may be applied to the second area. For example, the second pass voltage may be 9V and the first pass voltage may be 6V.

Since the magnitude of the pass voltage applied to the second area is relatively large, electrons in the first area can move to the second area. The movement of electrons lowers the electron density of the first area. As a result, the boosting efficiency of the channel voltage can be improved by the low electron density.

Program disturb may be prevented by improving the boosting efficiency of the channel voltage. In addition, since the magnitude of the pass voltage applied to the first area is relatively small, deterioration of the transistor insulating film due to the pass voltage can be minimized.

However, the scope of the present invention is not limited to the bias condition mentioned above. For example, a word line may not be interposed between the selected word line WL28 and the word line WL24, or conversely, a plurality of word lines may be included between the selected word line WL28 and the word line WL24. Even in this case, the boosting efficiency can be improved because the channels are separated.

In addition, although 32 word lines WL1 to WL32 are illustrated in the present exemplary embodiment, the scope of the present invention is not limited thereto, and it will be apparent to those skilled in the art. For example, 64 or 128 word lines can be applied to the present invention.

8 is a timing diagram for explaining a bias condition in the program method according to the present invention. Referring to FIG. 8, the program method according to the present invention is divided into steps t1 to t6. The t1 stage is an initialization stage, and a ground voltage (0V) is applied to each of the lines.

In step t2, the word lines WL24 to WL32 belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines WL1 to WL23 belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 5 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, the transistor insulating film degradation in the first area will be reduced.

In step t3, the ground voltage 0V is applied to the word line WL24. In response to the application of the ground voltage 0V, the transistor connected to the word line WL24 may be turned off. The channel will disconnect as the transistor is turned off. However, the scope of the present invention is not limited to this. For example, the voltage applied to the word line WL24 may be any voltage for turning off the transistor as well as the ground voltage 0V.

In step t4, the unselected word lines WL25 to WL27 & WL29 to WL32 and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t5, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t6 is a recovery step, in which each word line is driven to the ground voltage (0V).

However, the scope of the present invention is not limited to the bias condition mentioned above. It is a feature of the present invention to shift the charge in the channel by varying the magnitude of the pass voltages applied to each of the first and second areas. Accordingly, the bias condition for other operations may be performed in different cases depending on the case.

FIG. 9 is a diagram for describing an electron distribution in a channel in a period t1 to t3 of FIG. 8. FIG. 9A shows the electron distribution in the channel in the t1 section of FIG. 8 (t = t1). Referring to FIG. 9A, when the ground voltage 0V is applied to the word lines WL1 to WL32, electrons in the channel are arranged at a constant density. For simplicity, only four word lines WL23, WL24, WL25, and WL28 are shown in the figure.

FIG. 9B shows the electron distribution in the channel in the t2 section of FIG. 8 (t = t2). Referring to FIG. 9B, a second pass voltage Vpass2 that is relatively high is applied to the word line WL23, and a first pass voltage Vpass1 that is relatively low is applied to the word lines WL24 to WL32. As the electrons move, they move in the direction of the word line WL23.

Thus, the channel electron density in the first area is lowered and the channel electron density in the second area is higher. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since a relatively low first pass voltage Vpass1 is applied to the word lines WL24 to WL32 in the first area, deterioration of the transistor insulating layer may be reduced.

FIG. 9C shows the electron distribution in the channel in the t3 section of FIG. 8 (t = t3). Referring to FIG. 9C, as the ground voltage 0V is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel in the first area is lowered. As the electron density of the channel decreases, the boosting efficiency of the channel voltage increases. That is, in the present invention, by lowering the electron density of the channel corresponding to the selected word line, the self boosting efficiency will be improved.

10 is a view for explaining channel separation in the program method according to the present invention. Referring to FIG. 10, the channel is separated as the transistor MC3 is turned off. By the movement of the electrons described with reference to FIG. 9, the channel corresponding to the selected word line has a low electron density, and the channel not corresponding to the selected word line has a high electron density. Have Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

11 is a timing diagram illustrating a program method of a nonvolatile memory device according to a second embodiment of the present invention. Referring to FIG. 11, the program method according to the present invention is divided into t1 to t6 steps. The t1 stage is an initialization stage, and a ground voltage (0V) is applied to each of the lines.

In step t2, the word lines belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 8 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, deterioration of the transistor insulating layer in the first area will be reduced.

In step t3, the local voltage Vlocal is applied to the word line WL24. The local voltage Vlocal may have a level higher than the ground voltage 0V and lower than the first pass voltage Vpass1. The magnitude of the local voltage Vlocal is set to turn off the transistor connected to the word line WL24. In response to the application of the local voltage Vlocal, the transistor connected to the word line WL24 may be turned off. Thus, the channel will be separated.

In addition, by applying the first pass voltage Vpass1 to the unselected word lines WL25, WL26, and WL27, and applying a local voltage to the unselected word lines WL24, the channel voltage is prevented from rapidly changing. In other words, the spacing between the selected word line WL28 and the word line WL24 may be prevented due to a sudden boost of the channel voltage.

For example, when the channel voltage rises rapidly, a problem such as a band to band tuning (BTBT) phenomenon may occur in the transistor MC3 separating the channel. The BTBT phenomenon should be avoided because it will program unselected transistors.

However, the scope of the present invention is not limited to the bias condition. For example, there may be no space between the selected word line WL28 and the word line WL24, or a plurality of word lines may be included between the selected word line WL28 and the word line WL24. Even in this case, the boosting efficiency can be improved because the channels are separated.

In step t4, the unselected word lines WL25 to WL27 & WL29 to WL32 and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t5, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t6 is a recovery step, in which each word line is driven to the ground voltage (0V).

FIG. 12 is a diagram for describing an electron distribution in a channel in a section t1 to t3 of FIG. 11. FIG. 12A shows the electron distribution in the channel in the t1 section of FIG. 7 (t = t1). Referring to FIG. 12A, when the ground voltage 0V is applied to the word lines WL1 to WL32, electrons in the channel are arranged at a constant density.

FIG. 12B shows the electron distribution in the channel in the t2 section of FIG. 11 (t = t2). Referring to FIG. 12B, the second pass voltage Vpass2 that is relatively high is applied to the word lines WL1 to WL23, and the first pass voltage Vpass1 that is relatively low to the word lines WL24 to WL32. Is applied, the electrons move in the direction of the word line WL23.

Thus, the channel in the first area has a low electron density and the channel in the second area has a high electron density. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since the first pass voltage Vpass1, which is relatively low, is applied to the word line in the first area, deterioration of the transistor insulating layer may be reduced.

FIG. 12C shows the electron distribution in the channel in the t3 section of FIG. 11 (t = t3). Referring to FIG. 12C, as the local voltage Vlocal is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel in the first area is lowered. If the electron density of the channel is low, the boosting efficiency of the channel voltage increases. In the present invention, the self-boosting efficiency can be improved by lowering the electron density of the channel corresponding to the selected word line.

FIG. 13 is a diagram for describing channel separation in a program method according to a second exemplary embodiment of the present invention. Referring to FIG. 13, the channel is separated as the transistor MC3 is turned off. Due to the movement of electrons already described with reference to FIG. 12, the channel corresponding to the selected word line has a low electron density, and the channel not corresponding to the selected word line has a high electron density. Has Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

14 is a timing diagram illustrating a program method of a nonvolatile memory device according to a third embodiment of the present invention. Referring to FIG. 14, the program method according to the present invention is divided into t1 to t7 steps. The t1 step is an initialization step, and the ground voltage 0V is applied to each of the word lines WL1 to WL32.

In step t2, the word lines belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2. The level of the second pass voltage Vpass2 may be higher than the first pass voltage Vpass1.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 11 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, transistor degradation in the first area will be reduced.

In step t3, the word lines of the first area are driven to the ground voltage (0V). As the word lines of the first area are driven to the ground voltage (0V), the channel voltage in the second area becomes relatively higher than the voltage in the first area. This difference in voltage will cause electrons in the first area to move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of the transistor insulating layers respectively connected to the word lines may be prevented.

In step t4, the ground voltage 0V is applied to the word line WL24. In response to the application of the ground voltage 0V, the transistor connected to the word line WL24 may be turned off. The channel will disconnect as the transistor is turned off.

In step t5, the unselected word lines and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t6, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t7 is a recovery step, in which each word line is driven to the ground voltage (0V).

FIG. 15 is a diagram for describing an electron distribution in a channel in a period t1 to t4 in FIG. 14. FIG. 15A shows the electron distribution in the channel in the t1 section of FIG. 14 (t = t1). Referring to FIG. 15A, when the ground voltage 0V is applied to the word lines WL1 to WL32, electrons in the channel are arranged at a constant density.

FIG. 15B shows the electron distribution in the channel in the t2 section of FIG. 14 (t = t2). Referring to FIG. 15B, the second pass voltage Vpass2 that is relatively high is applied to the word lines WL1 to WL23, and the first pass voltage Vpass1 that is relatively low to the word lines WL24 to WL32. Is applied, the electrons move in the direction of the word line WL23.

Thus, the channel in the first area has a low electron density and the channel in the second area has a high electron density. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since a relatively low first pass voltage Vpass1 is applied to the word line in the first area, deterioration of the transistor insulating layer may be reduced.

FIG. 15C shows the electron distribution in the channel in the t3 section of FIG. 14 (t = t3). Referring to FIG. 15C, as the ground voltage 0V is applied to the word lines WL25 to WL27 and WL29 to WL32, the channel voltage corresponding to the word lines WL25 to WL27 and WL29 to WL32 is lowered. As the channel voltage decreases, electrons in the first area move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines WL25 to WL27 & WL29 to WL32 of the first area are driven to the ground voltage 0V lower than the pass voltage, transistor lead films respectively connected to the word lines WL25 to WL27 & WL29 to WL32. Deterioration of these can be prevented.

FIG. 15D shows the electron distribution in the channel in the t4 section of FIG. 14 (t = t4). Referring to FIG. 15D, when the ground voltage 0V is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel in the first area is lowered. If the electron density of the channel is low, the boosting efficiency of the channel voltage increases. In the present invention, the self boosting efficiency is improved by lowering the electron density of the channel corresponding to the selected word line.

16 is a diagram for describing channel separation in a program method according to a third embodiment of the present invention. Referring to FIG. 16, the channel is separated as the transistor MC3 is turned off. Due to the movement of electrons already described with reference to FIG. 15, the channel corresponding to the selected word line has a low electron density, and the channel corresponding to the selected word line has a high electron density. Has Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

17 is a timing diagram illustrating a program method of a nonvolatile memory device according to a fourth embodiment of the present invention. Referring to FIG. 17, the program method according to the present invention is divided into t1 to t7 steps. The t1 stage is an initialization stage, and the ground voltage 0V is applied to each of the word lines WL1 to WL32.

In step t2, the word lines WL24 to WL32 belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines WL1 to WL23 belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2. The level of the second pass voltage Vpass2 may be higher than the first pass voltage Vpass1.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 11 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, deterioration of the transistor insulating layer in the first area will be reduced.

In step t3, the word lines of the first area are driven to the ground voltage (0V). As the word lines of the first area are driven to the ground voltage 0V, the channel voltage in the second area becomes higher than the voltage in the first area.

This difference in voltage will cause electrons in the first area to move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

In step t4, the local voltage Vlocal is applied to the word line WL24. The local voltage Vlocal has a level higher than the ground voltage 0V and lower than the first pass voltage Vpass1. The local voltage Vlocal is set to turn off the transistor connected to the word line WL24. In response to the application of the local voltage Vlocal, the transistor connected to the word line WL24 will be turned off. Thus, the channel will be separated.

In addition, the local voltage Vlocal is applied to the unselected word line WL24 to prevent the channel voltage from changing rapidly. However, the scope of the present invention is not limited to the above bias conditions. For example, there may be no space between the selected word line WL28 and the word line WL24, or a plurality of word lines may be included between the selected word line WL28 and the word line WL24. Even in this case, the boosting efficiency is improved because the channels are separated.

In step t5, the unselected word lines and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t6, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t7 is a recovery step, in which each word line is driven to the ground voltage (0V).

FIG. 18 is a diagram for describing an electron distribution in a channel in a section t1 to t4 of FIG. 17. FIG. 18A shows the electron distribution in the channel in the t1 section of FIG. 17 (t = t1). Referring to FIG. 18A, when the ground voltage 0V is applied to the word lines WL1 to WL32, electrons in the channel are arranged at a constant density.

FIG. 18B shows the electron distribution in the channel in the t2 section of FIG. 17 (t = t2). Referring to FIG. 18B, the second pass voltage Vpass2 that is relatively high is applied to the word lines WL1 to WL23, and the first pass voltage Vpass1 that is relatively low to the word lines WL24 to WL32. As this is applied, electrons move in the direction of word line WL23.

As the electrons move, the channel in the first area has a low electron density, and the channel in the second area has a high electron density. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since a relatively low first pass voltage Vpass1 is applied to the word line in the first area, deterioration of the transistor insulating layer may be reduced.

FIG. 18C shows the electron distribution in the channel in the t3 section of FIG. 17 (t = t3). Referring to FIG. 18C, as the ground voltage 0V is applied to the word lines WL25 to WL27 & WL29 to WL32, the channel voltage corresponding to the word lines WL25 to WL27 & WL29 to WL32 is lowered. As the channel voltage decreases, electrons in the first area move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

FIG. 18 (d) shows the electron distribution in the channel in the t4 section of FIG. 17. Referring to FIG. 18D, as the local voltage Vlocal is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected.

The above-mentioned movement of electrons lowers the electron density of the channel in the first area. If the electron density of the channel is low, the boosting efficiency of the channel voltage increases. In the present invention, the self boosting efficiency is improved by lowering the electron density of the channel corresponding to the selected word line. In addition, a sudden change in the channel voltage is prevented by applying the local voltage Vlocal to the unselected word line WL24.

19 is a diagram for describing channel separation in a program method according to a fourth embodiment of the present invention. Referring to FIG. 19, the channel is separated as the transistor MC3 is turned off. By the movement of electrons described with reference to FIG. 18, the channel corresponding to the selected word line has a low electron density, and the channel not corresponding to the selected word line has a high electron density. Have Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

20 is a timing diagram illustrating a program method of a nonvolatile memory device according to a fifth embodiment of the present invention. 20, the program method according to the present invention is divided into steps t1 to t7. The t1 stage is an initialization stage. Each of the word lines WL1 to WL32 is driven to the ground voltage 0V.

In step t2, the word lines WL24 to WL32 belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2. The level of the second pass voltage Vpass2 may be higher than the first pass voltage Vpass1.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 17 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, deterioration of the transistor insulating layer in the first area will be reduced.

In step t3, the word lines of the first area are driven to the ground voltage (0V). As the word lines of the first area are driven to the ground voltage (0V), the channel voltage in the second area becomes relatively higher than the voltage in the first area. This difference in voltage will cause electrons in the first area to move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

In step t4, the first local voltage Vlocal1 is applied to the word line WL25, and the second local voltage Vlocal2 is applied to the word line WL24. The first local voltage Vlocal1 may have a level higher than the second local voltage Vlocal2.

In this embodiment, the channel voltage is prevented from changing rapidly by applying the first local voltage Vlocal1 and the second local voltage Vlocal2 to the unselected word lines WL25 and WL24, respectively. In addition, a spacing between the selected word line WL26 and the word lines WL25 and WL24 may prevent a problem due to a sudden boost of the channel voltage.

However, the scope of the present invention is not limited to the bias condition mentioned above. For example, there may be no space between the selected word line WL28 and the word lines WL25 and WL24, or a plurality of word lines may be included between the selected word line WL28 and the word lines WL25 and WL24. have.

In step t5, the unselected word lines and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t6, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t7 is a recovery step, in which each word line is driven to the ground voltage (0V).

FIG. 21 is a diagram for describing an electron distribution in a channel in a period t1 to t4 of FIG. 20. FIG. 21A shows the electron distribution in the channel in the t1 section of FIG. 20 (t = t1). Referring to FIG. 21A, when the ground voltage 0V is applied to the word lines WL1 to WL32, electrons in the channel are constantly arranged.

FIG. 21B shows the electron distribution in the channel in the t2 section of FIG. 20 (t = t2). Referring to FIG. 21B, a second pass voltage Vpass2 that is relatively high is applied to the word lines WL1 to WL23, and a first pass voltage Vpass1 that is relatively low to the word lines WL24 to WL32. As this is applied, the electrons move in the direction of the word line WL23 (ie, in the direction of the second area).

Thus, the channel in the first area has a low electron density and the channel in the second area has a high electron density. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since a relatively low first pass voltage Vpass1 is applied to the word line in the first area, deterioration of the transistor insulating layer may be reduced.

FIG. 21C shows the electron distribution in the channel in the t3 section of FIG. 20 (t = t3). Referring to FIG. 21C, as the word lines WL26 to WL27 and WL29 to WL32 are driven to the ground voltage 0V, a channel voltage corresponding to the word lines WL26 to WL27 and WL29 to WL32 is lowered. . As the channel voltage decreases, electrons in the first area move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

FIG. 21 (d) shows the electron distribution in the channel in the t4 section of FIG. 20 (t = t4). Referring to FIG. 21D, as the second local voltage Vlocal2 is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel in the first area is lowered. As the electron density of the channel decreases, the boosting efficiency of the channel voltage increases. In the present invention, the self boosting efficiency is improved by lowering the electron density of the channel corresponding to the selected word line. In addition, a sudden change in the channel voltage is prevented by applying the first local voltage Vlocal1 to the unselected word line WL25.

22 is a diagram for describing channel separation in a program method according to a fifth embodiment of the present invention. Referring to FIG. 22, the channel is separated as the transistor MC3 is turned off. By the movement of the electrons described with reference to FIG. 21, the channel corresponding to the selected word line has a low electron density, and the channel not corresponding to the selected word line has a high electron density. Have Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

FIG. 23 is a timing diagram illustrating a program method of a nonvolatile memory device according to a sixth embodiment of the present invention. Referring to FIG. 23, a program method according to the present invention is divided into t1 to t8 steps. The t1 stage is an initialization stage. Each of the word lines WL1 to WL32 is driven to the ground voltage 0V.

In step t2, the word lines WL24 to WL32 belonging to the first area are driven with the first pass voltage Vpass1. Transistors included in the first area may be turned on by applying the first pass voltage Vpass1. In addition, the word lines WL1 to WL23 belonging to the second area are driven by the second pass voltage Vpass2. Transistors included in the second area may be turned on by applying the second pass voltage Vpass2. The level of the second pass voltage Vpass2 may be higher than the first pass voltage Vpass1.

As the word lines belonging to the first area and the word lines belonging to the second area are driven by the first pass voltage Vpass1 and the second pass voltage Vpass2, electrons in the channel move. will be. This will be described in detail with reference to FIG. 20 to be described later. In addition, as the first area is driven with the first pass voltage Vpass1 lower than the second pass voltage Vpass2, deterioration of the transistor insulating layer in the first area will be reduced.

In step t3, the word lines WL26 to WL27 and WL29 to WL32 of the first area are driven to the ground voltage 0V. As the word lines WL26 to WL27 and WL29 to WL32 in the first area are driven to the ground voltage 0V, the channel voltage in the second area is the voltage in the first area. More relatively.

This difference in voltage will cause electrons in the first area to move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

In step t4, the word line WL25 is driven with the ground voltage 0V, and the second local voltage Vlocal2 is applied to the word line WL24. Therefore, the channel voltage corresponding to the word line WL24 is relatively higher than the channel voltage corresponding to the word line WL25. Due to this difference in channel voltage, electrons in the first area move to the second area.

In step t5, the word line WL25 is driven to the first local voltage Vlocal1. The first local voltage Vlocal1 has a higher level than the second local voltage Vlocal2.

In the present embodiment, the unselected word lines WL25 and WL24 are driven to the first local voltage Vlocal1 and the second local voltage Vlocal2, respectively, thereby preventing the channel voltage from changing drastically. In addition, the spacing between the selected word line WL28 and the word lines WL25 and WL24 may prevent a problem due to a sudden boost of the channel voltage.

However, the scope of the present invention is not limited to the bias condition mentioned above. For example, there may be no space between the selected word line WL28 and the word line WL25, or a plurality of word lines may be included between the selected word line WL28 and the word line WL25.

In step t6, the unselected word lines and the selected word line WL28 in the first area are driven with the second pass voltage Vpass2. By applying the second pass voltage Vpass2, the channel voltage of the first area will increase.

In step t7, the selected word line WL28 is driven by the program voltage Vpgm. The channel voltage of the first area will increase by the application of the program voltage Vpgm. The memory cell MC2 unselected by the elevated channel voltage will not be programmed. Step t8 is a recovery step, in which each word line is driven to the ground voltage (0V).

FIG. 24 is a diagram for describing an electron distribution in a channel in the sections t1 to t5 of FIG. 23. FIG. 24A shows the electron distribution in the channel in the t1 section of FIG. 19 (t = t1). Referring to FIG. 24A, when the ground voltage 0V is applied to the word lines WL1 to WL26, electrons in the channel are arranged at a constant density.

FIG. 24B shows the electron distribution in the channel in the t2 section of FIG. 23 (t = t2). Referring to FIG. 20B, the second pass voltage Vpass2 that is relatively high is applied to the word lines WL1 to WL23, and the first pass voltage Vpass1 that is relatively low to the word lines WL24 to WL32. As this is applied, the electrons move in the direction of the word line WL23 (ie, the direction of the second region).

As the electrons move, the channel in the first area has a low electron density, and the channel in the second area has a high electron density. The first area with low electron density has improved boosting efficiency. As a result, program disturb can be prevented. In addition, since a relatively low first pass voltage Vpass1 is applied to the word line in the first area, deterioration of the transistor may be reduced.

FIG. 24C shows the electron distribution in the channel in the t3 section of FIG. 23 (t = t3). Referring to FIG. 24C, as the ground voltage 0V is applied to the word lines WL26 to WL27 and WL29 to WL32, the channel voltage corresponding to the word lines WL26 to WL27 and WL29 to WL32 is lowered. . As the channel voltage decreases, electrons in the first area move to the second area. Thus, the electron density in the first area is reduced. In addition, as the word lines of the first area are driven to the ground voltage 0V lower than the pass voltage, deterioration of transistors respectively connected to the word lines may be prevented.

FIG. 24 (d) shows the electron distribution in the channel in the t4 section of FIG. 23 (t = t4). Referring to FIG. 24D, as the word line WL25 is driven with the ground voltage 0V, electrons in the first area move to the second area. In addition, as the second local voltage Vlocal2 is applied to the word line WL24, the transistor connected to the word line WL24 is turned off. As the transistor is turned off, the channel is disconnected. As a result, the electron density of the channel in the first area is lowered. As the electron density of the channel decreases, the boosting efficiency of the channel voltage increases. In the present invention, the self boosting efficiency is improved by lowering the electron density of the channel corresponding to the selected word line.

FIG. 24E shows the electron distribution in the channel in the t5 section of FIG. 23 (t = t5). Referring to FIG. 24E, the first local voltage Vlocal1 is applied to the word line WL25. In this embodiment, the channel voltage is prevented from changing rapidly by applying the first local voltage Vlocal1 and the second local voltage Vlocal2 to the unselected word lines WL25 and WL24, respectively. In addition, the spacing between the selected word line WL28 and the word lines WL25 and WL24 may prevent a problem due to a sudden boost of the channel voltage.

25 is a diagram for describing channel separation in a program method according to a sixth embodiment of the present invention. Referring to FIG. 25, the channel is separated as the transistor MC3 is turned off. Due to the movement of electrons already described with reference to FIG. 24, the channel corresponding to the selected word line has a low electron density, and the channel corresponding to the selected word line has a high electron density. Has Since the channel corresponding to the selected word line has a low electron density, the boosting efficiency of the channel voltage is improved. As a result, program disturb can be prevented by boosting the channel voltage.

In particular, program disturb may be more problematic in a multi level cell to which a high program voltage is applied. This is because the program voltage range of the multi-level cell is wider than that of the single-level cell. As a result, the program method according to the present invention will have a great effect in multi-level cells.

26 is a block diagram schematically illustrating a computing system 200 including a nonvolatile memory device according to the present invention. Referring to FIG. 26, the computing system 200 includes a processor 210, a memory controller 220, input devices 230, output devices 240, a nonvolatile memory device 250, and a main memory device. 260. Solid lines in the figures represent the system bus through which data or commands travel.

The memory controller 220 and the nonvolatile memory device 250 may constitute a memory card. In addition, the processor 210, the input devices 230, the output devices 240, and the main memory device 260 may configure a host that uses a memory card as a storage device.

The computing system 200 according to the present invention receives data from the outside through the input devices 230 (keyboard, camera, etc.). The input data may be a command by a user or multimedia data such as image data by a camera or the like. The input data is stored in the nonvolatile memory device 250 or the main memory device 260.

The processing result by the processor 210 is stored in the nonvolatile memory device 250 or the main memory device 260. The output devices 240 output data stored in the nonvolatile memory device 250 or the main memory device 260. The output devices 240 output digital data in a form that can be detected by a human. For example, the output device 240 includes a display or a speaker. The program method according to the present invention will be applied to the nonvolatile memory device 250. As the reliability of the nonvolatile memory device 250 is improved, the reliability of the computing system 200 will be proportionally improved.

The nonvolatile memory device 250 and / or the memory controller 220 may be mounted using various types of packages. For example, the nonvolatile memory device 250 and / or the controller 220 may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual. In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) , Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) ), Such as Wafer-Level Processed Stack Package (WSP).

Although not shown in the drawings, it is apparent to those skilled in the art that a power supply for supplying power for the operation of the computing system 200 is required. In addition, when the computing system 200 is a mobile device, a battery for supplying operating power of the computing system 200 may be additionally required.

27 is a block diagram schematically illustrating a configuration of an SSD system including a nonvolatile memory device according to the present invention. Referring to FIG. 27, the SSD system 300 includes an SSD controller 310 and nonvolatile memory devices 320 to 323.

The nonvolatile memory device according to the present invention may be applied to a solid state drive (SSD). SSD products, which are expected to replace hard disk drives (HDDs), are in the spotlight in the next-generation memory market. An SSD is a data storage device that uses memory chips such as flash memory to store data instead of a rotating dish used in a typical hard disk drive. SSDs have the advantages of being faster, resistant to external shocks, and lowering power consumption compared to mechanically moving hard disk drives.

Referring back to FIG. 27, the CPU 311 receives a command from the host and determines whether to store data from the host in the nonvolatile memory device or read data stored in the nonvolatile memory device and transmit the data to the host. And control.

The ATA interface 312 exchanges data with the host side under the control of the CPU 311 described above. The ATA interface 312 fetches commands and addresses from the host side and delivers them to the CPU 311 via the CPU bus. Data input from the host through the ATA interface 312 or data to be transmitted to the host are transferred through the SRAM cache 313 without passing through the CPU bus under the control of the CPU 311. The ATA interface 212 includes a serial ATA (S-ATA) standard and a parallel ATA (P-ATA) standard.

The SRAM cache 313 temporarily stores movement data between the host and the nonvolatile memory devices 320 to 323. The SRAM cache 313 is also used to store a program to be operated by the central processing unit 311. The SRAM cache 313 may be regarded as a kind of buffer memory, and may not necessarily be configured as SRAM. The flash interface 314 exchanges data with nonvolatile memories used as storage devices. The flash interface 314 may be configured to support NAND flash memory, One-NAND flash memory, or multi-level flash memory.

The semiconductor memory system according to the present invention can be used as a removable storage device. Therefore, it can be used as a storage device of MP3, digital camera, PDA, e-Book. It can also be used as a storage device such as a digital TV or a computer.

It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 is a block diagram illustrating a nonvolatile memory device according to the present invention.

FIG. 2 is a detailed view of the memory cell array shown in FIG. 1.

3 is a diagram for describing capacitances in a memory cell.

4 is a view for explaining an electron movement method according to the present invention.

5 is a view for explaining another embodiment of the electron movement method according to the present invention.

6 is a flowchart illustrating an electronic movement method during a program operation according to the present invention.

FIG. 7 is a diagram for describing a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

8 is a timing diagram for explaining a bias condition in the program method according to the present invention.

FIG. 9 is a diagram for describing an electron distribution in a channel in a period t1 to t3 of FIG. 4.

10 is a view for explaining channel separation in the program method according to the present invention.

11 is a timing diagram illustrating a program method of a nonvolatile memory device according to a second embodiment of the present invention.

FIG. 12 is a diagram for describing an electron distribution in a channel in a section t1 to t3 of FIG. 11.

FIG. 13 is a diagram for describing channel separation in a program method according to a second exemplary embodiment of the present invention.

14 is a timing diagram illustrating a program method of a nonvolatile memory device according to a third embodiment of the present invention.

FIG. 15 is a diagram for describing an electron distribution in a channel in a period t1 to t4 in FIG. 14.

16 is a diagram for describing channel separation in a program method according to a third embodiment of the present invention.

17 is a timing diagram illustrating a program method of a nonvolatile memory device according to a fourth embodiment of the present invention.

FIG. 18 is a diagram for describing an electron distribution in a channel in a section t1 to t4 of FIG. 17.

19 is a diagram for describing channel separation in a program method according to a fourth embodiment of the present invention.

20 is a timing diagram illustrating a program method of a nonvolatile memory device according to a fifth embodiment of the present invention.

FIG. 21 is a diagram for describing an electron distribution in a channel in a section t1 to t4 of FIG. 20.

22 is a diagram for describing channel separation in a program method according to a fifth embodiment of the present invention.

FIG. 23 is a timing diagram illustrating a program method of a nonvolatile memory device according to a sixth embodiment of the present invention.

FIG. 24 is a diagram for describing an electron distribution in a channel in the sections t1 to t5 of FIG. 23.

25 is a diagram for describing channel separation in a program method according to a sixth embodiment of the present invention.

26 is a block diagram schematically illustrating a computing system including a nonvolatile memory device according to the present invention.

27 is a block diagram schematically illustrating a configuration of an SSD system including a nonvolatile memory device according to the present invention.

Claims (8)

In the program method of the nonvolatile memory device, The nonvolatile memory device includes a local word line for dividing a memory cell string into a first region including a selection word line and a second region not including the selection word line. The program method is Driving word lines in the first region at a first pass voltage, and driving word lines in the second region at a second pass voltage higher than the first pass voltage; Turning off a cell transistor corresponding to the local word line after application of the first pass voltage and the second pass voltage; And Driving the select word line to a program voltage after turning off the cell transistor. The method of claim 1, After turning off the cell transistor, driving the unselected word line or the selected word line in the first region to the second pass voltage. The method of claim 1, And a local voltage higher than a ground voltage and lower than the first pass voltage is applied to the local word line to turn off the cell transistor. The method of claim 1, Driving the unselected word line in the first region to a voltage lower than the first pass voltage after the word lines in the first region are driven to the first pass voltage. In the program method of the nonvolatile memory device, The nonvolatile memory device includes a local word line for dividing a memory cell string into a first region including a selection word line and a second region not including the selection word line. The program method is Driving word lines in the first region at a first pass voltage, and driving word lines in the second region at a second pass voltage higher than the first pass voltage; After application of the first pass voltage and the second pass voltage, each of the first local voltage and the second local line and the first local word line included in the first region and adjacent to the first local word line Driving to two local voltages; And Driving the selected word line to a program voltage after application of the first local voltage and the second local voltage. The method of claim 5, Driving the unselected word line or the selected word line in the first region to the second pass voltage after application of the first local voltage and the second local voltage. The method of claim 5, The cell transistor corresponding to the first local word line is turned off by applying to the second local voltage, and the level of the second local voltage is higher than the ground voltage and lower than the first local voltage. . The method of claim 5, Driving the unselected word line in the first region to a voltage lower than the first pass voltage after the word lines in the first region are driven to the first pass voltage.

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